exynos_clock.h revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: exynos_clock.h,v 1.1.2.2 2015/12/27 12:09:32 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #ifndef _ARM_EXYNOS_CLOCK_H 30 1.1.2.2 skrll #define _ARM_EXYNOS_CLOCK_H 31 1.1.2.2 skrll 32 1.1.2.2 skrll #include <dev/clk/clk.h> 33 1.1.2.2 skrll 34 1.1.2.2 skrll enum exynos_clk_type { 35 1.1.2.2 skrll EXYNOS_CLK_FIXED, 36 1.1.2.2 skrll EXYNOS_CLK_PLL, 37 1.1.2.2 skrll EXYNOS_CLK_MUX, 38 1.1.2.2 skrll EXYNOS_CLK_DIV, 39 1.1.2.2 skrll EXYNOS_CLK_GATE 40 1.1.2.2 skrll }; 41 1.1.2.2 skrll 42 1.1.2.2 skrll struct exynos_fixed_clk { 43 1.1.2.2 skrll u_int rate; 44 1.1.2.2 skrll }; 45 1.1.2.2 skrll 46 1.1.2.2 skrll struct exynos_pll_clk { 47 1.1.2.2 skrll u_int lock_reg; 48 1.1.2.2 skrll u_int con0_reg; 49 1.1.2.2 skrll }; 50 1.1.2.2 skrll 51 1.1.2.2 skrll struct exynos_mux_clk { 52 1.1.2.2 skrll const char **parents; 53 1.1.2.2 skrll u_int nparents; 54 1.1.2.2 skrll u_int reg; 55 1.1.2.2 skrll u_int bits; 56 1.1.2.2 skrll }; 57 1.1.2.2 skrll 58 1.1.2.2 skrll struct exynos_div_clk { 59 1.1.2.2 skrll u_int reg; 60 1.1.2.2 skrll u_int bits; 61 1.1.2.2 skrll }; 62 1.1.2.2 skrll 63 1.1.2.2 skrll struct exynos_gate_clk { 64 1.1.2.2 skrll u_int reg; 65 1.1.2.2 skrll u_int bits; 66 1.1.2.2 skrll }; 67 1.1.2.2 skrll 68 1.1.2.2 skrll struct exynos_clk { 69 1.1.2.2 skrll struct clk base; /* must be first */ 70 1.1.2.2 skrll enum exynos_clk_type type; 71 1.1.2.2 skrll const char *alias; 72 1.1.2.2 skrll const char *parent; 73 1.1.2.2 skrll u_int refcnt; 74 1.1.2.2 skrll union { 75 1.1.2.2 skrll struct exynos_fixed_clk fixed; 76 1.1.2.2 skrll struct exynos_pll_clk pll; 77 1.1.2.2 skrll struct exynos_mux_clk mux; 78 1.1.2.2 skrll struct exynos_div_clk div; 79 1.1.2.2 skrll struct exynos_gate_clk gate; 80 1.1.2.2 skrll } u; 81 1.1.2.2 skrll }; 82 1.1.2.2 skrll 83 1.1.2.2 skrll #endif /* _ARM_EXYNOS_CLOCK_H */ 84
Indexes created Wed Oct 22 13:09:56 GMT 2025