exynos_ehci.c revision 1.2.18.2
1 1.2.18.2 pgoyette /* $NetBSD: exynos_ehci.c,v 1.2.18.2 2018/07/28 04:37:29 pgoyette Exp $ */ 2 1.1 marty 3 1.1 marty /*- 4 1.2.18.2 pgoyette * Copyright (c) 2015-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 1.1 marty * All rights reserved. 6 1.1 marty * 7 1.1 marty * Redistribution and use in source and binary forms, with or without 8 1.1 marty * modification, are permitted provided that the following conditions 9 1.1 marty * are met: 10 1.1 marty * 1. Redistributions of source code must retain the above copyright 11 1.1 marty * notice, this list of conditions and the following disclaimer. 12 1.1 marty * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 marty * notice, this list of conditions and the following disclaimer in the 14 1.1 marty * documentation and/or other materials provided with the distribution. 15 1.1 marty * 16 1.2.18.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.2.18.2 pgoyette * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.2.18.2 pgoyette * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.2.18.2 pgoyette * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.2.18.2 pgoyette * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.2.18.2 pgoyette * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.2.18.2 pgoyette * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.2.18.2 pgoyette * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.2.18.2 pgoyette * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.18.2 pgoyette * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.18.2 pgoyette * SUCH DAMAGE. 27 1.1 marty */ 28 1.1 marty 29 1.1 marty #include <sys/cdefs.h> 30 1.2.18.2 pgoyette __KERNEL_RCSID(0, "$NetBSD: exynos_ehci.c,v 1.2.18.2 2018/07/28 04:37:29 pgoyette Exp $"); 31 1.1 marty 32 1.1 marty #include <sys/param.h> 33 1.1 marty #include <sys/bus.h> 34 1.1 marty #include <sys/device.h> 35 1.2.18.2 pgoyette #include <sys/intr.h> 36 1.2.18.2 pgoyette #include <sys/systm.h> 37 1.2.18.2 pgoyette #include <sys/kernel.h> 38 1.1 marty 39 1.1 marty #include <dev/usb/usb.h> 40 1.1 marty #include <dev/usb/usbdi.h> 41 1.1 marty #include <dev/usb/usbdivar.h> 42 1.1 marty #include <dev/usb/usb_mem.h> 43 1.1 marty #include <dev/usb/ehcireg.h> 44 1.1 marty #include <dev/usb/ehcivar.h> 45 1.1 marty 46 1.1 marty #include <dev/fdt/fdtvar.h> 47 1.1 marty 48 1.1 marty static int exynos_ehci_match(device_t, cfdata_t, void *); 49 1.1 marty static void exynos_ehci_attach(device_t, device_t, void *); 50 1.1 marty 51 1.2.18.2 pgoyette CFATTACH_DECL2_NEW(exynos_ehci, sizeof(struct ehci_softc), 52 1.2.18.2 pgoyette exynos_ehci_match, exynos_ehci_attach, NULL, 53 1.2.18.2 pgoyette ehci_activate, NULL, ehci_childdet); 54 1.1 marty 55 1.1 marty static int 56 1.1 marty exynos_ehci_match(device_t parent, cfdata_t cf, void *aux) 57 1.1 marty { 58 1.2.18.2 pgoyette const char * const compatible[] = { 59 1.2.18.2 pgoyette "samsung,exynos4210-ehci", 60 1.2.18.2 pgoyette NULL 61 1.2.18.2 pgoyette }; 62 1.1 marty struct fdt_attach_args * const faa = aux; 63 1.2.18.2 pgoyette 64 1.1 marty return of_match_compatible(faa->faa_phandle, compatible); 65 1.1 marty } 66 1.1 marty 67 1.1 marty static void 68 1.1 marty exynos_ehci_attach(device_t parent, device_t self, void *aux) 69 1.1 marty { 70 1.2.18.2 pgoyette struct ehci_softc * const sc = device_private(self); 71 1.1 marty struct fdt_attach_args * const faa = aux; 72 1.2.18.2 pgoyette const int phandle = faa->faa_phandle; 73 1.2.18.2 pgoyette struct fdtbus_phy *phy; 74 1.2.18.2 pgoyette struct clk *clk; 75 1.2.18.2 pgoyette char intrstr[128]; 76 1.1 marty bus_addr_t addr; 77 1.1 marty bus_size_t size; 78 1.2.18.2 pgoyette int error, child; 79 1.2.18.2 pgoyette void *ih; 80 1.1 marty 81 1.2.18.2 pgoyette if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 82 1.1 marty aprint_error(": couldn't get registers\n"); 83 1.1 marty return; 84 1.1 marty } 85 1.1 marty 86 1.2.18.2 pgoyette /* Enable clocks */ 87 1.2.18.2 pgoyette clk = fdtbus_clock_get(phandle, "usbhost"); 88 1.2.18.2 pgoyette if (clk == NULL || clk_enable(clk) != 0) { 89 1.2.18.2 pgoyette aprint_error(": couldn't enable clock\n"); 90 1.2.18.2 pgoyette return; 91 1.2.18.2 pgoyette } 92 1.2.18.2 pgoyette 93 1.2.18.2 pgoyette /* Enable phys for each port */ 94 1.2.18.2 pgoyette for (child = OF_child(phandle); child; child = OF_peer(child)) { 95 1.2.18.2 pgoyette phy = fdtbus_phy_get_index(child, 0); 96 1.2.18.2 pgoyette if (phy && fdtbus_phy_enable(phy, true) != 0) 97 1.2.18.2 pgoyette aprint_error(": couldn't enable phy for %s\n", 98 1.2.18.2 pgoyette fdtbus_get_string(child, "name")); 99 1.2.18.2 pgoyette } 100 1.2.18.2 pgoyette 101 1.1 marty sc->sc_dev = self; 102 1.2 skrll sc->sc_bus.ub_hcpriv = sc; 103 1.2.18.2 pgoyette sc->sc_bus.ub_dmatag = faa->faa_dmat; 104 1.2 skrll sc->sc_bus.ub_revision = USBREV_2_0; 105 1.2.18.2 pgoyette if (of_hasprop(phandle, "has-transaction-translator")) 106 1.2.18.2 pgoyette sc->sc_flags |= EHCIF_ETTF; 107 1.2.18.2 pgoyette else 108 1.2.18.2 pgoyette sc->sc_ncomp = 1; 109 1.2.18.2 pgoyette sc->sc_size = size; 110 1.2.18.2 pgoyette sc->iot = faa->faa_bst; 111 1.2.18.2 pgoyette if (bus_space_map(sc->iot, addr, size, 0, &sc->ioh) != 0) { 112 1.2.18.2 pgoyette aprint_error(": couldn't map registers\n"); 113 1.1 marty return; 114 1.1 marty } 115 1.1 marty 116 1.2.18.2 pgoyette aprint_naive("\n"); 117 1.2.18.2 pgoyette aprint_normal(": Exynos EHCI\n"); 118 1.2.18.2 pgoyette 119 1.2.18.2 pgoyette /* Disable interrupts */ 120 1.2.18.2 pgoyette sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 121 1.2.18.2 pgoyette EOWRITE4(sc, EHCI_USBINTR, 0); 122 1.2.18.2 pgoyette 123 1.2.18.2 pgoyette if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 124 1.2.18.2 pgoyette aprint_error_dev(self, "failed to decode interrupt\n"); 125 1.2.18.2 pgoyette return; 126 1.2.18.2 pgoyette } 127 1.1 marty 128 1.2.18.2 pgoyette ih = fdtbus_intr_establish(phandle, 0, IPL_USB, FDT_INTR_MPSAFE, 129 1.2.18.2 pgoyette ehci_intr, sc); 130 1.2.18.2 pgoyette if (ih == NULL) { 131 1.2.18.2 pgoyette aprint_error_dev(self, "couldn't establish interrupt on %s\n", 132 1.2.18.2 pgoyette intrstr); 133 1.2.18.2 pgoyette return; 134 1.2.18.2 pgoyette } 135 1.2.18.2 pgoyette aprint_normal_dev(self, "interrupting on %s\n", intrstr); 136 1.1 marty 137 1.2 skrll error = ehci_init(sc); 138 1.2 skrll if (error) { 139 1.2 skrll aprint_error_dev(self, "init failed, error = %d\n", error); 140 1.1 marty return; 141 1.1 marty } 142 1.2.18.2 pgoyette 143 1.1 marty sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 144 1.1 marty } 145
Indexes created Wed Oct 29 18:09:52 GMT 2025