exynos_gpio.c revision 1.5.2.2
1 1.5.2.2 rmind /*- 2 1.5.2.2 rmind * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 1.5.2.2 rmind * All rights reserved. 4 1.5.2.2 rmind * 5 1.5.2.2 rmind * This code is derived from software contributed to The NetBSD Foundation 6 1.5.2.2 rmind * by Reinoud Zandijk 7 1.5.2.2 rmind * 8 1.5.2.2 rmind * Redistribution and use in source and binary forms, with or without 9 1.5.2.2 rmind * modification, are permitted provided that the following conditions 10 1.5.2.2 rmind * are met: 11 1.5.2.2 rmind * 1. Redistributions of source code must retain the above copyright 12 1.5.2.2 rmind * notice, this list of conditions and the following disclaimer. 13 1.5.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 14 1.5.2.2 rmind * notice, this list of conditions and the following disclaimer in the 15 1.5.2.2 rmind * documentation and/or other materials provided with the distribution. 16 1.5.2.2 rmind * 17 1.5.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 1.5.2.2 rmind * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 1.5.2.2 rmind * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 1.5.2.2 rmind * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 1.5.2.2 rmind * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 1.5.2.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 1.5.2.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 1.5.2.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 1.5.2.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 1.5.2.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 1.5.2.2 rmind * POSSIBILITY OF SUCH DAMAGE. 28 1.5.2.2 rmind */ 29 1.5.2.2 rmind 30 1.5.2.2 rmind #include "opt_exynos.h" 31 1.5.2.2 rmind #include "opt_arm_debug.h" 32 1.5.2.2 rmind #include "gpio.h" 33 1.5.2.2 rmind 34 1.5.2.2 rmind #include <sys/cdefs.h> 35 1.5.2.2 rmind __KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.5.2.2 2014/05/18 17:44:59 rmind Exp $"); 36 1.5.2.2 rmind 37 1.5.2.2 rmind #include <sys/param.h> 38 1.5.2.2 rmind #include <sys/bus.h> 39 1.5.2.2 rmind #include <sys/device.h> 40 1.5.2.2 rmind #include <sys/intr.h> 41 1.5.2.2 rmind #include <sys/systm.h> 42 1.5.2.2 rmind #include <sys/kmem.h> 43 1.5.2.2 rmind 44 1.5.2.2 rmind #include <arm/samsung/exynos_reg.h> 45 1.5.2.2 rmind #include <arm/samsung/exynos_io.h> 46 1.5.2.2 rmind #include <arm/samsung/exynos_intr.h> 47 1.5.2.2 rmind 48 1.5.2.2 rmind #include <sys/gpio.h> 49 1.5.2.2 rmind #include <dev/gpio/gpiovar.h> 50 1.5.2.2 rmind 51 1.5.2.2 rmind static int exynos_gpio_match(device_t, cfdata_t, void *); 52 1.5.2.2 rmind static void exynos_gpio_attach(device_t, device_t, void *); 53 1.5.2.2 rmind 54 1.5.2.2 rmind static int exynos_gpio_pin_read(void *, int); 55 1.5.2.2 rmind static void exynos_gpio_pin_write(void *, int, int); 56 1.5.2.2 rmind static void exynos_gpio_pin_ctl(void *, int, int); 57 1.5.2.2 rmind 58 1.5.2.2 rmind struct exynos_gpio_pin_cfg { 59 1.5.2.2 rmind uint32_t cfg; 60 1.5.2.2 rmind uint32_t pud; 61 1.5.2.2 rmind uint32_t drv; 62 1.5.2.2 rmind uint32_t conpwd; 63 1.5.2.2 rmind uint32_t pudpwd; 64 1.5.2.2 rmind }; 65 1.5.2.2 rmind 66 1.5.2.2 rmind struct exynos_gpio_pin_group { 67 1.5.2.2 rmind const char grp_name[6]; 68 1.5.2.2 rmind const bus_addr_t grp_core_offset; 69 1.5.2.2 rmind const uint8_t grp_bits; 70 1.5.2.2 rmind 71 1.5.2.2 rmind uint8_t grp_pin_mask; 72 1.5.2.2 rmind uint8_t grp_pin_inuse_mask; 73 1.5.2.2 rmind bus_space_handle_t grp_bsh; 74 1.5.2.2 rmind struct exynos_gpio_pin_cfg grp_cfg; 75 1.5.2.2 rmind struct gpio_chipset_tag grp_gc_tag; 76 1.5.2.2 rmind }; 77 1.5.2.2 rmind 78 1.5.2.2 rmind 79 1.5.2.2 rmind #define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o)) 80 1.5.2.2 rmind #define GPIO_GRP(v, s, o, n, b) \ 81 1.5.2.2 rmind { \ 82 1.5.2.2 rmind .grp_name = #n, \ 83 1.5.2.2 rmind .grp_core_offset = GPIO_REG(v,s,o), \ 84 1.5.2.2 rmind .grp_bits = b,\ 85 1.5.2.2 rmind } 86 1.5.2.2 rmind 87 1.5.2.2 rmind #ifdef EXYNOS4 88 1.5.2.2 rmind /* 89 1.5.2.2 rmind * Exynos 4412 contains 304 multi-functional input/output port pins and 164 90 1.5.2.2 rmind * memory port pins. There are 37 general port groups and two memory port 91 1.5.2.2 rmind * groups. They are: 92 1.5.2.2 rmind * 93 1.5.2.2 rmind * GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow 94 1.5.2.2 rmind * control, and/or 2xI2C 95 1.5.2.2 rmind * 96 1.5.2.2 rmind * GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM 97 1.5.2.2 rmind * 98 1.5.2.2 rmind * GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 99 1.5.2.2 rmind * and/or SPI 100 1.5.2.2 rmind * 101 1.5.2.2 rmind * GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI 102 1.5.2.2 rmind * 103 1.5.2.2 rmind * GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F, 104 1.5.2.2 rmind * HSI, and/ or Trace I/F 105 1.5.2.2 rmind * 106 1.5.2.2 rmind * GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F 107 1.5.2.2 rmind * 108 1.5.2.2 rmind * GPJ0, GPJ1: 13 in/out ports-CAM I/F 109 1.5.2.2 rmind * 110 1.5.2.2 rmind * GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC 111 1.5.2.2 rmind * (8-bit MMC)), and/or GPS debugging I/F 112 1.5.2.2 rmind * 113 1.5.2.2 rmind * GPL0, GPL1: 11 in/out ports-GPS I/F 114 1.5.2.2 rmind * 115 1.5.2.2 rmind * GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F 116 1.5.2.2 rmind * 117 1.5.2.2 rmind * GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad 118 1.5.2.2 rmind * I/F 119 1.5.2.2 rmind * 120 1.5.2.2 rmind * GPZ: 7 in/out ports-low Power I2S and/or PCM 121 1.5.2.2 rmind * 122 1.5.2.2 rmind * GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One 123 1.5.2.2 rmind * NAND) 124 1.5.2.2 rmind * 125 1.5.2.2 rmind * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information 126 1.5.2.2 rmind * about EBI configuration, refer to Chapter 5, and 6) 127 1.5.2.2 rmind * 128 1.5.2.2 rmind * MP1_0-MP1_9: 78 DRAM1 ports. NOTE: GPIO registers does not control these 129 1.5.2.2 rmind * ports. 130 1.5.2.2 rmind * 131 1.5.2.2 rmind * MP2_0-MP2_9: 78 DRAM2 ports. NOTE: GPIO registers does not control these 132 1.5.2.2 rmind * ports. 133 1.5.2.2 rmind * 134 1.5.2.2 rmind * ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK 135 1.5.2.2 rmind * 136 1.5.2.2 rmind * ETC7, ETC8 : 4 clock port for C2C 137 1.5.2.2 rmind * 138 1.5.2.2 rmind */ 139 1.5.2.2 rmind 140 1.5.2.2 rmind static struct exynos_gpio_pin_group exynos4_pin_groups[] = { 141 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0000, GPA0, 8), 142 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0020, GPA1, 6), 143 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0040, GPB, 8), 144 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0060, GPC0, 5), 145 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0080, GPC1, 5), 146 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x00A0, GPD0, 4), 147 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x00C0, GPD1, 4), 148 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0180, GPF0, 8), 149 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x01A0, GPF1, 8), 150 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x01C0, GPF2, 8), 151 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x01E0, GPF3, 8), 152 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0240, GPJ0, 8), 153 1.5.2.2 rmind GPIO_GRP(4, LEFT, 0x0260, GPJ1, 5), 154 1.5.2.2 rmind /* EXTINT skipped */ 155 1.5.2.2 rmind 156 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0040, GPK0, 8), 157 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0060, GPK1, 8), 158 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0080, GPK2, 7), 159 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x00A0, GPK3, 7), 160 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x00C0, GPL0, 7), 161 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x00E0, GPL1, 2), 162 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0100, GPL2, 8), 163 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0120, GPY0, 6), 164 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0140, GPY1, 4), 165 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0160, GPY2, 6), 166 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0180, GPY3, 8), 167 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x01A0, GPY4, 8), 168 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8), 169 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8), 170 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0200, ETC0, 6), 171 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0220, ETC6, 7), 172 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8), 173 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7), 174 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5), 175 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x02C0, GPM3, 8), 176 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x02E0, GPM4, 8), 177 1.5.2.2 rmind /* EXTINT skipped */ 178 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0C00, GPX0, 8), 179 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0C20, GPX1, 8), 180 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0C40, GPX2, 8), 181 1.5.2.2 rmind GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8), 182 1.5.2.2 rmind /* EXTINT skipped */ 183 1.5.2.2 rmind 184 1.5.2.2 rmind GPIO_GRP(4, I2S0, 0x0000, GPZ, 8), 185 1.5.2.2 rmind /* EXTINT skipped */ 186 1.5.2.2 rmind 187 1.5.2.2 rmind GPIO_GRP(4, C2C, 0x0000, GPV0, 8), 188 1.5.2.2 rmind GPIO_GRP(4, C2C, 0x0020, GPV1, 8), 189 1.5.2.2 rmind GPIO_GRP(4, C2C, 0x0040, ETC7, 2), 190 1.5.2.2 rmind GPIO_GRP(4, C2C, 0x0060, GPV2, 8), 191 1.5.2.2 rmind GPIO_GRP(4, C2C, 0x0080, GPV3, 8), 192 1.5.2.2 rmind GPIO_GRP(4, C2C, 0x00A0, ETC8, 2), 193 1.5.2.2 rmind GPIO_GRP(4, C2C, 0x00C0, GPV4, 2), 194 1.5.2.2 rmind /* EXTINT skipped */ 195 1.5.2.2 rmind }; 196 1.5.2.2 rmind #endif 197 1.5.2.2 rmind 198 1.5.2.2 rmind 199 1.5.2.2 rmind #ifdef EXYNOS5 200 1.5.2.2 rmind static struct exynos_gpio_pin_group exynos5_pin_groups[] = { 201 1.5.2.2 rmind }; 202 1.5.2.2 rmind #endif 203 1.5.2.2 rmind 204 1.5.2.2 rmind 205 1.5.2.2 rmind struct exynos_gpio_softc { 206 1.5.2.2 rmind device_t sc_dev; 207 1.5.2.2 rmind bus_space_tag_t sc_bst; 208 1.5.2.2 rmind bus_space_handle_t sc_bsh; 209 1.5.2.2 rmind }; 210 1.5.2.2 rmind 211 1.5.2.2 rmind 212 1.5.2.2 rmind /* force these structures in DATA segment */ 213 1.5.2.2 rmind static struct exynos_gpio_pin_group *exynos_pin_groups = NULL; 214 1.5.2.2 rmind static int exynos_n_pin_groups = 0; 215 1.5.2.2 rmind 216 1.5.2.2 rmind static struct exynos_gpio_softc exynos_gpio_sc = {}; 217 1.5.2.2 rmind 218 1.5.2.2 rmind 219 1.5.2.2 rmind CFATTACH_DECL_NEW(exynos_gpio, sizeof(struct exynos_gpio_softc), 220 1.5.2.2 rmind exynos_gpio_match, exynos_gpio_attach, NULL, NULL); 221 1.5.2.2 rmind 222 1.5.2.2 rmind 223 1.5.2.2 rmind static int 224 1.5.2.2 rmind exynos_gpio_match(device_t parent, cfdata_t cf, void *aux) 225 1.5.2.2 rmind { 226 1.5.2.2 rmind struct exyo_attach_args * const exyoaa = aux; 227 1.5.2.2 rmind struct exyo_locators *loc = &exyoaa->exyo_loc; 228 1.5.2.2 rmind 229 1.5.2.2 rmind /* no locators expected */ 230 1.5.2.2 rmind KASSERT(loc->loc_offset == 0); 231 1.5.2.2 rmind KASSERT(loc->loc_size == 0); 232 1.5.2.2 rmind KASSERT(loc->loc_port == EXYOCF_PORT_DEFAULT); 233 1.5.2.2 rmind 234 1.5.2.2 rmind /* there can only be one */ 235 1.5.2.2 rmind if (exynos_gpio_sc.sc_dev != NULL) 236 1.5.2.2 rmind return 0; 237 1.5.2.2 rmind return 1; 238 1.5.2.2 rmind } 239 1.5.2.2 rmind 240 1.5.2.2 rmind 241 1.5.2.2 rmind #if NGPIO > 0 242 1.5.2.2 rmind static void 243 1.5.2.2 rmind exynos_gpio_config_pins(device_t self) 244 1.5.2.2 rmind { 245 1.5.2.2 rmind struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 246 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 247 1.5.2.2 rmind struct gpiobus_attach_args gba; 248 1.5.2.2 rmind gpio_pin_t *pin, *pins; 249 1.5.2.2 rmind size_t pin_count = 0; 250 1.5.2.2 rmind int i, bit, mask, pincaps, data; 251 1.5.2.2 rmind 252 1.5.2.2 rmind if (exynos_n_pin_groups == 0) 253 1.5.2.2 rmind return; 254 1.5.2.2 rmind 255 1.5.2.2 rmind /* find out how many pins we can offer */ 256 1.5.2.2 rmind pin_count = 0; 257 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 258 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 259 1.5.2.2 rmind mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 260 1.5.2.2 rmind pin_count += popcount32(mask); 261 1.5.2.2 rmind } 262 1.5.2.2 rmind 263 1.5.2.2 rmind /* if no pins available, don't proceed */ 264 1.5.2.2 rmind if (pin_count == 0) 265 1.5.2.2 rmind return; 266 1.5.2.2 rmind 267 1.5.2.2 rmind /* allocate pin data */ 268 1.5.2.2 rmind pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count, KM_SLEEP); 269 1.5.2.2 rmind KASSERT(pins); 270 1.5.2.2 rmind 271 1.5.2.2 rmind pincaps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 272 1.5.2.2 rmind GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 273 1.5.2.2 rmind 274 1.5.2.2 rmind /* add all pins */ 275 1.5.2.2 rmind pin = pins; 276 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 277 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 278 1.5.2.2 rmind mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 279 1.5.2.2 rmind if (mask == 0) 280 1.5.2.2 rmind continue; 281 1.5.2.2 rmind gba.gba_gc = &grp->grp_gc_tag; 282 1.5.2.2 rmind gba.gba_pins = pin; 283 1.5.2.2 rmind data = bus_space_read_1(sc->sc_bst, grp->grp_bsh, 284 1.5.2.2 rmind EXYNOS_GPIO_DAT); 285 1.5.2.2 rmind for (bit = 0; mask != 0; mask >>= 1, data >>= 1, bit++) { 286 1.5.2.2 rmind if (mask & 1) { 287 1.5.2.2 rmind pin->pin_num = bit + (i << 3); 288 1.5.2.2 rmind pin->pin_caps = pincaps; 289 1.5.2.2 rmind pin->pin_flags = pincaps; 290 1.5.2.2 rmind pin->pin_state = (data & 1) != 0; 291 1.5.2.2 rmind pin++; 292 1.5.2.2 rmind } 293 1.5.2.2 rmind } 294 1.5.2.2 rmind gba.gba_npins = pin - gba.gba_pins; 295 1.5.2.2 rmind config_found_ia(self, "gpiobus", &gba, gpiobus_print); 296 1.5.2.2 rmind } 297 1.5.2.2 rmind } 298 1.5.2.2 rmind #endif 299 1.5.2.2 rmind 300 1.5.2.2 rmind 301 1.5.2.2 rmind static void 302 1.5.2.2 rmind exynos_gpio_attach(device_t parent, device_t self, void *aux) 303 1.5.2.2 rmind { 304 1.5.2.2 rmind struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 305 1.5.2.2 rmind struct exyo_attach_args * const exyoaa = aux; 306 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 307 1.5.2.2 rmind prop_dictionary_t dict = device_properties(self); 308 1.5.2.2 rmind uint32_t nc; 309 1.5.2.2 rmind char scrap[16]; 310 1.5.2.2 rmind int i; 311 1.5.2.2 rmind 312 1.5.2.2 rmind /* construct softc */ 313 1.5.2.2 rmind sc->sc_dev = self; 314 1.5.2.2 rmind 315 1.5.2.2 rmind /* we use the core bushandle here */ 316 1.5.2.2 rmind sc->sc_bst = exyoaa->exyo_core_bst; 317 1.5.2.2 rmind sc->sc_bsh = exyoaa->exyo_core_bsh; 318 1.5.2.2 rmind 319 1.5.2.2 rmind exynos_gpio_bootstrap(); 320 1.5.2.2 rmind if (exynos_n_pin_groups == 0) { 321 1.5.2.2 rmind printf(": disabled, no pins defined\n"); 322 1.5.2.2 rmind return; 323 1.5.2.2 rmind } 324 1.5.2.2 rmind 325 1.5.2.2 rmind KASSERT(exynos_pin_groups); 326 1.5.2.2 rmind KASSERT(exynos_n_pin_groups); 327 1.5.2.2 rmind 328 1.5.2.2 rmind aprint_naive("\n"); 329 1.5.2.2 rmind aprint_normal("\n"); 330 1.5.2.2 rmind 331 1.5.2.2 rmind /* go trough all pin groups */ 332 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 333 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 334 1.5.2.2 rmind snprintf(scrap, sizeof(scrap), "nc-%s", grp->grp_name); 335 1.5.2.2 rmind if (prop_dictionary_get_uint32(dict, scrap, &nc)) { 336 1.5.2.2 rmind KASSERT((~grp->grp_pin_mask & nc) == 0); 337 1.5.2.2 rmind /* switch off the pins we have signalled NC */ 338 1.5.2.2 rmind grp->grp_pin_mask &= ~nc; 339 1.5.2.2 rmind #if 0 340 1.5.2.2 rmind printf("%s: %-4s inuse_mask %02x, pin_mask %02x\n", 341 1.5.2.2 rmind __func__, grp->grp_name, 342 1.5.2.2 rmind grp->grp_pin_inuse_mask, grp->grp_pin_mask); 343 1.5.2.2 rmind #endif 344 1.5.2.2 rmind } 345 1.5.2.2 rmind } 346 1.5.2.2 rmind 347 1.5.2.2 rmind #if NGPIO > 0 348 1.5.2.2 rmind config_defer(self, exynos_gpio_config_pins); 349 1.5.2.2 rmind #endif 350 1.5.2.2 rmind } 351 1.5.2.2 rmind 352 1.5.2.2 rmind 353 1.5.2.2 rmind /* pin access functions */ 354 1.5.2.2 rmind static u_int 355 1.5.2.2 rmind exynos_gpio_get_pin_func(const struct exynos_gpio_pin_cfg *cfg, int pin) 356 1.5.2.2 rmind { 357 1.5.2.2 rmind const u_int shift = (pin & 7) << 2; 358 1.5.2.2 rmind 359 1.5.2.2 rmind return (cfg->cfg >> shift) & 0x0f; 360 1.5.2.2 rmind } 361 1.5.2.2 rmind 362 1.5.2.2 rmind 363 1.5.2.2 rmind static void 364 1.5.2.2 rmind exynos_gpio_set_pin_func(struct exynos_gpio_pin_cfg *cfg, 365 1.5.2.2 rmind int pin, int func) 366 1.5.2.2 rmind { 367 1.5.2.2 rmind const u_int shift = (pin & 7) << 2; 368 1.5.2.2 rmind 369 1.5.2.2 rmind cfg->cfg &= ~(0x0f << shift); 370 1.5.2.2 rmind cfg->cfg |= func << shift; 371 1.5.2.2 rmind } 372 1.5.2.2 rmind 373 1.5.2.2 rmind 374 1.5.2.2 rmind static void 375 1.5.2.2 rmind exynos_gpio_set_pin_pull(struct exynos_gpio_pin_cfg *cfg, int pin, int pull) 376 1.5.2.2 rmind { 377 1.5.2.2 rmind const u_int shift = (pin & 7) << 1; 378 1.5.2.2 rmind 379 1.5.2.2 rmind cfg->pud &= ~(0x3 << shift); 380 1.5.2.2 rmind cfg->pud |= pull << shift; 381 1.5.2.2 rmind } 382 1.5.2.2 rmind 383 1.5.2.2 rmind 384 1.5.2.2 rmind static int 385 1.5.2.2 rmind exynos_gpio_pin_read(void *cookie, int pin) 386 1.5.2.2 rmind { 387 1.5.2.2 rmind struct exynos_gpio_pin_group * const grp = cookie; 388 1.5.2.2 rmind 389 1.5.2.2 rmind KASSERT(pin < grp->grp_bits); 390 1.5.2.2 rmind return (bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 391 1.5.2.2 rmind EXYNOS_GPIO_DAT) >> pin) & 1; 392 1.5.2.2 rmind } 393 1.5.2.2 rmind 394 1.5.2.2 rmind 395 1.5.2.2 rmind static void 396 1.5.2.2 rmind exynos_gpio_pin_write(void *cookie, int pin, int value) 397 1.5.2.2 rmind { 398 1.5.2.2 rmind struct exynos_gpio_pin_group * const grp = cookie; 399 1.5.2.2 rmind int val; 400 1.5.2.2 rmind 401 1.5.2.2 rmind KASSERT(pin < grp->grp_bits); 402 1.5.2.2 rmind val = bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 403 1.5.2.2 rmind EXYNOS_GPIO_DAT); 404 1.5.2.2 rmind val &= ~__BIT(pin); 405 1.5.2.2 rmind if (value) 406 1.5.2.2 rmind val |= __BIT(pin); 407 1.5.2.2 rmind bus_space_write_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 408 1.5.2.2 rmind EXYNOS_GPIO_DAT, val); 409 1.5.2.2 rmind } 410 1.5.2.2 rmind 411 1.5.2.2 rmind 412 1.5.2.2 rmind static void 413 1.5.2.2 rmind exynos_gpio_update_cfg_regs(struct exynos_gpio_pin_group *grp, 414 1.5.2.2 rmind const struct exynos_gpio_pin_cfg *ncfg) 415 1.5.2.2 rmind { 416 1.5.2.2 rmind bus_space_tag_t bst = &exynos_bs_tag; 417 1.5.2.2 rmind 418 1.5.2.2 rmind if (grp->grp_cfg.cfg != ncfg->cfg) { 419 1.5.2.2 rmind bus_space_write_4(bst, grp->grp_bsh, 420 1.5.2.2 rmind EXYNOS_GPIO_CON, ncfg->cfg); 421 1.5.2.2 rmind grp->grp_cfg.cfg = ncfg->cfg; 422 1.5.2.2 rmind } 423 1.5.2.2 rmind if (grp->grp_cfg.pud != ncfg->pud) { 424 1.5.2.2 rmind bus_space_write_4(bst, grp->grp_bsh, 425 1.5.2.2 rmind EXYNOS_GPIO_PUD, ncfg->pud); 426 1.5.2.2 rmind grp->grp_cfg.pud = ncfg->pud; 427 1.5.2.2 rmind } 428 1.5.2.2 rmind 429 1.5.2.2 rmind /* the following attributes are not yet setable */ 430 1.5.2.2 rmind #if 0 431 1.5.2.2 rmind if (grp->grp_cfg.drv != ncfg->drv) { 432 1.5.2.2 rmind bus_space_write_4(bst, grp->grp_bsh, 433 1.5.2.2 rmind EXYNOS_GPIO_DRV, ncfg->drv); 434 1.5.2.2 rmind grp->grp_cfg.drv = ncfg->drv; 435 1.5.2.2 rmind } 436 1.5.2.2 rmind if (grp->grp_cfg.conpwd != ncfg->conpwd) { 437 1.5.2.2 rmind bus_space_write_4(bst, grp->grp_bsh, 438 1.5.2.2 rmind EXYNOS_GPIO_CONPWD, ncfg->conpwd); 439 1.5.2.2 rmind grp->grp_cfg.conpwd = ncfg->conpwd; 440 1.5.2.2 rmind } 441 1.5.2.2 rmind if (grp->grp_cfg.pudpwd != ncfg->pudpwd) { 442 1.5.2.2 rmind bus_space_write_4(bst, grp->grp_bsh, 443 1.5.2.2 rmind EXYNOS_GPIO_PUDPWD, ncfg->pudpwd); 444 1.5.2.2 rmind grp->grp_cfg.pudpwd = ncfg->pudpwd; 445 1.5.2.2 rmind } 446 1.5.2.2 rmind #endif 447 1.5.2.2 rmind } 448 1.5.2.2 rmind 449 1.5.2.2 rmind 450 1.5.2.2 rmind static void 451 1.5.2.2 rmind exynos_gpio_pin_ctl(void *cookie, int pin, int flags) 452 1.5.2.2 rmind { 453 1.5.2.2 rmind struct exynos_gpio_pin_group * const grp = cookie; 454 1.5.2.2 rmind struct exynos_gpio_pin_cfg ncfg = grp->grp_cfg; 455 1.5.2.2 rmind int pull; 456 1.5.2.2 rmind 457 1.5.2.2 rmind /* honour pullup requests */ 458 1.5.2.2 rmind pull = EXYNOS_GPIO_PIN_FLOAT; 459 1.5.2.2 rmind if (flags & GPIO_PIN_PULLUP) 460 1.5.2.2 rmind pull = EXYNOS_GPIO_PIN_PULL_UP; 461 1.5.2.2 rmind if (flags & GPIO_PIN_PULLDOWN) 462 1.5.2.2 rmind pull = EXYNOS_GPIO_PIN_PULL_DOWN; 463 1.5.2.2 rmind exynos_gpio_set_pin_pull(&ncfg, pin, pull); 464 1.5.2.2 rmind 465 1.5.2.2 rmind /* honour i/o */ 466 1.5.2.2 rmind if (flags & GPIO_PIN_INPUT) 467 1.5.2.2 rmind exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_INPUT); 468 1.5.2.2 rmind if (flags & GPIO_PIN_OUTPUT) 469 1.5.2.2 rmind exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_OUTPUT); 470 1.5.2.2 rmind 471 1.5.2.2 rmind /* update any config registers that changed */ 472 1.5.2.2 rmind exynos_gpio_update_cfg_regs(grp, &ncfg); 473 1.5.2.2 rmind } 474 1.5.2.2 rmind 475 1.5.2.2 rmind 476 1.5.2.2 rmind bool 477 1.5.2.2 rmind exynos_gpio_pinset_available(const struct exynos_gpio_pinset *req) 478 1.5.2.2 rmind { 479 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 480 1.5.2.2 rmind int i, n, inuse; 481 1.5.2.2 rmind 482 1.5.2.2 rmind KASSERT(req); 483 1.5.2.2 rmind if (exynos_n_pin_groups == 0) 484 1.5.2.2 rmind return false; 485 1.5.2.2 rmind 486 1.5.2.2 rmind /* we need a pinset group */ 487 1.5.2.2 rmind if (strlen(req->pinset_group) == 0) 488 1.5.2.2 rmind return false; 489 1.5.2.2 rmind 490 1.5.2.2 rmind /* determine which group is requested */ 491 1.5.2.2 rmind grp = NULL; 492 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 493 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 494 1.5.2.2 rmind if (strcmp(req->pinset_group, grp->grp_name) == 0) 495 1.5.2.2 rmind break; 496 1.5.2.2 rmind } 497 1.5.2.2 rmind /* found? */ 498 1.5.2.2 rmind if (i == exynos_n_pin_groups) 499 1.5.2.2 rmind return false; 500 1.5.2.2 rmind KASSERT(grp); 501 1.5.2.2 rmind 502 1.5.2.2 rmind /* fail unconnected pins */ 503 1.5.2.2 rmind if (req->pinset_mask & ~grp->grp_pin_mask) 504 1.5.2.2 rmind return false; 505 1.5.2.2 rmind 506 1.5.2.2 rmind /* if none in use, they are available */ 507 1.5.2.2 rmind if (req->pinset_mask & ~grp->grp_pin_inuse_mask) 508 1.5.2.2 rmind return true; 509 1.5.2.2 rmind 510 1.5.2.2 rmind /* OK, so some are in use; now see if the request is compatible */ 511 1.5.2.2 rmind inuse = req->pinset_mask & grp->grp_pin_inuse_mask; 512 1.5.2.2 rmind for (i = 0; inuse; i++, inuse >>= 1) { 513 1.5.2.2 rmind /* try to be smart by skipping zero's */ 514 1.5.2.2 rmind n = ffs(inuse) -1; 515 1.5.2.2 rmind i += n; 516 1.5.2.2 rmind inuse >>= n; 517 1.5.2.2 rmind /* this pin is in use, check its usage */ 518 1.5.2.2 rmind if (exynos_gpio_get_pin_func(&grp->grp_cfg, i) != req->pinset_func) 519 1.5.2.2 rmind return false; 520 1.5.2.2 rmind } 521 1.5.2.2 rmind 522 1.5.2.2 rmind /* seems to be OK */ 523 1.5.2.2 rmind return true; 524 1.5.2.2 rmind } 525 1.5.2.2 rmind 526 1.5.2.2 rmind 527 1.5.2.2 rmind void 528 1.5.2.2 rmind exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *req) 529 1.5.2.2 rmind { 530 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 531 1.5.2.2 rmind struct exynos_gpio_pin_cfg ncfg; 532 1.5.2.2 rmind int i, n, todo; 533 1.5.2.2 rmind 534 1.5.2.2 rmind KASSERT(req); 535 1.5.2.2 rmind KASSERT(exynos_gpio_pinset_available(req)); 536 1.5.2.2 rmind 537 1.5.2.2 rmind /* determine which group is requested */ 538 1.5.2.2 rmind grp = NULL; 539 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 540 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 541 1.5.2.2 rmind if (strcmp(req->pinset_group, grp->grp_name) == 0) 542 1.5.2.2 rmind break; 543 1.5.2.2 rmind } 544 1.5.2.2 rmind KASSERT(grp); 545 1.5.2.2 rmind 546 1.5.2.2 rmind /* check if all the pins have the right function */ 547 1.5.2.2 rmind if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0) 548 1.5.2.2 rmind return; 549 1.5.2.2 rmind 550 1.5.2.2 rmind /* copy current config for update routine */ 551 1.5.2.2 rmind ncfg = grp->grp_cfg; 552 1.5.2.2 rmind 553 1.5.2.2 rmind /* update the function of each pin that is not in use */ 554 1.5.2.2 rmind todo = req->pinset_mask & grp->grp_pin_inuse_mask; 555 1.5.2.2 rmind for (i = 0; todo; i++, todo >>= 1) { 556 1.5.2.2 rmind /* try to be smart by skipping zero's */ 557 1.5.2.2 rmind n = ffs(todo) -1; 558 1.5.2.2 rmind i += n; 559 1.5.2.2 rmind todo >>= n; 560 1.5.2.2 rmind /* change the function of this pin */ 561 1.5.2.2 rmind exynos_gpio_set_pin_func(&ncfg, i, req->pinset_func); 562 1.5.2.2 rmind } 563 1.5.2.2 rmind 564 1.5.2.2 rmind /* update config registers */ 565 1.5.2.2 rmind exynos_gpio_update_cfg_regs(grp, &ncfg); 566 1.5.2.2 rmind 567 1.5.2.2 rmind /* mark pins in use */ 568 1.5.2.2 rmind grp->grp_pin_inuse_mask |= req->pinset_mask; 569 1.5.2.2 rmind } 570 1.5.2.2 rmind 571 1.5.2.2 rmind 572 1.5.2.2 rmind /* get a pindata structure from a pinset structure */ 573 1.5.2.2 rmind void 574 1.5.2.2 rmind exynos_gpio_pinset_to_pindata(const struct exynos_gpio_pinset *req, int pinnr, 575 1.5.2.2 rmind struct exynos_gpio_pindata *pd) 576 1.5.2.2 rmind { 577 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 578 1.5.2.2 rmind int i; 579 1.5.2.2 rmind 580 1.5.2.2 rmind KASSERT(req); 581 1.5.2.2 rmind KASSERT(pd); 582 1.5.2.2 rmind KASSERT(req->pinset_mask & __BIT(pinnr)); 583 1.5.2.2 rmind 584 1.5.2.2 rmind /* determine which group is requested */ 585 1.5.2.2 rmind grp = NULL; 586 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 587 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 588 1.5.2.2 rmind if (strcmp(req->pinset_group, grp->grp_name) == 0) 589 1.5.2.2 rmind break; 590 1.5.2.2 rmind } 591 1.5.2.2 rmind KASSERT(grp); 592 1.5.2.2 rmind 593 1.5.2.2 rmind pd->pd_gc = &grp->grp_gc_tag; 594 1.5.2.2 rmind pd->pd_pin = pinnr; 595 1.5.2.2 rmind } 596 1.5.2.2 rmind 597 1.5.2.2 rmind 598 1.5.2.2 rmind /* XXXRPZ This release doesn't grock multiple usages! */ 599 1.5.2.2 rmind void 600 1.5.2.2 rmind exynos_gpio_pinset_release(const struct exynos_gpio_pinset *req) 601 1.5.2.2 rmind { 602 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 603 1.5.2.2 rmind int i; 604 1.5.2.2 rmind 605 1.5.2.2 rmind KASSERT(!exynos_gpio_pinset_available(req)); 606 1.5.2.2 rmind 607 1.5.2.2 rmind /* determine which group is requested */ 608 1.5.2.2 rmind grp = NULL; 609 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 610 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 611 1.5.2.2 rmind if (strcmp(req->pinset_group, grp->grp_name) == 0) 612 1.5.2.2 rmind break; 613 1.5.2.2 rmind } 614 1.5.2.2 rmind KASSERT(grp); 615 1.5.2.2 rmind 616 1.5.2.2 rmind /* bluntly mark as not being in use */ 617 1.5.2.2 rmind grp->grp_pin_inuse_mask &= ~req->pinset_mask; 618 1.5.2.2 rmind } 619 1.5.2.2 rmind 620 1.5.2.2 rmind 621 1.5.2.2 rmind /* 622 1.5.2.2 rmind * name convention : 623 1.5.2.2 rmind * pin = <func><groupname><pinnr>[<pud>] 624 1.5.2.2 rmind * func = '<' | '>' 625 1.5.2.2 rmind * pinnr = '['['0'-'7']']' 626 1.5.2.2 rmind * pud = 'F' | 'U' | 'D' 627 1.5.2.2 rmind * 628 1.5.2.2 rmind * example "<GPC1[0]", ">GPB[0]" 629 1.5.2.2 rmind */ 630 1.5.2.2 rmind 631 1.5.2.2 rmind bool 632 1.5.2.2 rmind exynos_gpio_pin_reserve(const char *name, struct exynos_gpio_pindata *pd) 633 1.5.2.2 rmind { 634 1.5.2.2 rmind struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 635 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 636 1.5.2.2 rmind struct exynos_gpio_pin_cfg ncfg; 637 1.5.2.2 rmind prop_dictionary_t dict = device_properties(sc->sc_dev); 638 1.5.2.2 rmind const char *pin_data; 639 1.5.2.2 rmind char grp_name[15], *pos; 640 1.5.2.2 rmind int func, pud, pinnr; 641 1.5.2.2 rmind int pi, i; 642 1.5.2.2 rmind 643 1.5.2.2 rmind if (exynos_n_pin_groups == 0) 644 1.5.2.2 rmind return false; 645 1.5.2.2 rmind 646 1.5.2.2 rmind /* do we have a named pin description? */ 647 1.5.2.2 rmind if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data)) 648 1.5.2.2 rmind return false; 649 1.5.2.2 rmind 650 1.5.2.2 rmind KASSERT(strlen(pin_data) < 10); 651 1.5.2.2 rmind if (!(pin_data[0] == '>' || pin_data[0] == '<')) { 652 1.5.2.2 rmind printf("%s: malformed pin data in '%s', missing direction\n", 653 1.5.2.2 rmind __func__, pin_data); 654 1.5.2.2 rmind return false; 655 1.5.2.2 rmind } 656 1.5.2.2 rmind 657 1.5.2.2 rmind func = (pin_data[0] == '<') ? 658 1.5.2.2 rmind EXYNOS_GPIO_FUNC_INPUT : EXYNOS_GPIO_FUNC_OUTPUT; 659 1.5.2.2 rmind 660 1.5.2.2 rmind /* find groupname */ 661 1.5.2.2 rmind pi = 1; pos = grp_name; 662 1.5.2.2 rmind while (pin_data[pi] && pin_data[pi] != '[') { 663 1.5.2.2 rmind *pos++ = pin_data[pi++]; 664 1.5.2.2 rmind } 665 1.5.2.2 rmind if (pin_data[pi] != '[') { 666 1.5.2.2 rmind printf("%s: malformed pin data in '%s', missing '['\n", 667 1.5.2.2 rmind __func__, pin_data); 668 1.5.2.2 rmind return false; 669 1.5.2.2 rmind } 670 1.5.2.2 rmind *pos++ = (char) 0; 671 1.5.2.2 rmind 672 1.5.2.2 rmind /* skip '[' */ 673 1.5.2.2 rmind pi++; 674 1.5.2.2 rmind if (!(pin_data[pi] >= '0' && pin_data[pi] <= '7')) { 675 1.5.2.2 rmind printf("%s: malformed pin data in '%s', bad pin number\n", 676 1.5.2.2 rmind __func__, pin_data); 677 1.5.2.2 rmind return false; 678 1.5.2.2 rmind } 679 1.5.2.2 rmind pinnr = pin_data[pi] - '0'; 680 1.5.2.2 rmind 681 1.5.2.2 rmind /* skip digit */ 682 1.5.2.2 rmind pi++; 683 1.5.2.2 rmind if ((pin_data[pi] != ']')) { 684 1.5.2.2 rmind printf("%s: malformed pin data in '%s', missing end ']'\n", 685 1.5.2.2 rmind __func__, pin_data); 686 1.5.2.2 rmind return false; 687 1.5.2.2 rmind } 688 1.5.2.2 rmind 689 1.5.2.2 rmind /* skip ']' */ 690 1.5.2.2 rmind pi++; 691 1.5.2.2 rmind pud = EXYNOS_GPIO_PIN_FLOAT; 692 1.5.2.2 rmind switch (tolower(pin_data[pi])) { 693 1.5.2.2 rmind case (char) 0: 694 1.5.2.2 rmind break; 695 1.5.2.2 rmind case 'f': 696 1.5.2.2 rmind pud = EXYNOS_GPIO_PIN_FLOAT; 697 1.5.2.2 rmind break; 698 1.5.2.2 rmind case 'u': 699 1.5.2.2 rmind pud = EXYNOS_GPIO_PIN_PULL_UP; 700 1.5.2.2 rmind break; 701 1.5.2.2 rmind case 'd': 702 1.5.2.2 rmind pud = EXYNOS_GPIO_PIN_PULL_DOWN; 703 1.5.2.2 rmind break; 704 1.5.2.2 rmind default: 705 1.5.2.2 rmind printf("%s: malformed pin data in '%s', expecting " 706 1.5.2.2 rmind "optional pull up/down or float argument\n", 707 1.5.2.2 rmind __func__, pin_data); 708 1.5.2.2 rmind return false; 709 1.5.2.2 rmind } 710 1.5.2.2 rmind 711 1.5.2.2 rmind /* determine which group is requested */ 712 1.5.2.2 rmind grp = NULL; 713 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 714 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 715 1.5.2.2 rmind if (strcmp(grp_name, grp->grp_name) == 0) 716 1.5.2.2 rmind break; 717 1.5.2.2 rmind } 718 1.5.2.2 rmind 719 1.5.2.2 rmind /* found? */ 720 1.5.2.2 rmind if (i >= exynos_n_pin_groups) { 721 1.5.2.2 rmind printf("%s: malformed pin data in '%s', " 722 1.5.2.2 rmind "no such pin group name\n", 723 1.5.2.2 rmind __func__, grp_name); 724 1.5.2.2 rmind return false; 725 1.5.2.2 rmind } 726 1.5.2.2 rmind KASSERT(grp); 727 1.5.2.2 rmind 728 1.5.2.2 rmind KASSERT(pinnr < grp->grp_bits); 729 1.5.2.2 rmind KASSERT(grp->grp_pin_mask & __BIT(pinnr)); 730 1.5.2.2 rmind KASSERT((grp->grp_pin_inuse_mask & __BIT(pinnr)) == 0); 731 1.5.2.2 rmind 732 1.5.2.2 rmind /* update our pin configuration */ 733 1.5.2.2 rmind ncfg = grp->grp_cfg; 734 1.5.2.2 rmind exynos_gpio_set_pin_func(&ncfg, pinnr, func); 735 1.5.2.2 rmind exynos_gpio_set_pin_pull(&ncfg, pinnr, pud); 736 1.5.2.2 rmind exynos_gpio_update_cfg_regs(grp, &ncfg); 737 1.5.2.2 rmind 738 1.5.2.2 rmind grp->grp_pin_inuse_mask |= __BIT(pinnr); 739 1.5.2.2 rmind grp->grp_pin_mask &= ~__BIT(pinnr); 740 1.5.2.2 rmind 741 1.5.2.2 rmind pd->pd_gc = &grp->grp_gc_tag; 742 1.5.2.2 rmind pd->pd_pin = pinnr; 743 1.5.2.2 rmind 744 1.5.2.2 rmind return true; 745 1.5.2.2 rmind } 746 1.5.2.2 rmind 747 1.5.2.2 rmind 748 1.5.2.2 rmind /* bootstrapping */ 749 1.5.2.2 rmind void 750 1.5.2.2 rmind exynos_gpio_bootstrap(void) 751 1.5.2.2 rmind { 752 1.5.2.2 rmind bus_space_tag_t bst = &exynos_bs_tag; 753 1.5.2.2 rmind struct exynos_gpio_pin_group *grp; 754 1.5.2.2 rmind struct gpio_chipset_tag *gc_tag; 755 1.5.2.2 rmind int i; 756 1.5.2.2 rmind 757 1.5.2.2 rmind /* determine what we're running on */ 758 1.5.2.2 rmind #ifdef EXYNOS4 759 1.5.2.2 rmind if (IS_EXYNOS4_P()) { 760 1.5.2.2 rmind exynos_pin_groups = exynos4_pin_groups; 761 1.5.2.2 rmind exynos_n_pin_groups = __arraycount(exynos4_pin_groups); 762 1.5.2.2 rmind } 763 1.5.2.2 rmind #endif 764 1.5.2.2 rmind #ifdef EXYNOS5 765 1.5.2.2 rmind if (IS_EXYNOS5_P()) { 766 1.5.2.2 rmind exynos_pin_groups = exynos5_pin_groups; 767 1.5.2.2 rmind exynos_n_pin_groups = __arraycount(exynos5_pin_groups); 768 1.5.2.2 rmind } 769 1.5.2.2 rmind #endif 770 1.5.2.2 rmind 771 1.5.2.2 rmind if (exynos_n_pin_groups == 0) 772 1.5.2.2 rmind return; 773 1.5.2.2 rmind 774 1.5.2.2 rmind /* init groups */ 775 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 776 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 777 1.5.2.2 rmind gc_tag = &grp->grp_gc_tag; 778 1.5.2.2 rmind 779 1.5.2.2 rmind bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 780 1.5.2.2 rmind grp->grp_core_offset, EXYNOS_GPIO_GRP_SIZE, 781 1.5.2.2 rmind &grp->grp_bsh); 782 1.5.2.2 rmind KASSERT(&grp->grp_bsh); 783 1.5.2.2 rmind 784 1.5.2.2 rmind grp->grp_pin_mask = __BIT(grp->grp_bits) - 1; 785 1.5.2.2 rmind grp->grp_pin_inuse_mask = 0; 786 1.5.2.2 rmind 787 1.5.2.2 rmind gc_tag->gp_cookie = grp; 788 1.5.2.2 rmind gc_tag->gp_pin_read = exynos_gpio_pin_read; 789 1.5.2.2 rmind gc_tag->gp_pin_write = exynos_gpio_pin_write; 790 1.5.2.2 rmind gc_tag->gp_pin_ctl = exynos_gpio_pin_ctl; 791 1.5.2.2 rmind 792 1.5.2.2 rmind /* read in our initial settings */ 793 1.5.2.2 rmind grp->grp_cfg.cfg = bus_space_read_4(bst, grp->grp_bsh, 794 1.5.2.2 rmind EXYNOS_GPIO_CON); 795 1.5.2.2 rmind grp->grp_cfg.pud = bus_space_read_4(bst, grp->grp_bsh, 796 1.5.2.2 rmind EXYNOS_GPIO_PUD); 797 1.5.2.2 rmind grp->grp_cfg.drv = bus_space_read_4(bst, grp->grp_bsh, 798 1.5.2.2 rmind EXYNOS_GPIO_DRV); 799 1.5.2.2 rmind grp->grp_cfg.conpwd = bus_space_read_4(bst, grp->grp_bsh, 800 1.5.2.2 rmind EXYNOS_GPIO_CONPWD); 801 1.5.2.2 rmind grp->grp_cfg.pudpwd = bus_space_read_4(bst, grp->grp_bsh, 802 1.5.2.2 rmind EXYNOS_GPIO_PUDPWD); 803 1.5.2.2 rmind 804 1.5.2.2 rmind /* 805 1.5.2.2 rmind * Normally we would count the busy pins. 806 1.5.2.2 rmind * 807 1.5.2.2 rmind * We can't check inuse here since uboot has used pins for its 808 1.5.2.2 rmind * own use and left them configured forbidding us to use pins 809 1.5.2.2 rmind * for our own sake. 810 1.5.2.2 rmind */ 811 1.5.2.2 rmind #if 0 812 1.5.2.2 rmind for (int j = 0, int mask = 1; 813 1.5.2.2 rmind (mask & grp->grp_pin_mask) != 0; 814 1.5.2.2 rmind j++, mask <<= 1) { 815 1.5.2.2 rmind int func = exynos_gpio_get_pin_func(&grp->grp_cfg, j); 816 1.5.2.2 rmind if (func > EXYNOS_GPIO_FUNC_INPUT) { 817 1.5.2.2 rmind printf("%s: %s[%d] func %d\n", __func__, 818 1.5.2.2 rmind grp->grp_name, j, func); 819 1.5.2.2 rmind } 820 1.5.2.2 rmind } 821 1.5.2.2 rmind #endif 822 1.5.2.2 rmind } 823 1.5.2.2 rmind #if 0 824 1.5.2.2 rmind printf("\n"); 825 1.5.2.2 rmind printf("default NC pin list generated: \n"); 826 1.5.2.2 rmind /* enable this for default NC pins list generation */ 827 1.5.2.2 rmind for (i = 0; i < exynos_n_pin_groups; i++) { 828 1.5.2.2 rmind grp = &exynos_pin_groups[i]; 829 1.5.2.2 rmind printf("prop_dictionary_set_uint32(dict, \"nc-%s\", " 830 1.5.2.2 rmind "0x%02x - 0b00000000);\n", 831 1.5.2.2 rmind grp->grp_name, grp->grp_pin_mask); 832 1.5.2.2 rmind } 833 1.5.2.2 rmind #endif 834 1.5.2.2 rmind } 835 1.5.2.2 rmind 836
Indexes created Wed Oct 22 13:09:56 GMT 2025