exynos_gpio.c revision 1.7.2.2
1 1.7.2.2 tls /*- 2 1.7.2.2 tls * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 1.7.2.2 tls * All rights reserved. 4 1.7.2.2 tls * 5 1.7.2.2 tls * This code is derived from software contributed to The NetBSD Foundation 6 1.7.2.2 tls * by Reinoud Zandijk 7 1.7.2.2 tls * 8 1.7.2.2 tls * Redistribution and use in source and binary forms, with or without 9 1.7.2.2 tls * modification, are permitted provided that the following conditions 10 1.7.2.2 tls * are met: 11 1.7.2.2 tls * 1. Redistributions of source code must retain the above copyright 12 1.7.2.2 tls * notice, this list of conditions and the following disclaimer. 13 1.7.2.2 tls * 2. Redistributions in binary form must reproduce the above copyright 14 1.7.2.2 tls * notice, this list of conditions and the following disclaimer in the 15 1.7.2.2 tls * documentation and/or other materials provided with the distribution. 16 1.7.2.2 tls * 17 1.7.2.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 1.7.2.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 1.7.2.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 1.7.2.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 1.7.2.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 1.7.2.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 1.7.2.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 1.7.2.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 1.7.2.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 1.7.2.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 1.7.2.2 tls * POSSIBILITY OF SUCH DAMAGE. 28 1.7.2.2 tls */ 29 1.7.2.2 tls 30 1.7.2.2 tls #include "opt_exynos.h" 31 1.7.2.2 tls #include "opt_arm_debug.h" 32 1.7.2.2 tls #include "gpio.h" 33 1.7.2.2 tls 34 1.7.2.2 tls #include <sys/cdefs.h> 35 1.7.2.2 tls __KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.7.2.2 2014/08/20 00:02:47 tls Exp $"); 36 1.7.2.2 tls 37 1.7.2.2 tls #include <sys/param.h> 38 1.7.2.2 tls #include <sys/bus.h> 39 1.7.2.2 tls #include <sys/device.h> 40 1.7.2.2 tls #include <sys/intr.h> 41 1.7.2.2 tls #include <sys/systm.h> 42 1.7.2.2 tls #include <sys/kmem.h> 43 1.7.2.2 tls 44 1.7.2.2 tls #include <arm/samsung/exynos_reg.h> 45 1.7.2.2 tls #include <arm/samsung/exynos_io.h> 46 1.7.2.2 tls #include <arm/samsung/exynos_intr.h> 47 1.7.2.2 tls 48 1.7.2.2 tls #include <sys/gpio.h> 49 1.7.2.2 tls #include <dev/gpio/gpiovar.h> 50 1.7.2.2 tls 51 1.7.2.2 tls static int exynos_gpio_match(device_t, cfdata_t, void *); 52 1.7.2.2 tls static void exynos_gpio_attach(device_t, device_t, void *); 53 1.7.2.2 tls 54 1.7.2.2 tls static int exynos_gpio_pin_read(void *, int); 55 1.7.2.2 tls static void exynos_gpio_pin_write(void *, int, int); 56 1.7.2.2 tls static void exynos_gpio_pin_ctl(void *, int, int); 57 1.7.2.2 tls 58 1.7.2.2 tls struct exynos_gpio_pin_cfg { 59 1.7.2.2 tls uint32_t cfg; 60 1.7.2.2 tls uint32_t pud; 61 1.7.2.2 tls uint32_t drv; 62 1.7.2.2 tls uint32_t conpwd; 63 1.7.2.2 tls uint32_t pudpwd; 64 1.7.2.2 tls }; 65 1.7.2.2 tls 66 1.7.2.2 tls struct exynos_gpio_pin_group { 67 1.7.2.2 tls const char grp_name[6]; 68 1.7.2.2 tls const bus_addr_t grp_core_offset; 69 1.7.2.2 tls const uint8_t grp_bits; 70 1.7.2.2 tls 71 1.7.2.2 tls uint8_t grp_pin_mask; 72 1.7.2.2 tls uint8_t grp_pin_inuse_mask; 73 1.7.2.2 tls bus_space_handle_t grp_bsh; 74 1.7.2.2 tls struct exynos_gpio_pin_cfg grp_cfg; 75 1.7.2.2 tls struct gpio_chipset_tag grp_gc_tag; 76 1.7.2.2 tls }; 77 1.7.2.2 tls 78 1.7.2.2 tls 79 1.7.2.2 tls #define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o)) 80 1.7.2.2 tls #define GPIO_GRP(v, s, o, n, b) \ 81 1.7.2.2 tls { \ 82 1.7.2.2 tls .grp_name = #n, \ 83 1.7.2.2 tls .grp_core_offset = GPIO_REG(v,s,o), \ 84 1.7.2.2 tls .grp_bits = b,\ 85 1.7.2.2 tls } 86 1.7.2.2 tls 87 1.7.2.2 tls #ifdef EXYNOS4 88 1.7.2.2 tls /* 89 1.7.2.2 tls * Exynos 4412 contains 304 multi-functional input/output port pins and 164 90 1.7.2.2 tls * memory port pins. There are 37 general port groups and two memory port 91 1.7.2.2 tls * groups. They are: 92 1.7.2.2 tls * 93 1.7.2.2 tls * GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow 94 1.7.2.2 tls * control, and/or 2xI2C 95 1.7.2.2 tls * 96 1.7.2.2 tls * GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM 97 1.7.2.2 tls * 98 1.7.2.2 tls * GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 99 1.7.2.2 tls * and/or SPI 100 1.7.2.2 tls * 101 1.7.2.2 tls * GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI 102 1.7.2.2 tls * 103 1.7.2.2 tls * GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F, 104 1.7.2.2 tls * HSI, and/ or Trace I/F 105 1.7.2.2 tls * 106 1.7.2.2 tls * GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F 107 1.7.2.2 tls * 108 1.7.2.2 tls * GPJ0, GPJ1: 13 in/out ports-CAM I/F 109 1.7.2.2 tls * 110 1.7.2.2 tls * GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC 111 1.7.2.2 tls * (8-bit MMC)), and/or GPS debugging I/F 112 1.7.2.2 tls * 113 1.7.2.2 tls * GPL0, GPL1: 11 in/out ports-GPS I/F 114 1.7.2.2 tls * 115 1.7.2.2 tls * GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F 116 1.7.2.2 tls * 117 1.7.2.2 tls * GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad 118 1.7.2.2 tls * I/F 119 1.7.2.2 tls * 120 1.7.2.2 tls * GPZ: 7 in/out ports-low Power I2S and/or PCM 121 1.7.2.2 tls * 122 1.7.2.2 tls * GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One 123 1.7.2.2 tls * NAND) 124 1.7.2.2 tls * 125 1.7.2.2 tls * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information 126 1.7.2.2 tls * about EBI configuration, refer to Chapter 5, and 6) 127 1.7.2.2 tls * 128 1.7.2.2 tls * MP1_0-MP1_9: 78 DRAM1 ports. NOTE: GPIO registers does not control these 129 1.7.2.2 tls * ports. 130 1.7.2.2 tls * 131 1.7.2.2 tls * MP2_0-MP2_9: 78 DRAM2 ports. NOTE: GPIO registers does not control these 132 1.7.2.2 tls * ports. 133 1.7.2.2 tls * 134 1.7.2.2 tls * ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK 135 1.7.2.2 tls * 136 1.7.2.2 tls * ETC7, ETC8 : 4 clock port for C2C 137 1.7.2.2 tls * 138 1.7.2.2 tls */ 139 1.7.2.2 tls 140 1.7.2.2 tls static struct exynos_gpio_pin_group exynos4_pin_groups[] = { 141 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0000, GPA0, 8), 142 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0020, GPA1, 6), 143 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0040, GPB, 8), 144 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0060, GPC0, 5), 145 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0080, GPC1, 5), 146 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x00A0, GPD0, 4), 147 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x00C0, GPD1, 4), 148 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0180, GPF0, 8), 149 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x01A0, GPF1, 8), 150 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x01C0, GPF2, 8), 151 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x01E0, GPF3, 8), 152 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0240, GPJ0, 8), 153 1.7.2.2 tls GPIO_GRP(4, LEFT, 0x0260, GPJ1, 5), 154 1.7.2.2 tls /* EXTINT skipped */ 155 1.7.2.2 tls 156 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0040, GPK0, 8), 157 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0060, GPK1, 8), 158 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0080, GPK2, 7), 159 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x00A0, GPK3, 7), 160 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x00C0, GPL0, 7), 161 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x00E0, GPL1, 2), 162 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0100, GPL2, 8), 163 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0120, GPY0, 6), 164 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0140, GPY1, 4), 165 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0160, GPY2, 6), 166 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0180, GPY3, 8), 167 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x01A0, GPY4, 8), 168 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8), 169 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8), 170 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0200, ETC0, 6), 171 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0220, ETC6, 7), 172 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8), 173 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7), 174 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5), 175 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x02C0, GPM3, 8), 176 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x02E0, GPM4, 8), 177 1.7.2.2 tls /* EXTINT skipped */ 178 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0C00, GPX0, 8), 179 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0C20, GPX1, 8), 180 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0C40, GPX2, 8), 181 1.7.2.2 tls GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8), 182 1.7.2.2 tls /* EXTINT skipped */ 183 1.7.2.2 tls 184 1.7.2.2 tls GPIO_GRP(4, I2S0, 0x0000, GPZ, 8), 185 1.7.2.2 tls /* EXTINT skipped */ 186 1.7.2.2 tls 187 1.7.2.2 tls GPIO_GRP(4, C2C, 0x0000, GPV0, 8), 188 1.7.2.2 tls GPIO_GRP(4, C2C, 0x0020, GPV1, 8), 189 1.7.2.2 tls GPIO_GRP(4, C2C, 0x0040, ETC7, 2), 190 1.7.2.2 tls GPIO_GRP(4, C2C, 0x0060, GPV2, 8), 191 1.7.2.2 tls GPIO_GRP(4, C2C, 0x0080, GPV3, 8), 192 1.7.2.2 tls GPIO_GRP(4, C2C, 0x00A0, ETC8, 2), 193 1.7.2.2 tls GPIO_GRP(4, C2C, 0x00C0, GPV4, 2), 194 1.7.2.2 tls /* EXTINT skipped */ 195 1.7.2.2 tls }; 196 1.7.2.2 tls #endif 197 1.7.2.2 tls 198 1.7.2.2 tls 199 1.7.2.2 tls #ifdef EXYNOS5 200 1.7.2.2 tls static struct exynos_gpio_pin_group exynos5_pin_groups[] = { 201 1.7.2.2 tls }; 202 1.7.2.2 tls #endif 203 1.7.2.2 tls 204 1.7.2.2 tls 205 1.7.2.2 tls struct exynos_gpio_softc { 206 1.7.2.2 tls device_t sc_dev; 207 1.7.2.2 tls bus_space_tag_t sc_bst; 208 1.7.2.2 tls bus_space_handle_t sc_bsh; 209 1.7.2.2 tls }; 210 1.7.2.2 tls 211 1.7.2.2 tls 212 1.7.2.2 tls /* force these structures in DATA segment */ 213 1.7.2.2 tls static struct exynos_gpio_pin_group *exynos_pin_groups = NULL; 214 1.7.2.2 tls static int exynos_n_pin_groups = 0; 215 1.7.2.2 tls 216 1.7.2.2 tls static struct exynos_gpio_softc exynos_gpio_sc = {}; 217 1.7.2.2 tls 218 1.7.2.2 tls 219 1.7.2.2 tls CFATTACH_DECL_NEW(exynos_gpio, sizeof(struct exynos_gpio_softc), 220 1.7.2.2 tls exynos_gpio_match, exynos_gpio_attach, NULL, NULL); 221 1.7.2.2 tls 222 1.7.2.2 tls 223 1.7.2.2 tls static int 224 1.7.2.2 tls exynos_gpio_match(device_t parent, cfdata_t cf, void *aux) 225 1.7.2.2 tls { 226 1.7.2.2 tls struct exyo_attach_args * const exyoaa = aux; 227 1.7.2.2 tls struct exyo_locators *loc = &exyoaa->exyo_loc; 228 1.7.2.2 tls 229 1.7.2.2 tls /* no locators expected */ 230 1.7.2.2 tls KASSERT(loc->loc_offset == 0); 231 1.7.2.2 tls KASSERT(loc->loc_size == 0); 232 1.7.2.2 tls KASSERT(loc->loc_port == EXYOCF_PORT_DEFAULT); 233 1.7.2.2 tls 234 1.7.2.2 tls /* there can only be one */ 235 1.7.2.2 tls if (exynos_gpio_sc.sc_dev != NULL) 236 1.7.2.2 tls return 0; 237 1.7.2.2 tls return 1; 238 1.7.2.2 tls } 239 1.7.2.2 tls 240 1.7.2.2 tls 241 1.7.2.2 tls #if NGPIO > 0 242 1.7.2.2 tls static void 243 1.7.2.2 tls exynos_gpio_config_pins(device_t self) 244 1.7.2.2 tls { 245 1.7.2.2 tls struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 246 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 247 1.7.2.2 tls struct gpiobus_attach_args gba; 248 1.7.2.2 tls gpio_pin_t *pin, *pins; 249 1.7.2.2 tls size_t pin_count = 0; 250 1.7.2.2 tls int i, bit, mask, pincaps, data; 251 1.7.2.2 tls 252 1.7.2.2 tls if (exynos_n_pin_groups == 0) 253 1.7.2.2 tls return; 254 1.7.2.2 tls 255 1.7.2.2 tls /* find out how many pins we can offer */ 256 1.7.2.2 tls pin_count = 0; 257 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 258 1.7.2.2 tls grp = &exynos_pin_groups[i]; 259 1.7.2.2 tls mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 260 1.7.2.2 tls pin_count += popcount32(mask); 261 1.7.2.2 tls } 262 1.7.2.2 tls 263 1.7.2.2 tls /* if no pins available, don't proceed */ 264 1.7.2.2 tls if (pin_count == 0) 265 1.7.2.2 tls return; 266 1.7.2.2 tls 267 1.7.2.2 tls /* allocate pin data */ 268 1.7.2.2 tls pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count, KM_SLEEP); 269 1.7.2.2 tls KASSERT(pins); 270 1.7.2.2 tls 271 1.7.2.2 tls pincaps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 272 1.7.2.2 tls GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 273 1.7.2.2 tls 274 1.7.2.2 tls /* add all pins */ 275 1.7.2.2 tls pin = pins; 276 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 277 1.7.2.2 tls grp = &exynos_pin_groups[i]; 278 1.7.2.2 tls mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 279 1.7.2.2 tls if (mask == 0) 280 1.7.2.2 tls continue; 281 1.7.2.2 tls gba.gba_gc = &grp->grp_gc_tag; 282 1.7.2.2 tls gba.gba_pins = pin; 283 1.7.2.2 tls data = bus_space_read_1(sc->sc_bst, grp->grp_bsh, 284 1.7.2.2 tls EXYNOS_GPIO_DAT); 285 1.7.2.2 tls for (bit = 0; mask != 0; mask >>= 1, data >>= 1, bit++) { 286 1.7.2.2 tls if (mask & 1) { 287 1.7.2.2 tls pin->pin_num = bit + (i << 3); 288 1.7.2.2 tls pin->pin_caps = pincaps; 289 1.7.2.2 tls pin->pin_flags = pincaps; 290 1.7.2.2 tls pin->pin_state = (data & 1) != 0; 291 1.7.2.2 tls pin++; 292 1.7.2.2 tls } 293 1.7.2.2 tls } 294 1.7.2.2 tls gba.gba_npins = pin - gba.gba_pins; 295 1.7.2.2 tls config_found_ia(self, "gpiobus", &gba, gpiobus_print); 296 1.7.2.2 tls } 297 1.7.2.2 tls } 298 1.7.2.2 tls #endif 299 1.7.2.2 tls 300 1.7.2.2 tls 301 1.7.2.2 tls static void 302 1.7.2.2 tls exynos_gpio_attach(device_t parent, device_t self, void *aux) 303 1.7.2.2 tls { 304 1.7.2.2 tls struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 305 1.7.2.2 tls struct exyo_attach_args * const exyoaa = aux; 306 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 307 1.7.2.2 tls prop_dictionary_t dict = device_properties(self); 308 1.7.2.2 tls uint32_t nc; 309 1.7.2.2 tls char scrap[16]; 310 1.7.2.2 tls int i; 311 1.7.2.2 tls 312 1.7.2.2 tls /* construct softc */ 313 1.7.2.2 tls sc->sc_dev = self; 314 1.7.2.2 tls 315 1.7.2.2 tls /* we use the core bushandle here */ 316 1.7.2.2 tls sc->sc_bst = exyoaa->exyo_core_bst; 317 1.7.2.2 tls sc->sc_bsh = exyoaa->exyo_core_bsh; 318 1.7.2.2 tls 319 1.7.2.2 tls exynos_gpio_bootstrap(); 320 1.7.2.2 tls if (exynos_n_pin_groups == 0) { 321 1.7.2.2 tls printf(": disabled, no pins defined\n"); 322 1.7.2.2 tls return; 323 1.7.2.2 tls } 324 1.7.2.2 tls 325 1.7.2.2 tls KASSERT(exynos_pin_groups); 326 1.7.2.2 tls KASSERT(exynos_n_pin_groups); 327 1.7.2.2 tls 328 1.7.2.2 tls aprint_naive("\n"); 329 1.7.2.2 tls aprint_normal("\n"); 330 1.7.2.2 tls 331 1.7.2.2 tls /* go trough all pin groups */ 332 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 333 1.7.2.2 tls grp = &exynos_pin_groups[i]; 334 1.7.2.2 tls snprintf(scrap, sizeof(scrap), "nc-%s", grp->grp_name); 335 1.7.2.2 tls if (prop_dictionary_get_uint32(dict, scrap, &nc)) { 336 1.7.2.2 tls KASSERT((~grp->grp_pin_mask & nc) == 0); 337 1.7.2.2 tls /* switch off the pins we have signalled NC */ 338 1.7.2.2 tls grp->grp_pin_mask &= ~nc; 339 1.7.2.2 tls #if 0 340 1.7.2.2 tls printf("%s: %-4s inuse_mask %02x, pin_mask %02x\n", 341 1.7.2.2 tls __func__, grp->grp_name, 342 1.7.2.2 tls grp->grp_pin_inuse_mask, grp->grp_pin_mask); 343 1.7.2.2 tls #endif 344 1.7.2.2 tls } 345 1.7.2.2 tls } 346 1.7.2.2 tls 347 1.7.2.2 tls #if NGPIO > 0 348 1.7.2.2 tls config_defer(self, exynos_gpio_config_pins); 349 1.7.2.2 tls #endif 350 1.7.2.2 tls } 351 1.7.2.2 tls 352 1.7.2.2 tls 353 1.7.2.2 tls /* pin access functions */ 354 1.7.2.2 tls static u_int 355 1.7.2.2 tls exynos_gpio_get_pin_func(const struct exynos_gpio_pin_cfg *cfg, int pin) 356 1.7.2.2 tls { 357 1.7.2.2 tls const u_int shift = (pin & 7) << 2; 358 1.7.2.2 tls 359 1.7.2.2 tls return (cfg->cfg >> shift) & 0x0f; 360 1.7.2.2 tls } 361 1.7.2.2 tls 362 1.7.2.2 tls 363 1.7.2.2 tls static void 364 1.7.2.2 tls exynos_gpio_set_pin_func(struct exynos_gpio_pin_cfg *cfg, 365 1.7.2.2 tls int pin, int func) 366 1.7.2.2 tls { 367 1.7.2.2 tls const u_int shift = (pin & 7) << 2; 368 1.7.2.2 tls 369 1.7.2.2 tls cfg->cfg &= ~(0x0f << shift); 370 1.7.2.2 tls cfg->cfg |= func << shift; 371 1.7.2.2 tls } 372 1.7.2.2 tls 373 1.7.2.2 tls 374 1.7.2.2 tls static void 375 1.7.2.2 tls exynos_gpio_set_pin_pull(struct exynos_gpio_pin_cfg *cfg, int pin, int pull) 376 1.7.2.2 tls { 377 1.7.2.2 tls const u_int shift = (pin & 7) << 1; 378 1.7.2.2 tls 379 1.7.2.2 tls cfg->pud &= ~(0x3 << shift); 380 1.7.2.2 tls cfg->pud |= pull << shift; 381 1.7.2.2 tls } 382 1.7.2.2 tls 383 1.7.2.2 tls 384 1.7.2.2 tls static int 385 1.7.2.2 tls exynos_gpio_pin_read(void *cookie, int pin) 386 1.7.2.2 tls { 387 1.7.2.2 tls struct exynos_gpio_pin_group * const grp = cookie; 388 1.7.2.2 tls 389 1.7.2.2 tls KASSERT(pin < grp->grp_bits); 390 1.7.2.2 tls return (bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 391 1.7.2.2 tls EXYNOS_GPIO_DAT) >> pin) & 1; 392 1.7.2.2 tls } 393 1.7.2.2 tls 394 1.7.2.2 tls 395 1.7.2.2 tls static void 396 1.7.2.2 tls exynos_gpio_pin_write(void *cookie, int pin, int value) 397 1.7.2.2 tls { 398 1.7.2.2 tls struct exynos_gpio_pin_group * const grp = cookie; 399 1.7.2.2 tls int val; 400 1.7.2.2 tls 401 1.7.2.2 tls KASSERT(pin < grp->grp_bits); 402 1.7.2.2 tls val = bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 403 1.7.2.2 tls EXYNOS_GPIO_DAT); 404 1.7.2.2 tls val &= ~__BIT(pin); 405 1.7.2.2 tls if (value) 406 1.7.2.2 tls val |= __BIT(pin); 407 1.7.2.2 tls bus_space_write_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 408 1.7.2.2 tls EXYNOS_GPIO_DAT, val); 409 1.7.2.2 tls } 410 1.7.2.2 tls 411 1.7.2.2 tls 412 1.7.2.2 tls static void 413 1.7.2.2 tls exynos_gpio_update_cfg_regs(struct exynos_gpio_pin_group *grp, 414 1.7.2.2 tls const struct exynos_gpio_pin_cfg *ncfg) 415 1.7.2.2 tls { 416 1.7.2.2 tls bus_space_tag_t bst = &exynos_bs_tag; 417 1.7.2.2 tls 418 1.7.2.2 tls if (grp->grp_cfg.cfg != ncfg->cfg) { 419 1.7.2.2 tls bus_space_write_4(bst, grp->grp_bsh, 420 1.7.2.2 tls EXYNOS_GPIO_CON, ncfg->cfg); 421 1.7.2.2 tls grp->grp_cfg.cfg = ncfg->cfg; 422 1.7.2.2 tls } 423 1.7.2.2 tls if (grp->grp_cfg.pud != ncfg->pud) { 424 1.7.2.2 tls bus_space_write_4(bst, grp->grp_bsh, 425 1.7.2.2 tls EXYNOS_GPIO_PUD, ncfg->pud); 426 1.7.2.2 tls grp->grp_cfg.pud = ncfg->pud; 427 1.7.2.2 tls } 428 1.7.2.2 tls 429 1.7.2.2 tls /* the following attributes are not yet setable */ 430 1.7.2.2 tls #if 0 431 1.7.2.2 tls if (grp->grp_cfg.drv != ncfg->drv) { 432 1.7.2.2 tls bus_space_write_4(bst, grp->grp_bsh, 433 1.7.2.2 tls EXYNOS_GPIO_DRV, ncfg->drv); 434 1.7.2.2 tls grp->grp_cfg.drv = ncfg->drv; 435 1.7.2.2 tls } 436 1.7.2.2 tls if (grp->grp_cfg.conpwd != ncfg->conpwd) { 437 1.7.2.2 tls bus_space_write_4(bst, grp->grp_bsh, 438 1.7.2.2 tls EXYNOS_GPIO_CONPWD, ncfg->conpwd); 439 1.7.2.2 tls grp->grp_cfg.conpwd = ncfg->conpwd; 440 1.7.2.2 tls } 441 1.7.2.2 tls if (grp->grp_cfg.pudpwd != ncfg->pudpwd) { 442 1.7.2.2 tls bus_space_write_4(bst, grp->grp_bsh, 443 1.7.2.2 tls EXYNOS_GPIO_PUDPWD, ncfg->pudpwd); 444 1.7.2.2 tls grp->grp_cfg.pudpwd = ncfg->pudpwd; 445 1.7.2.2 tls } 446 1.7.2.2 tls #endif 447 1.7.2.2 tls } 448 1.7.2.2 tls 449 1.7.2.2 tls 450 1.7.2.2 tls static void 451 1.7.2.2 tls exynos_gpio_pin_ctl(void *cookie, int pin, int flags) 452 1.7.2.2 tls { 453 1.7.2.2 tls struct exynos_gpio_pin_group * const grp = cookie; 454 1.7.2.2 tls struct exynos_gpio_pin_cfg ncfg = grp->grp_cfg; 455 1.7.2.2 tls int pull; 456 1.7.2.2 tls 457 1.7.2.2 tls /* honour pullup requests */ 458 1.7.2.2 tls pull = EXYNOS_GPIO_PIN_FLOAT; 459 1.7.2.2 tls if (flags & GPIO_PIN_PULLUP) 460 1.7.2.2 tls pull = EXYNOS_GPIO_PIN_PULL_UP; 461 1.7.2.2 tls if (flags & GPIO_PIN_PULLDOWN) 462 1.7.2.2 tls pull = EXYNOS_GPIO_PIN_PULL_DOWN; 463 1.7.2.2 tls exynos_gpio_set_pin_pull(&ncfg, pin, pull); 464 1.7.2.2 tls 465 1.7.2.2 tls /* honour i/o */ 466 1.7.2.2 tls if (flags & GPIO_PIN_INPUT) 467 1.7.2.2 tls exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_INPUT); 468 1.7.2.2 tls if (flags & GPIO_PIN_OUTPUT) 469 1.7.2.2 tls exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_OUTPUT); 470 1.7.2.2 tls 471 1.7.2.2 tls /* update any config registers that changed */ 472 1.7.2.2 tls exynos_gpio_update_cfg_regs(grp, &ncfg); 473 1.7.2.2 tls } 474 1.7.2.2 tls 475 1.7.2.2 tls 476 1.7.2.2 tls bool 477 1.7.2.2 tls exynos_gpio_pinset_available(const struct exynos_gpio_pinset *req) 478 1.7.2.2 tls { 479 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 480 1.7.2.2 tls int i, n, inuse; 481 1.7.2.2 tls 482 1.7.2.2 tls KASSERT(req); 483 1.7.2.2 tls if (exynos_n_pin_groups == 0) 484 1.7.2.2 tls return false; 485 1.7.2.2 tls 486 1.7.2.2 tls /* we need a pinset group */ 487 1.7.2.2 tls if (strlen(req->pinset_group) == 0) 488 1.7.2.2 tls return false; 489 1.7.2.2 tls 490 1.7.2.2 tls /* determine which group is requested */ 491 1.7.2.2 tls grp = NULL; 492 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 493 1.7.2.2 tls grp = &exynos_pin_groups[i]; 494 1.7.2.2 tls if (strcmp(req->pinset_group, grp->grp_name) == 0) 495 1.7.2.2 tls break; 496 1.7.2.2 tls } 497 1.7.2.2 tls /* found? */ 498 1.7.2.2 tls if (i == exynos_n_pin_groups) 499 1.7.2.2 tls return false; 500 1.7.2.2 tls KASSERT(grp); 501 1.7.2.2 tls 502 1.7.2.2 tls /* fail unconnected pins */ 503 1.7.2.2 tls if (req->pinset_mask & ~grp->grp_pin_mask) 504 1.7.2.2 tls return false; 505 1.7.2.2 tls 506 1.7.2.2 tls /* if none in use, they are available */ 507 1.7.2.2 tls if (req->pinset_mask & ~grp->grp_pin_inuse_mask) 508 1.7.2.2 tls return true; 509 1.7.2.2 tls 510 1.7.2.2 tls /* OK, so some are in use; now see if the request is compatible */ 511 1.7.2.2 tls inuse = req->pinset_mask & grp->grp_pin_inuse_mask; 512 1.7.2.2 tls for (i = 0; inuse; i++, inuse >>= 1) { 513 1.7.2.2 tls /* try to be smart by skipping zero's */ 514 1.7.2.2 tls n = ffs(inuse) -1; 515 1.7.2.2 tls i += n; 516 1.7.2.2 tls inuse >>= n; 517 1.7.2.2 tls /* this pin is in use, check its usage */ 518 1.7.2.2 tls if (exynos_gpio_get_pin_func(&grp->grp_cfg, i) != req->pinset_func) 519 1.7.2.2 tls return false; 520 1.7.2.2 tls } 521 1.7.2.2 tls 522 1.7.2.2 tls /* seems to be OK */ 523 1.7.2.2 tls return true; 524 1.7.2.2 tls } 525 1.7.2.2 tls 526 1.7.2.2 tls 527 1.7.2.2 tls void 528 1.7.2.2 tls exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *req) 529 1.7.2.2 tls { 530 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 531 1.7.2.2 tls struct exynos_gpio_pin_cfg ncfg; 532 1.7.2.2 tls int i, n, todo; 533 1.7.2.2 tls 534 1.7.2.2 tls KASSERT(req); 535 1.7.2.2 tls KASSERT(exynos_gpio_pinset_available(req)); 536 1.7.2.2 tls 537 1.7.2.2 tls /* determine which group is requested */ 538 1.7.2.2 tls grp = NULL; 539 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 540 1.7.2.2 tls grp = &exynos_pin_groups[i]; 541 1.7.2.2 tls if (strcmp(req->pinset_group, grp->grp_name) == 0) 542 1.7.2.2 tls break; 543 1.7.2.2 tls } 544 1.7.2.2 tls KASSERT(grp); 545 1.7.2.2 tls 546 1.7.2.2 tls /* check if all the pins have the right function */ 547 1.7.2.2 tls if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0) 548 1.7.2.2 tls return; 549 1.7.2.2 tls 550 1.7.2.2 tls /* copy current config for update routine */ 551 1.7.2.2 tls ncfg = grp->grp_cfg; 552 1.7.2.2 tls 553 1.7.2.2 tls /* update the function of each pin that is not in use */ 554 1.7.2.2 tls todo = req->pinset_mask & grp->grp_pin_inuse_mask; 555 1.7.2.2 tls for (i = 0; todo; i++, todo >>= 1) { 556 1.7.2.2 tls /* try to be smart by skipping zero's */ 557 1.7.2.2 tls n = ffs(todo) -1; 558 1.7.2.2 tls i += n; 559 1.7.2.2 tls todo >>= n; 560 1.7.2.2 tls /* change the function of this pin */ 561 1.7.2.2 tls exynos_gpio_set_pin_func(&ncfg, i, req->pinset_func); 562 1.7.2.2 tls } 563 1.7.2.2 tls 564 1.7.2.2 tls /* update config registers */ 565 1.7.2.2 tls exynos_gpio_update_cfg_regs(grp, &ncfg); 566 1.7.2.2 tls 567 1.7.2.2 tls /* mark pins in use */ 568 1.7.2.2 tls grp->grp_pin_inuse_mask |= req->pinset_mask; 569 1.7.2.2 tls } 570 1.7.2.2 tls 571 1.7.2.2 tls 572 1.7.2.2 tls /* get a pindata structure from a pinset structure */ 573 1.7.2.2 tls void 574 1.7.2.2 tls exynos_gpio_pinset_to_pindata(const struct exynos_gpio_pinset *req, int pinnr, 575 1.7.2.2 tls struct exynos_gpio_pindata *pd) 576 1.7.2.2 tls { 577 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 578 1.7.2.2 tls int i; 579 1.7.2.2 tls 580 1.7.2.2 tls KASSERT(req); 581 1.7.2.2 tls KASSERT(pd); 582 1.7.2.2 tls KASSERT(req->pinset_mask & __BIT(pinnr)); 583 1.7.2.2 tls 584 1.7.2.2 tls /* determine which group is requested */ 585 1.7.2.2 tls grp = NULL; 586 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 587 1.7.2.2 tls grp = &exynos_pin_groups[i]; 588 1.7.2.2 tls if (strcmp(req->pinset_group, grp->grp_name) == 0) 589 1.7.2.2 tls break; 590 1.7.2.2 tls } 591 1.7.2.2 tls KASSERT(grp); 592 1.7.2.2 tls 593 1.7.2.2 tls pd->pd_gc = &grp->grp_gc_tag; 594 1.7.2.2 tls pd->pd_pin = pinnr; 595 1.7.2.2 tls } 596 1.7.2.2 tls 597 1.7.2.2 tls 598 1.7.2.2 tls /* XXXRPZ This release doesn't grock multiple usages! */ 599 1.7.2.2 tls void 600 1.7.2.2 tls exynos_gpio_pinset_release(const struct exynos_gpio_pinset *req) 601 1.7.2.2 tls { 602 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 603 1.7.2.2 tls int i; 604 1.7.2.2 tls 605 1.7.2.2 tls KASSERT(!exynos_gpio_pinset_available(req)); 606 1.7.2.2 tls 607 1.7.2.2 tls /* determine which group is requested */ 608 1.7.2.2 tls grp = NULL; 609 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 610 1.7.2.2 tls grp = &exynos_pin_groups[i]; 611 1.7.2.2 tls if (strcmp(req->pinset_group, grp->grp_name) == 0) 612 1.7.2.2 tls break; 613 1.7.2.2 tls } 614 1.7.2.2 tls KASSERT(grp); 615 1.7.2.2 tls 616 1.7.2.2 tls /* bluntly mark as not being in use */ 617 1.7.2.2 tls grp->grp_pin_inuse_mask &= ~req->pinset_mask; 618 1.7.2.2 tls } 619 1.7.2.2 tls 620 1.7.2.2 tls 621 1.7.2.2 tls /* 622 1.7.2.2 tls * name convention : 623 1.7.2.2 tls * pin = <func><groupname><pinnr>[<pud>] 624 1.7.2.2 tls * func = '<' | '>' 625 1.7.2.2 tls * pinnr = '['['0'-'7']']' 626 1.7.2.2 tls * pud = 'F' | 'U' | 'D' 627 1.7.2.2 tls * 628 1.7.2.2 tls * example "<GPC1[0]", ">GPB[0]" 629 1.7.2.2 tls */ 630 1.7.2.2 tls 631 1.7.2.2 tls bool 632 1.7.2.2 tls exynos_gpio_pin_reserve(const char *name, struct exynos_gpio_pindata *pd) 633 1.7.2.2 tls { 634 1.7.2.2 tls struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 635 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 636 1.7.2.2 tls struct exynos_gpio_pin_cfg ncfg; 637 1.7.2.2 tls prop_dictionary_t dict = device_properties(sc->sc_dev); 638 1.7.2.2 tls const char *pin_data; 639 1.7.2.2 tls char grp_name[15], *pos; 640 1.7.2.2 tls int func, pud, pinnr; 641 1.7.2.2 tls int pi, i; 642 1.7.2.2 tls 643 1.7.2.2 tls if (exynos_n_pin_groups == 0) 644 1.7.2.2 tls return false; 645 1.7.2.2 tls 646 1.7.2.2 tls /* do we have a named pin description? */ 647 1.7.2.2 tls if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data)) 648 1.7.2.2 tls return false; 649 1.7.2.2 tls 650 1.7.2.2 tls KASSERT(strlen(pin_data) < 10); 651 1.7.2.2 tls if (!(pin_data[0] == '>' || pin_data[0] == '<')) { 652 1.7.2.2 tls printf("%s: malformed pin data in '%s', missing direction\n", 653 1.7.2.2 tls __func__, pin_data); 654 1.7.2.2 tls return false; 655 1.7.2.2 tls } 656 1.7.2.2 tls 657 1.7.2.2 tls func = (pin_data[0] == '<') ? 658 1.7.2.2 tls EXYNOS_GPIO_FUNC_INPUT : EXYNOS_GPIO_FUNC_OUTPUT; 659 1.7.2.2 tls 660 1.7.2.2 tls /* find groupname */ 661 1.7.2.2 tls pi = 1; pos = grp_name; 662 1.7.2.2 tls while (pin_data[pi] && pin_data[pi] != '[') { 663 1.7.2.2 tls *pos++ = pin_data[pi++]; 664 1.7.2.2 tls } 665 1.7.2.2 tls if (pin_data[pi] != '[') { 666 1.7.2.2 tls printf("%s: malformed pin data in '%s', missing '['\n", 667 1.7.2.2 tls __func__, pin_data); 668 1.7.2.2 tls return false; 669 1.7.2.2 tls } 670 1.7.2.2 tls *pos++ = (char) 0; 671 1.7.2.2 tls 672 1.7.2.2 tls /* skip '[' */ 673 1.7.2.2 tls pi++; 674 1.7.2.2 tls if (!(pin_data[pi] >= '0' && pin_data[pi] <= '7')) { 675 1.7.2.2 tls printf("%s: malformed pin data in '%s', bad pin number\n", 676 1.7.2.2 tls __func__, pin_data); 677 1.7.2.2 tls return false; 678 1.7.2.2 tls } 679 1.7.2.2 tls pinnr = pin_data[pi] - '0'; 680 1.7.2.2 tls 681 1.7.2.2 tls /* skip digit */ 682 1.7.2.2 tls pi++; 683 1.7.2.2 tls if ((pin_data[pi] != ']')) { 684 1.7.2.2 tls printf("%s: malformed pin data in '%s', missing end ']'\n", 685 1.7.2.2 tls __func__, pin_data); 686 1.7.2.2 tls return false; 687 1.7.2.2 tls } 688 1.7.2.2 tls 689 1.7.2.2 tls /* skip ']' */ 690 1.7.2.2 tls pi++; 691 1.7.2.2 tls pud = EXYNOS_GPIO_PIN_FLOAT; 692 1.7.2.2 tls switch (tolower(pin_data[pi])) { 693 1.7.2.2 tls case (char) 0: 694 1.7.2.2 tls break; 695 1.7.2.2 tls case 'f': 696 1.7.2.2 tls pud = EXYNOS_GPIO_PIN_FLOAT; 697 1.7.2.2 tls break; 698 1.7.2.2 tls case 'u': 699 1.7.2.2 tls pud = EXYNOS_GPIO_PIN_PULL_UP; 700 1.7.2.2 tls break; 701 1.7.2.2 tls case 'd': 702 1.7.2.2 tls pud = EXYNOS_GPIO_PIN_PULL_DOWN; 703 1.7.2.2 tls break; 704 1.7.2.2 tls default: 705 1.7.2.2 tls printf("%s: malformed pin data in '%s', expecting " 706 1.7.2.2 tls "optional pull up/down or float argument\n", 707 1.7.2.2 tls __func__, pin_data); 708 1.7.2.2 tls return false; 709 1.7.2.2 tls } 710 1.7.2.2 tls 711 1.7.2.2 tls /* determine which group is requested */ 712 1.7.2.2 tls grp = NULL; 713 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 714 1.7.2.2 tls grp = &exynos_pin_groups[i]; 715 1.7.2.2 tls if (strcmp(grp_name, grp->grp_name) == 0) 716 1.7.2.2 tls break; 717 1.7.2.2 tls } 718 1.7.2.2 tls 719 1.7.2.2 tls /* found? */ 720 1.7.2.2 tls if (i >= exynos_n_pin_groups) { 721 1.7.2.2 tls printf("%s: malformed pin data in '%s', " 722 1.7.2.2 tls "no such pin group name\n", 723 1.7.2.2 tls __func__, grp_name); 724 1.7.2.2 tls return false; 725 1.7.2.2 tls } 726 1.7.2.2 tls KASSERT(grp); 727 1.7.2.2 tls 728 1.7.2.2 tls /* in range? */ 729 1.7.2.2 tls if (pinnr >= grp->grp_bits) 730 1.7.2.2 tls return false; 731 1.7.2.2 tls 732 1.7.2.2 tls /* marked as connected? */ 733 1.7.2.2 tls if ((grp->grp_pin_mask & __BIT(pinnr)) == 0) 734 1.7.2.2 tls return false; 735 1.7.2.2 tls 736 1.7.2.2 tls /* it better not be used!! this is not taken lightly */ 737 1.7.2.2 tls KASSERT((grp->grp_pin_inuse_mask & __BIT(pinnr)) == 0); 738 1.7.2.2 tls 739 1.7.2.2 tls /* update our pin configuration */ 740 1.7.2.2 tls ncfg = grp->grp_cfg; 741 1.7.2.2 tls exynos_gpio_set_pin_func(&ncfg, pinnr, func); 742 1.7.2.2 tls exynos_gpio_set_pin_pull(&ncfg, pinnr, pud); 743 1.7.2.2 tls exynos_gpio_update_cfg_regs(grp, &ncfg); 744 1.7.2.2 tls 745 1.7.2.2 tls grp->grp_pin_inuse_mask |= __BIT(pinnr); 746 1.7.2.2 tls grp->grp_pin_mask &= ~__BIT(pinnr); 747 1.7.2.2 tls 748 1.7.2.2 tls pd->pd_gc = &grp->grp_gc_tag; 749 1.7.2.2 tls pd->pd_pin = pinnr; 750 1.7.2.2 tls 751 1.7.2.2 tls return true; 752 1.7.2.2 tls } 753 1.7.2.2 tls 754 1.7.2.2 tls 755 1.7.2.2 tls /* bootstrapping */ 756 1.7.2.2 tls void 757 1.7.2.2 tls exynos_gpio_bootstrap(void) 758 1.7.2.2 tls { 759 1.7.2.2 tls bus_space_tag_t bst = &exynos_bs_tag; 760 1.7.2.2 tls struct exynos_gpio_pin_group *grp; 761 1.7.2.2 tls struct gpio_chipset_tag *gc_tag; 762 1.7.2.2 tls int i; 763 1.7.2.2 tls 764 1.7.2.2 tls /* determine what we're running on */ 765 1.7.2.2 tls #ifdef EXYNOS4 766 1.7.2.2 tls if (IS_EXYNOS4_P()) { 767 1.7.2.2 tls exynos_pin_groups = exynos4_pin_groups; 768 1.7.2.2 tls exynos_n_pin_groups = __arraycount(exynos4_pin_groups); 769 1.7.2.2 tls } 770 1.7.2.2 tls #endif 771 1.7.2.2 tls #ifdef EXYNOS5 772 1.7.2.2 tls if (IS_EXYNOS5_P()) { 773 1.7.2.2 tls exynos_pin_groups = exynos5_pin_groups; 774 1.7.2.2 tls exynos_n_pin_groups = __arraycount(exynos5_pin_groups); 775 1.7.2.2 tls } 776 1.7.2.2 tls #endif 777 1.7.2.2 tls 778 1.7.2.2 tls if (exynos_n_pin_groups == 0) 779 1.7.2.2 tls return; 780 1.7.2.2 tls 781 1.7.2.2 tls /* init groups */ 782 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 783 1.7.2.2 tls grp = &exynos_pin_groups[i]; 784 1.7.2.2 tls gc_tag = &grp->grp_gc_tag; 785 1.7.2.2 tls 786 1.7.2.2 tls bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 787 1.7.2.2 tls grp->grp_core_offset, EXYNOS_GPIO_GRP_SIZE, 788 1.7.2.2 tls &grp->grp_bsh); 789 1.7.2.2 tls KASSERT(&grp->grp_bsh); 790 1.7.2.2 tls 791 1.7.2.2 tls grp->grp_pin_mask = __BIT(grp->grp_bits) - 1; 792 1.7.2.2 tls grp->grp_pin_inuse_mask = 0; 793 1.7.2.2 tls 794 1.7.2.2 tls gc_tag->gp_cookie = grp; 795 1.7.2.2 tls gc_tag->gp_pin_read = exynos_gpio_pin_read; 796 1.7.2.2 tls gc_tag->gp_pin_write = exynos_gpio_pin_write; 797 1.7.2.2 tls gc_tag->gp_pin_ctl = exynos_gpio_pin_ctl; 798 1.7.2.2 tls 799 1.7.2.2 tls /* read in our initial settings */ 800 1.7.2.2 tls grp->grp_cfg.cfg = bus_space_read_4(bst, grp->grp_bsh, 801 1.7.2.2 tls EXYNOS_GPIO_CON); 802 1.7.2.2 tls grp->grp_cfg.pud = bus_space_read_4(bst, grp->grp_bsh, 803 1.7.2.2 tls EXYNOS_GPIO_PUD); 804 1.7.2.2 tls grp->grp_cfg.drv = bus_space_read_4(bst, grp->grp_bsh, 805 1.7.2.2 tls EXYNOS_GPIO_DRV); 806 1.7.2.2 tls grp->grp_cfg.conpwd = bus_space_read_4(bst, grp->grp_bsh, 807 1.7.2.2 tls EXYNOS_GPIO_CONPWD); 808 1.7.2.2 tls grp->grp_cfg.pudpwd = bus_space_read_4(bst, grp->grp_bsh, 809 1.7.2.2 tls EXYNOS_GPIO_PUDPWD); 810 1.7.2.2 tls 811 1.7.2.2 tls /* 812 1.7.2.2 tls * Normally we would count the busy pins. 813 1.7.2.2 tls * 814 1.7.2.2 tls * We can't check inuse here since uboot has used pins for its 815 1.7.2.2 tls * own use and left them configured forbidding us to use pins 816 1.7.2.2 tls * for our own sake. 817 1.7.2.2 tls */ 818 1.7.2.2 tls #if 0 819 1.7.2.2 tls for (int j = 0, int mask = 1; 820 1.7.2.2 tls (mask & grp->grp_pin_mask) != 0; 821 1.7.2.2 tls j++, mask <<= 1) { 822 1.7.2.2 tls int func = exynos_gpio_get_pin_func(&grp->grp_cfg, j); 823 1.7.2.2 tls if (func > EXYNOS_GPIO_FUNC_INPUT) { 824 1.7.2.2 tls printf("%s: %s[%d] func %d\n", __func__, 825 1.7.2.2 tls grp->grp_name, j, func); 826 1.7.2.2 tls } 827 1.7.2.2 tls } 828 1.7.2.2 tls #endif 829 1.7.2.2 tls } 830 1.7.2.2 tls #if 0 831 1.7.2.2 tls printf("\n"); 832 1.7.2.2 tls printf("default NC pin list generated: \n"); 833 1.7.2.2 tls /* enable this for default NC pins list generation */ 834 1.7.2.2 tls for (i = 0; i < exynos_n_pin_groups; i++) { 835 1.7.2.2 tls grp = &exynos_pin_groups[i]; 836 1.7.2.2 tls printf("prop_dictionary_set_uint32(dict, \"nc-%s\", " 837 1.7.2.2 tls "0x%02x - 0b00000000);\n", 838 1.7.2.2 tls grp->grp_name, grp->grp_pin_mask); 839 1.7.2.2 tls } 840 1.7.2.2 tls #endif 841 1.7.2.2 tls } 842 1.7.2.2 tls 843
Indexes created Tue Oct 21 16:10:11 GMT 2025