exynos_gpio.c revision 1.12
1 /* $NetBSD: exynos_gpio.c,v 1.12 2014/12/29 22:34:08 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_exynos.h" 33 #include "opt_arm_debug.h" 34 #include "gpio.h" 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.12 2014/12/29 22:34:08 skrll Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/device.h> 42 #include <sys/intr.h> 43 #include <sys/systm.h> 44 #include <sys/kmem.h> 45 46 #include <arm/samsung/exynos_reg.h> 47 #include <arm/samsung/exynos_io.h> 48 #include <arm/samsung/exynos_intr.h> 49 50 #include <sys/gpio.h> 51 #include <dev/gpio/gpiovar.h> 52 53 static int exynos_gpio_match(device_t, cfdata_t, void *); 54 static void exynos_gpio_attach(device_t, device_t, void *); 55 56 static int exynos_gpio_pin_read(void *, int); 57 static void exynos_gpio_pin_write(void *, int, int); 58 static void exynos_gpio_pin_ctl(void *, int, int); 59 60 struct exynos_gpio_pin_cfg { 61 uint32_t cfg; 62 uint32_t pud; 63 uint32_t drv; 64 uint32_t conpwd; 65 uint32_t pudpwd; 66 }; 67 68 struct exynos_gpio_pin_group { 69 const char grp_name[6]; 70 const bus_addr_t grp_core_offset; 71 const uint8_t grp_bits; 72 73 uint8_t grp_pin_mask; 74 uint8_t grp_pin_inuse_mask; 75 bus_space_handle_t grp_bsh; 76 struct exynos_gpio_pin_cfg grp_cfg; 77 struct gpio_chipset_tag grp_gc_tag; 78 }; 79 80 81 #define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o)) 82 #define GPIO_GRP(v, s, o, n, b) \ 83 { \ 84 .grp_name = #n, \ 85 .grp_core_offset = GPIO_REG(v,s,o), \ 86 .grp_bits = b,\ 87 } 88 89 #ifdef EXYNOS4 90 /* 91 * Exynos 4412 contains 304 multi-functional input/output port pins and 164 92 * memory port pins. There are 37 general port groups and two memory port 93 * groups. They are: 94 * 95 * GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow 96 * control, and/or 2xI2C 97 * 98 * GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM 99 * 100 * GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 101 * and/or SPI 102 * 103 * GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI 104 * 105 * GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F, 106 * HSI, and/ or Trace I/F 107 * 108 * GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F 109 * 110 * GPJ0, GPJ1: 13 in/out ports-CAM I/F 111 * 112 * GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC 113 * (8-bit MMC)), and/or GPS debugging I/F 114 * 115 * GPL0, GPL1: 11 in/out ports-GPS I/F 116 * 117 * GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F 118 * 119 * GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad 120 * I/F 121 * 122 * GPZ: 7 in/out ports-low Power I2S and/or PCM 123 * 124 * GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One 125 * NAND) 126 * 127 * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information 128 * about EBI configuration, refer to Chapter 5, and 6) 129 * 130 * MP1_0-MP1_9: 78 DRAM1 ports. NOTE: GPIO registers does not control these 131 * ports. 132 * 133 * MP2_0-MP2_9: 78 DRAM2 ports. NOTE: GPIO registers does not control these 134 * ports. 135 * 136 * ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK 137 * 138 * ETC7, ETC8 : 4 clock port for C2C 139 * 140 */ 141 142 static struct exynos_gpio_pin_group exynos4_pin_groups[] = { 143 GPIO_GRP(4, LEFT, 0x0000, GPA0, 8), 144 GPIO_GRP(4, LEFT, 0x0020, GPA1, 6), 145 GPIO_GRP(4, LEFT, 0x0040, GPB, 8), 146 GPIO_GRP(4, LEFT, 0x0060, GPC0, 5), 147 GPIO_GRP(4, LEFT, 0x0080, GPC1, 5), 148 GPIO_GRP(4, LEFT, 0x00A0, GPD0, 4), 149 GPIO_GRP(4, LEFT, 0x00C0, GPD1, 4), 150 GPIO_GRP(4, LEFT, 0x0180, GPF0, 8), 151 GPIO_GRP(4, LEFT, 0x01A0, GPF1, 8), 152 GPIO_GRP(4, LEFT, 0x01C0, GPF2, 8), 153 GPIO_GRP(4, LEFT, 0x01E0, GPF3, 8), 154 GPIO_GRP(4, LEFT, 0x0240, GPJ0, 8), 155 GPIO_GRP(4, LEFT, 0x0260, GPJ1, 5), 156 /* EXTINT skipped */ 157 158 GPIO_GRP(4, RIGHT, 0x0040, GPK0, 8), 159 GPIO_GRP(4, RIGHT, 0x0060, GPK1, 8), 160 GPIO_GRP(4, RIGHT, 0x0080, GPK2, 7), 161 GPIO_GRP(4, RIGHT, 0x00A0, GPK3, 7), 162 GPIO_GRP(4, RIGHT, 0x00C0, GPL0, 7), 163 GPIO_GRP(4, RIGHT, 0x00E0, GPL1, 2), 164 GPIO_GRP(4, RIGHT, 0x0100, GPL2, 8), 165 GPIO_GRP(4, RIGHT, 0x0120, GPY0, 6), 166 GPIO_GRP(4, RIGHT, 0x0140, GPY1, 4), 167 GPIO_GRP(4, RIGHT, 0x0160, GPY2, 6), 168 GPIO_GRP(4, RIGHT, 0x0180, GPY3, 8), 169 GPIO_GRP(4, RIGHT, 0x01A0, GPY4, 8), 170 GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8), 171 GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8), 172 GPIO_GRP(4, RIGHT, 0x0200, ETC0, 6), 173 GPIO_GRP(4, RIGHT, 0x0220, ETC6, 8), 174 GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8), 175 GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7), 176 GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5), 177 GPIO_GRP(4, RIGHT, 0x02C0, GPM3, 8), 178 GPIO_GRP(4, RIGHT, 0x02E0, GPM4, 8), 179 /* EXTINT skipped */ 180 GPIO_GRP(4, RIGHT, 0x0C00, GPX0, 8), 181 GPIO_GRP(4, RIGHT, 0x0C20, GPX1, 8), 182 GPIO_GRP(4, RIGHT, 0x0C40, GPX2, 8), 183 GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8), 184 /* EXTINT skipped */ 185 186 GPIO_GRP(4, I2S0, 0x0000, GPZ, 8), 187 /* EXTINT skipped */ 188 189 GPIO_GRP(4, C2C, 0x0000, GPV0, 8), 190 GPIO_GRP(4, C2C, 0x0020, GPV1, 8), 191 GPIO_GRP(4, C2C, 0x0040, ETC7, 2), 192 GPIO_GRP(4, C2C, 0x0060, GPV2, 8), 193 GPIO_GRP(4, C2C, 0x0080, GPV3, 8), 194 GPIO_GRP(4, C2C, 0x00A0, ETC8, 2), 195 GPIO_GRP(4, C2C, 0x00C0, GPV4, 2), 196 /* EXTINT skipped */ 197 }; 198 #endif 199 200 201 #ifdef EXYNOS5 202 203 /* 204 * Exynos 5250 contains 253 multi-functional input/output port pins and 160 205 * memory port pins. There are 39 general port groups and 2 memory port 206 * groups. They are: 207 * 208 * GPA0, GPA1: 14 in/out ports-2xUART with flow control, UART without flow 209 * control, and/or 2xI2C , and/or2xHS-I2C 210 * 211 * GPA2: 8 in/out ports-2xSPI, and/or I2C 212 * 213 * GPB0, GPB1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 214 * and/or SPI 215 * 216 * GPB2, GPB3: 8 in/out ports-PWM, I2C, and/or I2C ,and/or HS-I2C 217 * 218 * GPC0, GPC1: 11 in/out ports-1xMMC (8-bit MMC) I/F 219 * 220 * GPC2: 7 in/out ports-1xMMC (4-bit MMC) I/F 221 * 222 * GPC3, GPC4: 14 in/out ports-2xMMC (4-bit MMC) and/or 1xMMC (8-bit MMC) I/F 223 * 224 * GPD0: 4 pin/out ports-1xUART with flow control I/F 225 * 226 * GPD1: 8 pin/out ports-HSI I/F 227 * 228 * GPE0, GPE1, GPF0, GPF1, GPG0, GPG1, GPG2, GPH0, GPH1: 48 in/out ports-CAM 229 * I/F, and/or Trace I/F 230 * 231 * GPV0, GPV1, GPV2, GPV3, GPV4: 34 in/out ports-C2C I/F 232 * 233 * GPX0, 1, 2, 3: 32 in/out port-external wake-up interrupts (up-to 32-bit), 234 * and/or AUD I/F, and/or MFC I/F (GPX groups are in alive region) 235 * 236 * GPY0, GPY1, GPY2: 16 in/out ports-control signals of EBI (SROM) 237 * 238 * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI 239 * 240 * GPZ: 7 in/out ports-low power I2S and/or PCM 241 * 242 * MP1_0-MP1_10: 80 DRAM1 ports NOTE: GPIO registers do not control these 243 * ports. 244 * 245 * MP2_0-MP2_10: 80 DRAM2 ports NOTE: GPIO registers do not control these 246 * ports. 247 * 248 * ETC0, ETC5, ETC6, ETC7, ETC8: 22 in/out ETC ports-JTAG, C2C_CLK (Rx), 249 * RESET, CLOCK, USBOTG and USB3, C2C_CLK (Tx) 250 */ 251 252 static struct exynos_gpio_pin_group exynos5_pin_groups[] = { 253 GPIO_GRP(5, LEFT, 0x0000, GPA0, 8), 254 GPIO_GRP(5, LEFT, 0x0020, GPA1, 6), 255 GPIO_GRP(5, LEFT, 0x0040, GPA2, 8), 256 GPIO_GRP(5, LEFT, 0x0060, GPB0, 5), 257 GPIO_GRP(5, LEFT, 0x0080, GPB1, 5), 258 GPIO_GRP(5, LEFT, 0x00A0, GPB2, 4), 259 GPIO_GRP(5, LEFT, 0x00C0, GPB3, 4), 260 GPIO_GRP(5, LEFT, 0x00E0, GPC0, 7), 261 GPIO_GRP(5, LEFT, 0x0100, GPC1, 4), 262 GPIO_GRP(5, LEFT, 0x0120, GPC2, 7), 263 GPIO_GRP(5, LEFT, 0x0140, GPC3, 7), 264 GPIO_GRP(5, LEFT, 0x0160, GPD0, 4), 265 GPIO_GRP(5, LEFT, 0x0180, GPD1, 8), 266 GPIO_GRP(5, LEFT, 0x01A0, GPY0, 6), 267 GPIO_GRP(5, LEFT, 0x01C0, GPY1, 4), 268 GPIO_GRP(5, LEFT, 0x01E0, GPY2, 6), 269 GPIO_GRP(5, LEFT, 0x0200, GPY3, 8), 270 GPIO_GRP(5, LEFT, 0x0220, GPY4, 8), 271 GPIO_GRP(5, LEFT, 0x0240, GPY5, 8), 272 GPIO_GRP(5, LEFT, 0x0260, GPY6, 8), 273 GPIO_GRP(5, LEFT, 0x0280, ETC0, 6), 274 GPIO_GRP(5, LEFT, 0x02A0, ETC6, 7), 275 GPIO_GRP(5, LEFT, 0x02C0, ETC7, 5), 276 GPIO_GRP(5, LEFT, 0x02E0, GPC4, 7), 277 /* EXTINT skipped */ 278 GPIO_GRP(5, LEFT, 0x0C00, GPX0, 8), 279 GPIO_GRP(5, LEFT, 0x0C20, GPX1, 8), 280 GPIO_GRP(5, LEFT, 0x0C40, GPX2, 8), 281 GPIO_GRP(5, LEFT, 0x0C60, GPX3, 8), 282 /* EXTINT skipped */ 283 284 GPIO_GRP(5, RIGHT, 0x0000, GPE0, 8), 285 GPIO_GRP(5, RIGHT, 0x0020, GPE1, 2), 286 GPIO_GRP(5, RIGHT, 0x0040, GPF0, 4), 287 GPIO_GRP(5, RIGHT, 0x0060, GPF1, 4), 288 GPIO_GRP(5, RIGHT, 0x0080, GPG0, 8), 289 GPIO_GRP(5, RIGHT, 0x00A0, GPG1, 8), 290 GPIO_GRP(5, RIGHT, 0x00C0, GPG2, 2), 291 GPIO_GRP(5, RIGHT, 0x00E0, GPH0, 4), 292 GPIO_GRP(5, RIGHT, 0x0100, GPH1, 8), 293 /* EXTINT skipped */ 294 295 GPIO_GRP(5, USB, 0x0000, GPJ0, 8), // unknown num bits 296 GPIO_GRP(5, USB, 0x0020, GPJ1, 8), // unknown num bits 297 GPIO_GRP(5, USB, 0x0040, GPJ2, 8), // unknown num bits 298 GPIO_GRP(5, USB, 0x0060, GPJ3, 8), // unknown num bits 299 GPIO_GRP(5, USB, 0x0080, GPJ4, 8), // unknown num bits 300 GPIO_GRP(5, USB, 0x00A0, GPK0, 8), // unknown num bits 301 GPIO_GRP(5, USB, 0x00C0, GPK1, 8), // unknown num bits 302 GPIO_GRP(5, USB, 0x00E0, GPK2, 8), // unknown num bits 303 GPIO_GRP(5, USB, 0x0100, GPK3, 8), // unknown num bits 304 /* unknown bits skipped */ 305 306 GPIO_GRP(5, C2C, 0x0000, GPV0, 8), 307 GPIO_GRP(5, C2C, 0x0020, GPV1, 8), 308 GPIO_GRP(5, C2C, 0x0040, ETC5, 2), 309 GPIO_GRP(5, C2C, 0x0060, GPV2, 8), 310 GPIO_GRP(5, C2C, 0x0080, GPV3, 8), 311 GPIO_GRP(5, C2C, 0x00A0, ETC8, 2), 312 GPIO_GRP(5, C2C, 0x00C0, GPV4, 2), 313 /* EXTINT skipped */ 314 315 GPIO_GRP(5, I2S, 0x0000, GPZ, 7), 316 /* EXTINT skipped */ 317 }; 318 #endif 319 320 321 struct exynos_gpio_softc { 322 device_t sc_dev; 323 bus_space_tag_t sc_bst; 324 bus_space_handle_t sc_bsh; 325 }; 326 327 328 /* force these structures in DATA segment */ 329 static struct exynos_gpio_pin_group *exynos_pin_groups = NULL; 330 static int exynos_n_pin_groups = 0; 331 332 static struct exynos_gpio_softc exynos_gpio_sc = {}; 333 334 335 CFATTACH_DECL_NEW(exynos_gpio, sizeof(struct exynos_gpio_softc), 336 exynos_gpio_match, exynos_gpio_attach, NULL, NULL); 337 338 339 static int 340 exynos_gpio_match(device_t parent, cfdata_t cf, void *aux) 341 { 342 #ifdef DIAGNOSTIC 343 struct exyo_attach_args * const exyoaa = aux; 344 struct exyo_locators *loc = &exyoaa->exyo_loc; 345 #endif 346 347 /* no locators expected */ 348 KASSERT(loc->loc_offset == 0); 349 KASSERT(loc->loc_size == 0); 350 KASSERT(loc->loc_port == EXYOCF_PORT_DEFAULT); 351 352 /* there can only be one */ 353 if (exynos_gpio_sc.sc_dev != NULL) 354 return 0; 355 return 1; 356 } 357 358 359 #if NGPIO > 0 360 static void 361 exynos_gpio_config_pins(device_t self) 362 { 363 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 364 struct exynos_gpio_pin_group *grp; 365 struct gpiobus_attach_args gba; 366 gpio_pin_t *pin, *pins; 367 size_t pin_count = 0; 368 int i, bit, mask, pincaps, data; 369 370 if (exynos_n_pin_groups == 0) 371 return; 372 373 /* find out how many pins we can offer */ 374 pin_count = 0; 375 for (i = 0; i < exynos_n_pin_groups; i++) { 376 grp = &exynos_pin_groups[i]; 377 mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 378 pin_count += popcount32(mask); 379 } 380 381 /* if no pins available, don't proceed */ 382 if (pin_count == 0) 383 return; 384 385 /* allocate pin data */ 386 pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count, KM_SLEEP); 387 KASSERT(pins); 388 389 pincaps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 390 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 391 392 /* add all pins */ 393 pin = pins; 394 for (i = 0; i < exynos_n_pin_groups; i++) { 395 grp = &exynos_pin_groups[i]; 396 mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 397 if (mask == 0) 398 continue; 399 gba.gba_gc = &grp->grp_gc_tag; 400 gba.gba_pins = pin; 401 data = bus_space_read_1(sc->sc_bst, grp->grp_bsh, 402 EXYNOS_GPIO_DAT); 403 for (bit = 0; mask != 0; mask >>= 1, data >>= 1, bit++) { 404 if (mask & 1) { 405 pin->pin_num = bit + (i << 3); 406 pin->pin_caps = pincaps; 407 pin->pin_flags = pincaps; 408 pin->pin_state = (data & 1) != 0; 409 pin++; 410 } 411 } 412 gba.gba_npins = pin - gba.gba_pins; 413 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 414 } 415 } 416 #endif 417 418 419 static void 420 exynos_gpio_attach(device_t parent, device_t self, void *aux) 421 { 422 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 423 struct exyo_attach_args * const exyoaa = aux; 424 struct exynos_gpio_pin_group *grp; 425 prop_dictionary_t dict = device_properties(self); 426 uint32_t nc; 427 char scrap[16]; 428 int i; 429 430 /* construct softc */ 431 sc->sc_dev = self; 432 433 /* we use the core bushandle here */ 434 sc->sc_bst = exyoaa->exyo_core_bst; 435 sc->sc_bsh = exyoaa->exyo_core_bsh; 436 437 exynos_gpio_bootstrap(); 438 if (exynos_n_pin_groups == 0) { 439 printf(": disabled, no pins defined\n"); 440 return; 441 } 442 443 KASSERT(exynos_pin_groups); 444 KASSERT(exynos_n_pin_groups); 445 446 aprint_naive("\n"); 447 aprint_normal("\n"); 448 449 /* go trough all pin groups */ 450 for (i = 0; i < exynos_n_pin_groups; i++) { 451 grp = &exynos_pin_groups[i]; 452 snprintf(scrap, sizeof(scrap), "nc-%s", grp->grp_name); 453 if (prop_dictionary_get_uint32(dict, scrap, &nc)) { 454 KASSERT((~grp->grp_pin_mask & nc) == 0); 455 /* switch off the pins we have signalled NC */ 456 grp->grp_pin_mask &= ~nc; 457 #if 0 458 printf("%s: %-4s inuse_mask %02x, pin_mask %02x\n", 459 __func__, grp->grp_name, 460 grp->grp_pin_inuse_mask, grp->grp_pin_mask); 461 #endif 462 } 463 } 464 465 #if NGPIO > 0 466 config_defer(self, exynos_gpio_config_pins); 467 #endif 468 } 469 470 471 /* pin access functions */ 472 static u_int 473 exynos_gpio_get_pin_func(const struct exynos_gpio_pin_cfg *cfg, int pin) 474 { 475 const u_int shift = (pin & 7) << 2; 476 477 return (cfg->cfg >> shift) & 0x0f; 478 } 479 480 481 static void 482 exynos_gpio_set_pin_func(struct exynos_gpio_pin_cfg *cfg, 483 int pin, int func) 484 { 485 const u_int shift = (pin & 7) << 2; 486 487 cfg->cfg &= ~(0x0f << shift); 488 cfg->cfg |= func << shift; 489 } 490 491 492 static void 493 exynos_gpio_set_pin_pull(struct exynos_gpio_pin_cfg *cfg, int pin, int pull) 494 { 495 const u_int shift = (pin & 7) << 1; 496 497 cfg->pud &= ~(0x3 << shift); 498 cfg->pud |= pull << shift; 499 } 500 501 502 static int 503 exynos_gpio_pin_read(void *cookie, int pin) 504 { 505 struct exynos_gpio_pin_group * const grp = cookie; 506 507 KASSERT(pin < grp->grp_bits); 508 return (bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 509 EXYNOS_GPIO_DAT) >> pin) & 1; 510 } 511 512 513 static void 514 exynos_gpio_pin_write(void *cookie, int pin, int value) 515 { 516 struct exynos_gpio_pin_group * const grp = cookie; 517 int val; 518 519 KASSERT(pin < grp->grp_bits); 520 val = bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 521 EXYNOS_GPIO_DAT); 522 val &= ~__BIT(pin); 523 if (value) 524 val |= __BIT(pin); 525 bus_space_write_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 526 EXYNOS_GPIO_DAT, val); 527 } 528 529 530 static void 531 exynos_gpio_update_cfg_regs(struct exynos_gpio_pin_group *grp, 532 const struct exynos_gpio_pin_cfg *ncfg) 533 { 534 bus_space_tag_t bst = &exynos_bs_tag; 535 536 if (grp->grp_cfg.cfg != ncfg->cfg) { 537 bus_space_write_4(bst, grp->grp_bsh, 538 EXYNOS_GPIO_CON, ncfg->cfg); 539 grp->grp_cfg.cfg = ncfg->cfg; 540 } 541 if (grp->grp_cfg.pud != ncfg->pud) { 542 bus_space_write_4(bst, grp->grp_bsh, 543 EXYNOS_GPIO_PUD, ncfg->pud); 544 grp->grp_cfg.pud = ncfg->pud; 545 } 546 547 /* the following attributes are not yet setable */ 548 #if 0 549 if (grp->grp_cfg.drv != ncfg->drv) { 550 bus_space_write_4(bst, grp->grp_bsh, 551 EXYNOS_GPIO_DRV, ncfg->drv); 552 grp->grp_cfg.drv = ncfg->drv; 553 } 554 if (grp->grp_cfg.conpwd != ncfg->conpwd) { 555 bus_space_write_4(bst, grp->grp_bsh, 556 EXYNOS_GPIO_CONPWD, ncfg->conpwd); 557 grp->grp_cfg.conpwd = ncfg->conpwd; 558 } 559 if (grp->grp_cfg.pudpwd != ncfg->pudpwd) { 560 bus_space_write_4(bst, grp->grp_bsh, 561 EXYNOS_GPIO_PUDPWD, ncfg->pudpwd); 562 grp->grp_cfg.pudpwd = ncfg->pudpwd; 563 } 564 #endif 565 } 566 567 568 static void 569 exynos_gpio_pin_ctl(void *cookie, int pin, int flags) 570 { 571 struct exynos_gpio_pin_group * const grp = cookie; 572 struct exynos_gpio_pin_cfg ncfg = grp->grp_cfg; 573 int pull; 574 575 /* honour pullup requests */ 576 pull = EXYNOS_GPIO_PIN_FLOAT; 577 if (flags & GPIO_PIN_PULLUP) 578 pull = EXYNOS_GPIO_PIN_PULL_UP; 579 if (flags & GPIO_PIN_PULLDOWN) 580 pull = EXYNOS_GPIO_PIN_PULL_DOWN; 581 exynos_gpio_set_pin_pull(&ncfg, pin, pull); 582 583 /* honour i/o */ 584 if (flags & GPIO_PIN_INPUT) 585 exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_INPUT); 586 if (flags & GPIO_PIN_OUTPUT) 587 exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_OUTPUT); 588 589 /* update any config registers that changed */ 590 exynos_gpio_update_cfg_regs(grp, &ncfg); 591 } 592 593 594 bool 595 exynos_gpio_pinset_available(const struct exynos_gpio_pinset *req) 596 { 597 struct exynos_gpio_pin_group *grp; 598 int i, n, inuse; 599 600 KASSERT(req); 601 if (exynos_n_pin_groups == 0) 602 return false; 603 604 /* we need a pinset group */ 605 if (strlen(req->pinset_group) == 0) 606 return false; 607 608 /* determine which group is requested */ 609 grp = NULL; 610 for (i = 0; i < exynos_n_pin_groups; i++) { 611 grp = &exynos_pin_groups[i]; 612 if (strcmp(req->pinset_group, grp->grp_name) == 0) 613 break; 614 } 615 /* found? */ 616 if (i == exynos_n_pin_groups) 617 return false; 618 KASSERT(grp); 619 620 /* fail unconnected pins */ 621 if (req->pinset_mask & ~grp->grp_pin_mask) 622 return false; 623 624 /* if none in use, they are available */ 625 if (req->pinset_mask & ~grp->grp_pin_inuse_mask) 626 return true; 627 628 /* OK, so some are in use; now see if the request is compatible */ 629 inuse = req->pinset_mask & grp->grp_pin_inuse_mask; 630 for (i = 0; inuse; i++, inuse >>= 1) { 631 /* try to be smart by skipping zero's */ 632 n = ffs(inuse) -1; 633 i += n; 634 inuse >>= n; 635 /* this pin is in use, check its usage */ 636 if (exynos_gpio_get_pin_func(&grp->grp_cfg, i) != req->pinset_func) 637 return false; 638 } 639 640 /* seems to be OK */ 641 return true; 642 } 643 644 645 void 646 exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *req) 647 { 648 struct exynos_gpio_pin_group *grp; 649 struct exynos_gpio_pin_cfg ncfg; 650 int i, n, todo; 651 652 KASSERT(req); 653 KASSERT(exynos_gpio_pinset_available(req)); 654 655 /* determine which group is requested */ 656 grp = NULL; 657 for (i = 0; i < exynos_n_pin_groups; i++) { 658 grp = &exynos_pin_groups[i]; 659 if (strcmp(req->pinset_group, grp->grp_name) == 0) 660 break; 661 } 662 KASSERT(grp); 663 664 /* check if all the pins have the right function */ 665 if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0) 666 return; 667 668 /* copy current config for update routine */ 669 ncfg = grp->grp_cfg; 670 671 /* update the function of each pin that is not in use */ 672 todo = req->pinset_mask & grp->grp_pin_inuse_mask; 673 for (i = 0; todo; i++, todo >>= 1) { 674 /* try to be smart by skipping zero's */ 675 n = ffs(todo) -1; 676 i += n; 677 todo >>= n; 678 /* change the function of this pin */ 679 exynos_gpio_set_pin_func(&ncfg, i, req->pinset_func); 680 } 681 682 /* update config registers */ 683 exynos_gpio_update_cfg_regs(grp, &ncfg); 684 685 /* mark pins in use */ 686 grp->grp_pin_inuse_mask |= req->pinset_mask; 687 } 688 689 690 /* get a pindata structure from a pinset structure */ 691 void 692 exynos_gpio_pinset_to_pindata(const struct exynos_gpio_pinset *req, int pinnr, 693 struct exynos_gpio_pindata *pd) 694 { 695 struct exynos_gpio_pin_group *grp; 696 int i; 697 698 KASSERT(req); 699 KASSERT(pd); 700 KASSERT(req->pinset_mask & __BIT(pinnr)); 701 702 /* determine which group is requested */ 703 grp = NULL; 704 for (i = 0; i < exynos_n_pin_groups; i++) { 705 grp = &exynos_pin_groups[i]; 706 if (strcmp(req->pinset_group, grp->grp_name) == 0) 707 break; 708 } 709 KASSERT(grp); 710 711 pd->pd_gc = &grp->grp_gc_tag; 712 pd->pd_pin = pinnr; 713 } 714 715 716 /* XXXRPZ This release doesn't grock multiple usages! */ 717 void 718 exynos_gpio_pinset_release(const struct exynos_gpio_pinset *req) 719 { 720 struct exynos_gpio_pin_group *grp; 721 int i; 722 723 KASSERT(!exynos_gpio_pinset_available(req)); 724 725 /* determine which group is requested */ 726 grp = NULL; 727 for (i = 0; i < exynos_n_pin_groups; i++) { 728 grp = &exynos_pin_groups[i]; 729 if (strcmp(req->pinset_group, grp->grp_name) == 0) 730 break; 731 } 732 KASSERT(grp); 733 734 /* bluntly mark as not being in use */ 735 grp->grp_pin_inuse_mask &= ~req->pinset_mask; 736 } 737 738 739 /* 740 * name convention : 741 * pin = <func><groupname><pinnr>[<pud>] 742 * func = '<' | '>' 743 * pinnr = '['['0'-'7']']' 744 * pud = 'F' | 'U' | 'D' 745 * 746 * example "<GPC1[0]", ">GPB[0]" 747 */ 748 749 bool 750 exynos_gpio_pin_reserve(const char *name, struct exynos_gpio_pindata *pd) 751 { 752 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 753 struct exynos_gpio_pin_group *grp; 754 struct exynos_gpio_pin_cfg ncfg; 755 prop_dictionary_t dict = device_properties(sc->sc_dev); 756 const char *pin_data; 757 char grp_name[15], *pos; 758 int func, pud, pinnr; 759 int pi, i; 760 761 if (exynos_n_pin_groups == 0) 762 return false; 763 764 /* do we have a named pin description? */ 765 if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data)) 766 return false; 767 768 KASSERT(strlen(pin_data) < 10); 769 if (!(pin_data[0] == '>' || pin_data[0] == '<')) { 770 printf("%s: malformed pin data in '%s', missing direction\n", 771 __func__, pin_data); 772 return false; 773 } 774 775 func = (pin_data[0] == '<') ? 776 EXYNOS_GPIO_FUNC_INPUT : EXYNOS_GPIO_FUNC_OUTPUT; 777 778 /* find groupname */ 779 pi = 1; pos = grp_name; 780 while (pin_data[pi] && pin_data[pi] != '[') { 781 *pos++ = pin_data[pi++]; 782 } 783 if (pin_data[pi] != '[') { 784 printf("%s: malformed pin data in '%s', missing '['\n", 785 __func__, pin_data); 786 return false; 787 } 788 *pos++ = (char) 0; 789 790 /* skip '[' */ 791 pi++; 792 if (!(pin_data[pi] >= '0' && pin_data[pi] <= '7')) { 793 printf("%s: malformed pin data in '%s', bad pin number\n", 794 __func__, pin_data); 795 return false; 796 } 797 pinnr = pin_data[pi] - '0'; 798 799 /* skip digit */ 800 pi++; 801 if ((pin_data[pi] != ']')) { 802 printf("%s: malformed pin data in '%s', missing end ']'\n", 803 __func__, pin_data); 804 return false; 805 } 806 807 /* skip ']' */ 808 pi++; 809 pud = EXYNOS_GPIO_PIN_FLOAT; 810 switch (tolower(pin_data[pi])) { 811 case (char) 0: 812 break; 813 case 'f': 814 pud = EXYNOS_GPIO_PIN_FLOAT; 815 break; 816 case 'u': 817 pud = EXYNOS_GPIO_PIN_PULL_UP; 818 break; 819 case 'd': 820 pud = EXYNOS_GPIO_PIN_PULL_DOWN; 821 break; 822 default: 823 printf("%s: malformed pin data in '%s', expecting " 824 "optional pull up/down or float argument\n", 825 __func__, pin_data); 826 return false; 827 } 828 829 /* determine which group is requested */ 830 grp = NULL; 831 for (i = 0; i < exynos_n_pin_groups; i++) { 832 grp = &exynos_pin_groups[i]; 833 if (strcmp(grp_name, grp->grp_name) == 0) 834 break; 835 } 836 837 /* found? */ 838 if (i >= exynos_n_pin_groups) { 839 printf("%s: malformed pin data in '%s', " 840 "no such pin group name\n", 841 __func__, grp_name); 842 return false; 843 } 844 KASSERT(grp); 845 846 /* in range? */ 847 if (pinnr >= grp->grp_bits) 848 return false; 849 850 /* marked as connected? */ 851 if ((grp->grp_pin_mask & __BIT(pinnr)) == 0) 852 return false; 853 854 /* it better not be used!! this is not taken lightly */ 855 KASSERT((grp->grp_pin_inuse_mask & __BIT(pinnr)) == 0); 856 857 /* update our pin configuration */ 858 ncfg = grp->grp_cfg; 859 exynos_gpio_set_pin_func(&ncfg, pinnr, func); 860 exynos_gpio_set_pin_pull(&ncfg, pinnr, pud); 861 exynos_gpio_update_cfg_regs(grp, &ncfg); 862 863 grp->grp_pin_inuse_mask |= __BIT(pinnr); 864 grp->grp_pin_mask &= ~__BIT(pinnr); 865 866 pd->pd_gc = &grp->grp_gc_tag; 867 pd->pd_pin = pinnr; 868 869 return true; 870 } 871 872 873 /* bootstrapping */ 874 void 875 exynos_gpio_bootstrap(void) 876 { 877 bus_space_tag_t bst = &exynos_bs_tag; 878 struct exynos_gpio_pin_group *grp; 879 struct gpio_chipset_tag *gc_tag; 880 int i; 881 882 /* determine what we're running on */ 883 #ifdef EXYNOS4 884 if (IS_EXYNOS4_P()) { 885 exynos_pin_groups = exynos4_pin_groups; 886 exynos_n_pin_groups = __arraycount(exynos4_pin_groups); 887 } 888 #endif 889 #ifdef EXYNOS5 890 if (IS_EXYNOS5_P()) { 891 exynos_pin_groups = exynos5_pin_groups; 892 exynos_n_pin_groups = __arraycount(exynos5_pin_groups); 893 } 894 #endif 895 896 if (exynos_n_pin_groups == 0) 897 return; 898 899 /* init groups */ 900 for (i = 0; i < exynos_n_pin_groups; i++) { 901 grp = &exynos_pin_groups[i]; 902 gc_tag = &grp->grp_gc_tag; 903 904 bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 905 grp->grp_core_offset, EXYNOS_GPIO_GRP_SIZE, 906 &grp->grp_bsh); 907 KASSERT(&grp->grp_bsh); 908 909 grp->grp_pin_mask = __BIT(grp->grp_bits) - 1; 910 grp->grp_pin_inuse_mask = 0; 911 912 gc_tag->gp_cookie = grp; 913 gc_tag->gp_pin_read = exynos_gpio_pin_read; 914 gc_tag->gp_pin_write = exynos_gpio_pin_write; 915 gc_tag->gp_pin_ctl = exynos_gpio_pin_ctl; 916 917 /* read in our initial settings */ 918 grp->grp_cfg.cfg = bus_space_read_4(bst, grp->grp_bsh, 919 EXYNOS_GPIO_CON); 920 grp->grp_cfg.pud = bus_space_read_4(bst, grp->grp_bsh, 921 EXYNOS_GPIO_PUD); 922 grp->grp_cfg.drv = bus_space_read_4(bst, grp->grp_bsh, 923 EXYNOS_GPIO_DRV); 924 grp->grp_cfg.conpwd = bus_space_read_4(bst, grp->grp_bsh, 925 EXYNOS_GPIO_CONPWD); 926 grp->grp_cfg.pudpwd = bus_space_read_4(bst, grp->grp_bsh, 927 EXYNOS_GPIO_PUDPWD); 928 929 /* 930 * Normally we would count the busy pins. 931 * 932 * We can't check inuse here since uboot has used pins for its 933 * own use and left them configured forbidding us to use pins 934 * for our own sake. 935 */ 936 #if 0 937 for (int j = 0, int mask = 1; 938 (mask & grp->grp_pin_mask) != 0; 939 j++, mask <<= 1) { 940 int func = exynos_gpio_get_pin_func(&grp->grp_cfg, j); 941 if (func > EXYNOS_GPIO_FUNC_INPUT) { 942 printf("%s: %s[%d] func %d\n", __func__, 943 grp->grp_name, j, func); 944 } 945 } 946 #endif 947 } 948 #if 0 949 printf("\n"); 950 printf("default NC pin list generated: \n"); 951 /* enable this for default NC pins list generation */ 952 for (i = 0; i < exynos_n_pin_groups; i++) { 953 grp = &exynos_pin_groups[i]; 954 printf("prop_dictionary_set_uint32(dict, \"nc-%s\", " 955 "0x%02x - 0b00000000);\n", 956 grp->grp_name, grp->grp_pin_mask); 957 } 958 #endif 959 } 960 961
Indexes created Tue Sep 30 20:09:53 GMT 2025