exynos_gpio.c revision 1.8
1 /*- 2 * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Reinoud Zandijk 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "opt_exynos.h" 31 #include "opt_arm_debug.h" 32 #include "gpio.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.8 2014/08/26 11:49:39 reinoud Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/device.h> 40 #include <sys/intr.h> 41 #include <sys/systm.h> 42 #include <sys/kmem.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_io.h> 46 #include <arm/samsung/exynos_intr.h> 47 48 #include <sys/gpio.h> 49 #include <dev/gpio/gpiovar.h> 50 51 static int exynos_gpio_match(device_t, cfdata_t, void *); 52 static void exynos_gpio_attach(device_t, device_t, void *); 53 54 static int exynos_gpio_pin_read(void *, int); 55 static void exynos_gpio_pin_write(void *, int, int); 56 static void exynos_gpio_pin_ctl(void *, int, int); 57 58 struct exynos_gpio_pin_cfg { 59 uint32_t cfg; 60 uint32_t pud; 61 uint32_t drv; 62 uint32_t conpwd; 63 uint32_t pudpwd; 64 }; 65 66 struct exynos_gpio_pin_group { 67 const char grp_name[6]; 68 const bus_addr_t grp_core_offset; 69 const uint8_t grp_bits; 70 71 uint8_t grp_pin_mask; 72 uint8_t grp_pin_inuse_mask; 73 bus_space_handle_t grp_bsh; 74 struct exynos_gpio_pin_cfg grp_cfg; 75 struct gpio_chipset_tag grp_gc_tag; 76 }; 77 78 79 #define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o)) 80 #define GPIO_GRP(v, s, o, n, b) \ 81 { \ 82 .grp_name = #n, \ 83 .grp_core_offset = GPIO_REG(v,s,o), \ 84 .grp_bits = b,\ 85 } 86 87 #ifdef EXYNOS4 88 /* 89 * Exynos 4412 contains 304 multi-functional input/output port pins and 164 90 * memory port pins. There are 37 general port groups and two memory port 91 * groups. They are: 92 * 93 * GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow 94 * control, and/or 2xI2C 95 * 96 * GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM 97 * 98 * GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 99 * and/or SPI 100 * 101 * GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI 102 * 103 * GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F, 104 * HSI, and/ or Trace I/F 105 * 106 * GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F 107 * 108 * GPJ0, GPJ1: 13 in/out ports-CAM I/F 109 * 110 * GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC 111 * (8-bit MMC)), and/or GPS debugging I/F 112 * 113 * GPL0, GPL1: 11 in/out ports-GPS I/F 114 * 115 * GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F 116 * 117 * GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad 118 * I/F 119 * 120 * GPZ: 7 in/out ports-low Power I2S and/or PCM 121 * 122 * GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One 123 * NAND) 124 * 125 * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information 126 * about EBI configuration, refer to Chapter 5, and 6) 127 * 128 * MP1_0-MP1_9: 78 DRAM1 ports. NOTE: GPIO registers does not control these 129 * ports. 130 * 131 * MP2_0-MP2_9: 78 DRAM2 ports. NOTE: GPIO registers does not control these 132 * ports. 133 * 134 * ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK 135 * 136 * ETC7, ETC8 : 4 clock port for C2C 137 * 138 */ 139 140 static struct exynos_gpio_pin_group exynos4_pin_groups[] = { 141 GPIO_GRP(4, LEFT, 0x0000, GPA0, 8), 142 GPIO_GRP(4, LEFT, 0x0020, GPA1, 6), 143 GPIO_GRP(4, LEFT, 0x0040, GPB, 8), 144 GPIO_GRP(4, LEFT, 0x0060, GPC0, 5), 145 GPIO_GRP(4, LEFT, 0x0080, GPC1, 5), 146 GPIO_GRP(4, LEFT, 0x00A0, GPD0, 4), 147 GPIO_GRP(4, LEFT, 0x00C0, GPD1, 4), 148 GPIO_GRP(4, LEFT, 0x0180, GPF0, 8), 149 GPIO_GRP(4, LEFT, 0x01A0, GPF1, 8), 150 GPIO_GRP(4, LEFT, 0x01C0, GPF2, 8), 151 GPIO_GRP(4, LEFT, 0x01E0, GPF3, 8), 152 GPIO_GRP(4, LEFT, 0x0240, GPJ0, 8), 153 GPIO_GRP(4, LEFT, 0x0260, GPJ1, 5), 154 /* EXTINT skipped */ 155 156 GPIO_GRP(4, RIGHT, 0x0040, GPK0, 8), 157 GPIO_GRP(4, RIGHT, 0x0060, GPK1, 8), 158 GPIO_GRP(4, RIGHT, 0x0080, GPK2, 7), 159 GPIO_GRP(4, RIGHT, 0x00A0, GPK3, 7), 160 GPIO_GRP(4, RIGHT, 0x00C0, GPL0, 7), 161 GPIO_GRP(4, RIGHT, 0x00E0, GPL1, 2), 162 GPIO_GRP(4, RIGHT, 0x0100, GPL2, 8), 163 GPIO_GRP(4, RIGHT, 0x0120, GPY0, 6), 164 GPIO_GRP(4, RIGHT, 0x0140, GPY1, 4), 165 GPIO_GRP(4, RIGHT, 0x0160, GPY2, 6), 166 GPIO_GRP(4, RIGHT, 0x0180, GPY3, 8), 167 GPIO_GRP(4, RIGHT, 0x01A0, GPY4, 8), 168 GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8), 169 GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8), 170 GPIO_GRP(4, RIGHT, 0x0200, ETC0, 6), 171 GPIO_GRP(4, RIGHT, 0x0220, ETC6, 7), 172 GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8), 173 GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7), 174 GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5), 175 GPIO_GRP(4, RIGHT, 0x02C0, GPM3, 8), 176 GPIO_GRP(4, RIGHT, 0x02E0, GPM4, 8), 177 /* EXTINT skipped */ 178 GPIO_GRP(4, RIGHT, 0x0C00, GPX0, 8), 179 GPIO_GRP(4, RIGHT, 0x0C20, GPX1, 8), 180 GPIO_GRP(4, RIGHT, 0x0C40, GPX2, 8), 181 GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8), 182 /* EXTINT skipped */ 183 184 GPIO_GRP(4, I2S0, 0x0000, GPZ, 8), 185 /* EXTINT skipped */ 186 187 GPIO_GRP(4, C2C, 0x0000, GPV0, 8), 188 GPIO_GRP(4, C2C, 0x0020, GPV1, 8), 189 GPIO_GRP(4, C2C, 0x0040, ETC7, 2), 190 GPIO_GRP(4, C2C, 0x0060, GPV2, 8), 191 GPIO_GRP(4, C2C, 0x0080, GPV3, 8), 192 GPIO_GRP(4, C2C, 0x00A0, ETC8, 2), 193 GPIO_GRP(4, C2C, 0x00C0, GPV4, 2), 194 /* EXTINT skipped */ 195 }; 196 #endif 197 198 199 #ifdef EXYNOS5 200 201 /* 202 * Exynos 5250 contains 253 multi-functional input/output port pins and 160 203 * memory port pins. There are 39 general port groups and 2 memory port 204 * groups. They are: 205 * 206 * GPA0, GPA1: 14 in/out ports-2xUART with flow control, UART without flow 207 * control, and/or 2xI2C , and/or2xHS-I2C 208 * 209 * GPA2: 8 in/out ports-2xSPI, and/or I2C 210 * 211 * GPB0, GPB1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 212 * and/or SPI 213 * 214 * GPB2, GPB3: 8 in/out ports-PWM, I2C, and/or I2C ,and/or HS-I2C 215 * 216 * GPC0, GPC1: 11 in/out ports-1xMMC (8-bit MMC) I/F 217 * 218 * GPC2: 7 in/out ports-1xMMC (4-bit MMC) I/F 219 * 220 * GPC3, GPC4: 14 in/out ports-2xMMC (4-bit MMC) and/or 1xMMC (8-bit MMC) I/F 221 * 222 * GPD0: 4 pin/out ports-1xUART with flow control I/F 223 * 224 * GPD1: 8 pin/out ports-HSI I/F 225 * 226 * GPE0, GPE1, GPF0, GPF1, GPG0, GPG1, GPG2, GPH0, GPH1: 48 in/out ports-CAM 227 * I/F, and/or Trace I/F 228 * 229 * GPV0, GPV1, GPV2, GPV3, GPV4: 34 in/out ports-C2C I/F 230 * 231 * GPX0, 1, 2, 3: 32 in/out port-external wake-up interrupts (up-to 32-bit), 232 * and/or AUD I/F, and/or MFC I/F (GPX groups are in alive region) 233 * 234 * GPY0, GPY1, GPY2: 16 in/out ports-control signals of EBI (SROM) 235 * 236 * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI 237 * 238 * GPZ: 7 in/out ports-low power I2S and/or PCM 239 * 240 * MP1_0-MP1_10: 80 DRAM1 ports NOTE: GPIO registers do not control these 241 * ports. 242 * 243 * MP2_0-MP2_10: 80 DRAM2 ports NOTE: GPIO registers do not control these 244 * ports. 245 * 246 * ETC0, ETC5, ETC6, ETC7, ETC8: 22 in/out ETC ports-JTAG, C2C_CLK (Rx), 247 * RESET, CLOCK, USBOTG and USB3, C2C_CLK (Tx) 248 */ 249 250 static struct exynos_gpio_pin_group exynos5_pin_groups[] = { 251 GPIO_GRP(5, LEFT, 0x0000, GPA0, 8), 252 GPIO_GRP(5, LEFT, 0x0020, GPA1, 6), 253 GPIO_GRP(5, LEFT, 0x0040, GPA2, 8), 254 GPIO_GRP(5, LEFT, 0x0060, GPB0, 5), 255 GPIO_GRP(5, LEFT, 0x0080, GPB1, 5), 256 GPIO_GRP(5, LEFT, 0x00A0, GPB2, 4), 257 GPIO_GRP(5, LEFT, 0x00C0, GPB3, 4), 258 GPIO_GRP(5, LEFT, 0x00E0, GPC0, 7), 259 GPIO_GRP(5, LEFT, 0x0100, GPC1, 4), 260 GPIO_GRP(5, LEFT, 0x0120, GPC2, 7), 261 GPIO_GRP(5, LEFT, 0x0140, GPC3, 7), 262 GPIO_GRP(5, LEFT, 0x0160, GPD0, 4), 263 GPIO_GRP(5, LEFT, 0x0180, GPD1, 8), 264 GPIO_GRP(5, LEFT, 0x01A0, GPY0, 6), 265 GPIO_GRP(5, LEFT, 0x01C0, GPY1, 4), 266 GPIO_GRP(5, LEFT, 0x01E0, GPY2, 6), 267 GPIO_GRP(5, LEFT, 0x0200, GPY3, 8), 268 GPIO_GRP(5, LEFT, 0x0220, GPY4, 8), 269 GPIO_GRP(5, LEFT, 0x0240, GPY5, 8), 270 GPIO_GRP(5, LEFT, 0x0260, GPY6, 8), 271 GPIO_GRP(5, LEFT, 0x0280, ETC0, 6), 272 GPIO_GRP(5, LEFT, 0x02A0, ETC6, 7), 273 GPIO_GRP(5, LEFT, 0x02C0, ETC7, 5), 274 GPIO_GRP(5, LEFT, 0x02E0, GPC4, 7), 275 /* EXTINT skipped */ 276 GPIO_GRP(5, LEFT, 0x0C00, GPX0, 8), 277 GPIO_GRP(5, LEFT, 0x0C20, GPX1, 8), 278 GPIO_GRP(5, LEFT, 0x0C40, GPX2, 8), 279 GPIO_GRP(5, LEFT, 0x0C60, GPX3, 8), 280 /* EXTINT skipped */ 281 282 GPIO_GRP(5, RIGHT, 0x0000, GPE0, 8), 283 GPIO_GRP(5, RIGHT, 0x0020, GPE1, 2), 284 GPIO_GRP(5, RIGHT, 0x0040, GPF0, 4), 285 GPIO_GRP(5, RIGHT, 0x0060, GPF1, 4), 286 GPIO_GRP(5, RIGHT, 0x0080, GPG0, 8), 287 GPIO_GRP(5, RIGHT, 0x00A0, GPG1, 8), 288 GPIO_GRP(5, RIGHT, 0x00C0, GPG2, 2), 289 GPIO_GRP(5, RIGHT, 0x00E0, GPH0, 4), 290 GPIO_GRP(5, RIGHT, 0x0100, GPH1, 8), 291 /* EXTINT skipped */ 292 293 GPIO_GRP(5, C2C, 0x0000, GPV0, 8), 294 GPIO_GRP(5, C2C, 0x0020, GPV1, 8), 295 GPIO_GRP(5, C2C, 0x0040, ETC5, 2), 296 GPIO_GRP(5, C2C, 0x0060, GPV2, 8), 297 GPIO_GRP(5, C2C, 0x0080, GPV3, 8), 298 GPIO_GRP(5, C2C, 0x00A0, ETC8, 2), 299 GPIO_GRP(5, C2C, 0x00C0, GPV4, 2), 300 /* EXTINT skipped */ 301 302 GPIO_GRP(5, I2S, 0x0000, GPZ, 7), 303 /* EXTINT skipped */ 304 }; 305 #endif 306 307 308 struct exynos_gpio_softc { 309 device_t sc_dev; 310 bus_space_tag_t sc_bst; 311 bus_space_handle_t sc_bsh; 312 }; 313 314 315 /* force these structures in DATA segment */ 316 static struct exynos_gpio_pin_group *exynos_pin_groups = NULL; 317 static int exynos_n_pin_groups = 0; 318 319 static struct exynos_gpio_softc exynos_gpio_sc = {}; 320 321 322 CFATTACH_DECL_NEW(exynos_gpio, sizeof(struct exynos_gpio_softc), 323 exynos_gpio_match, exynos_gpio_attach, NULL, NULL); 324 325 326 static int 327 exynos_gpio_match(device_t parent, cfdata_t cf, void *aux) 328 { 329 #ifdef DIAGNOSTIC 330 struct exyo_attach_args * const exyoaa = aux; 331 struct exyo_locators *loc = &exyoaa->exyo_loc; 332 #endif 333 334 /* no locators expected */ 335 KASSERT(loc->loc_offset == 0); 336 KASSERT(loc->loc_size == 0); 337 KASSERT(loc->loc_port == EXYOCF_PORT_DEFAULT); 338 339 /* there can only be one */ 340 if (exynos_gpio_sc.sc_dev != NULL) 341 return 0; 342 return 1; 343 } 344 345 346 #if NGPIO > 0 347 static void 348 exynos_gpio_config_pins(device_t self) 349 { 350 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 351 struct exynos_gpio_pin_group *grp; 352 struct gpiobus_attach_args gba; 353 gpio_pin_t *pin, *pins; 354 size_t pin_count = 0; 355 int i, bit, mask, pincaps, data; 356 357 if (exynos_n_pin_groups == 0) 358 return; 359 360 /* find out how many pins we can offer */ 361 pin_count = 0; 362 for (i = 0; i < exynos_n_pin_groups; i++) { 363 grp = &exynos_pin_groups[i]; 364 mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 365 pin_count += popcount32(mask); 366 } 367 368 /* if no pins available, don't proceed */ 369 if (pin_count == 0) 370 return; 371 372 /* allocate pin data */ 373 pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count, KM_SLEEP); 374 KASSERT(pins); 375 376 pincaps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 377 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 378 379 /* add all pins */ 380 pin = pins; 381 for (i = 0; i < exynos_n_pin_groups; i++) { 382 grp = &exynos_pin_groups[i]; 383 mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 384 if (mask == 0) 385 continue; 386 gba.gba_gc = &grp->grp_gc_tag; 387 gba.gba_pins = pin; 388 data = bus_space_read_1(sc->sc_bst, grp->grp_bsh, 389 EXYNOS_GPIO_DAT); 390 for (bit = 0; mask != 0; mask >>= 1, data >>= 1, bit++) { 391 if (mask & 1) { 392 pin->pin_num = bit + (i << 3); 393 pin->pin_caps = pincaps; 394 pin->pin_flags = pincaps; 395 pin->pin_state = (data & 1) != 0; 396 pin++; 397 } 398 } 399 gba.gba_npins = pin - gba.gba_pins; 400 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 401 } 402 } 403 #endif 404 405 406 static void 407 exynos_gpio_attach(device_t parent, device_t self, void *aux) 408 { 409 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 410 struct exyo_attach_args * const exyoaa = aux; 411 struct exynos_gpio_pin_group *grp; 412 prop_dictionary_t dict = device_properties(self); 413 uint32_t nc; 414 char scrap[16]; 415 int i; 416 417 /* construct softc */ 418 sc->sc_dev = self; 419 420 /* we use the core bushandle here */ 421 sc->sc_bst = exyoaa->exyo_core_bst; 422 sc->sc_bsh = exyoaa->exyo_core_bsh; 423 424 exynos_gpio_bootstrap(); 425 if (exynos_n_pin_groups == 0) { 426 printf(": disabled, no pins defined\n"); 427 return; 428 } 429 430 KASSERT(exynos_pin_groups); 431 KASSERT(exynos_n_pin_groups); 432 433 aprint_naive("\n"); 434 aprint_normal("\n"); 435 436 /* go trough all pin groups */ 437 for (i = 0; i < exynos_n_pin_groups; i++) { 438 grp = &exynos_pin_groups[i]; 439 snprintf(scrap, sizeof(scrap), "nc-%s", grp->grp_name); 440 if (prop_dictionary_get_uint32(dict, scrap, &nc)) { 441 KASSERT((~grp->grp_pin_mask & nc) == 0); 442 /* switch off the pins we have signalled NC */ 443 grp->grp_pin_mask &= ~nc; 444 #if 0 445 printf("%s: %-4s inuse_mask %02x, pin_mask %02x\n", 446 __func__, grp->grp_name, 447 grp->grp_pin_inuse_mask, grp->grp_pin_mask); 448 #endif 449 } 450 } 451 452 #if NGPIO > 0 453 config_defer(self, exynos_gpio_config_pins); 454 #endif 455 } 456 457 458 /* pin access functions */ 459 static u_int 460 exynos_gpio_get_pin_func(const struct exynos_gpio_pin_cfg *cfg, int pin) 461 { 462 const u_int shift = (pin & 7) << 2; 463 464 return (cfg->cfg >> shift) & 0x0f; 465 } 466 467 468 static void 469 exynos_gpio_set_pin_func(struct exynos_gpio_pin_cfg *cfg, 470 int pin, int func) 471 { 472 const u_int shift = (pin & 7) << 2; 473 474 cfg->cfg &= ~(0x0f << shift); 475 cfg->cfg |= func << shift; 476 } 477 478 479 static void 480 exynos_gpio_set_pin_pull(struct exynos_gpio_pin_cfg *cfg, int pin, int pull) 481 { 482 const u_int shift = (pin & 7) << 1; 483 484 cfg->pud &= ~(0x3 << shift); 485 cfg->pud |= pull << shift; 486 } 487 488 489 static int 490 exynos_gpio_pin_read(void *cookie, int pin) 491 { 492 struct exynos_gpio_pin_group * const grp = cookie; 493 494 KASSERT(pin < grp->grp_bits); 495 return (bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 496 EXYNOS_GPIO_DAT) >> pin) & 1; 497 } 498 499 500 static void 501 exynos_gpio_pin_write(void *cookie, int pin, int value) 502 { 503 struct exynos_gpio_pin_group * const grp = cookie; 504 int val; 505 506 KASSERT(pin < grp->grp_bits); 507 val = bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 508 EXYNOS_GPIO_DAT); 509 val &= ~__BIT(pin); 510 if (value) 511 val |= __BIT(pin); 512 bus_space_write_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 513 EXYNOS_GPIO_DAT, val); 514 } 515 516 517 static void 518 exynos_gpio_update_cfg_regs(struct exynos_gpio_pin_group *grp, 519 const struct exynos_gpio_pin_cfg *ncfg) 520 { 521 bus_space_tag_t bst = &exynos_bs_tag; 522 523 if (grp->grp_cfg.cfg != ncfg->cfg) { 524 bus_space_write_4(bst, grp->grp_bsh, 525 EXYNOS_GPIO_CON, ncfg->cfg); 526 grp->grp_cfg.cfg = ncfg->cfg; 527 } 528 if (grp->grp_cfg.pud != ncfg->pud) { 529 bus_space_write_4(bst, grp->grp_bsh, 530 EXYNOS_GPIO_PUD, ncfg->pud); 531 grp->grp_cfg.pud = ncfg->pud; 532 } 533 534 /* the following attributes are not yet setable */ 535 #if 0 536 if (grp->grp_cfg.drv != ncfg->drv) { 537 bus_space_write_4(bst, grp->grp_bsh, 538 EXYNOS_GPIO_DRV, ncfg->drv); 539 grp->grp_cfg.drv = ncfg->drv; 540 } 541 if (grp->grp_cfg.conpwd != ncfg->conpwd) { 542 bus_space_write_4(bst, grp->grp_bsh, 543 EXYNOS_GPIO_CONPWD, ncfg->conpwd); 544 grp->grp_cfg.conpwd = ncfg->conpwd; 545 } 546 if (grp->grp_cfg.pudpwd != ncfg->pudpwd) { 547 bus_space_write_4(bst, grp->grp_bsh, 548 EXYNOS_GPIO_PUDPWD, ncfg->pudpwd); 549 grp->grp_cfg.pudpwd = ncfg->pudpwd; 550 } 551 #endif 552 } 553 554 555 static void 556 exynos_gpio_pin_ctl(void *cookie, int pin, int flags) 557 { 558 struct exynos_gpio_pin_group * const grp = cookie; 559 struct exynos_gpio_pin_cfg ncfg = grp->grp_cfg; 560 int pull; 561 562 /* honour pullup requests */ 563 pull = EXYNOS_GPIO_PIN_FLOAT; 564 if (flags & GPIO_PIN_PULLUP) 565 pull = EXYNOS_GPIO_PIN_PULL_UP; 566 if (flags & GPIO_PIN_PULLDOWN) 567 pull = EXYNOS_GPIO_PIN_PULL_DOWN; 568 exynos_gpio_set_pin_pull(&ncfg, pin, pull); 569 570 /* honour i/o */ 571 if (flags & GPIO_PIN_INPUT) 572 exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_INPUT); 573 if (flags & GPIO_PIN_OUTPUT) 574 exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_OUTPUT); 575 576 /* update any config registers that changed */ 577 exynos_gpio_update_cfg_regs(grp, &ncfg); 578 } 579 580 581 bool 582 exynos_gpio_pinset_available(const struct exynos_gpio_pinset *req) 583 { 584 struct exynos_gpio_pin_group *grp; 585 int i, n, inuse; 586 587 KASSERT(req); 588 if (exynos_n_pin_groups == 0) 589 return false; 590 591 /* we need a pinset group */ 592 if (strlen(req->pinset_group) == 0) 593 return false; 594 595 /* determine which group is requested */ 596 grp = NULL; 597 for (i = 0; i < exynos_n_pin_groups; i++) { 598 grp = &exynos_pin_groups[i]; 599 if (strcmp(req->pinset_group, grp->grp_name) == 0) 600 break; 601 } 602 /* found? */ 603 if (i == exynos_n_pin_groups) 604 return false; 605 KASSERT(grp); 606 607 /* fail unconnected pins */ 608 if (req->pinset_mask & ~grp->grp_pin_mask) 609 return false; 610 611 /* if none in use, they are available */ 612 if (req->pinset_mask & ~grp->grp_pin_inuse_mask) 613 return true; 614 615 /* OK, so some are in use; now see if the request is compatible */ 616 inuse = req->pinset_mask & grp->grp_pin_inuse_mask; 617 for (i = 0; inuse; i++, inuse >>= 1) { 618 /* try to be smart by skipping zero's */ 619 n = ffs(inuse) -1; 620 i += n; 621 inuse >>= n; 622 /* this pin is in use, check its usage */ 623 if (exynos_gpio_get_pin_func(&grp->grp_cfg, i) != req->pinset_func) 624 return false; 625 } 626 627 /* seems to be OK */ 628 return true; 629 } 630 631 632 void 633 exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *req) 634 { 635 struct exynos_gpio_pin_group *grp; 636 struct exynos_gpio_pin_cfg ncfg; 637 int i, n, todo; 638 639 KASSERT(req); 640 KASSERT(exynos_gpio_pinset_available(req)); 641 642 /* determine which group is requested */ 643 grp = NULL; 644 for (i = 0; i < exynos_n_pin_groups; i++) { 645 grp = &exynos_pin_groups[i]; 646 if (strcmp(req->pinset_group, grp->grp_name) == 0) 647 break; 648 } 649 KASSERT(grp); 650 651 /* check if all the pins have the right function */ 652 if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0) 653 return; 654 655 /* copy current config for update routine */ 656 ncfg = grp->grp_cfg; 657 658 /* update the function of each pin that is not in use */ 659 todo = req->pinset_mask & grp->grp_pin_inuse_mask; 660 for (i = 0; todo; i++, todo >>= 1) { 661 /* try to be smart by skipping zero's */ 662 n = ffs(todo) -1; 663 i += n; 664 todo >>= n; 665 /* change the function of this pin */ 666 exynos_gpio_set_pin_func(&ncfg, i, req->pinset_func); 667 } 668 669 /* update config registers */ 670 exynos_gpio_update_cfg_regs(grp, &ncfg); 671 672 /* mark pins in use */ 673 grp->grp_pin_inuse_mask |= req->pinset_mask; 674 } 675 676 677 /* get a pindata structure from a pinset structure */ 678 void 679 exynos_gpio_pinset_to_pindata(const struct exynos_gpio_pinset *req, int pinnr, 680 struct exynos_gpio_pindata *pd) 681 { 682 struct exynos_gpio_pin_group *grp; 683 int i; 684 685 KASSERT(req); 686 KASSERT(pd); 687 KASSERT(req->pinset_mask & __BIT(pinnr)); 688 689 /* determine which group is requested */ 690 grp = NULL; 691 for (i = 0; i < exynos_n_pin_groups; i++) { 692 grp = &exynos_pin_groups[i]; 693 if (strcmp(req->pinset_group, grp->grp_name) == 0) 694 break; 695 } 696 KASSERT(grp); 697 698 pd->pd_gc = &grp->grp_gc_tag; 699 pd->pd_pin = pinnr; 700 } 701 702 703 /* XXXRPZ This release doesn't grock multiple usages! */ 704 void 705 exynos_gpio_pinset_release(const struct exynos_gpio_pinset *req) 706 { 707 struct exynos_gpio_pin_group *grp; 708 int i; 709 710 KASSERT(!exynos_gpio_pinset_available(req)); 711 712 /* determine which group is requested */ 713 grp = NULL; 714 for (i = 0; i < exynos_n_pin_groups; i++) { 715 grp = &exynos_pin_groups[i]; 716 if (strcmp(req->pinset_group, grp->grp_name) == 0) 717 break; 718 } 719 KASSERT(grp); 720 721 /* bluntly mark as not being in use */ 722 grp->grp_pin_inuse_mask &= ~req->pinset_mask; 723 } 724 725 726 /* 727 * name convention : 728 * pin = <func><groupname><pinnr>[<pud>] 729 * func = '<' | '>' 730 * pinnr = '['['0'-'7']']' 731 * pud = 'F' | 'U' | 'D' 732 * 733 * example "<GPC1[0]", ">GPB[0]" 734 */ 735 736 bool 737 exynos_gpio_pin_reserve(const char *name, struct exynos_gpio_pindata *pd) 738 { 739 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 740 struct exynos_gpio_pin_group *grp; 741 struct exynos_gpio_pin_cfg ncfg; 742 prop_dictionary_t dict = device_properties(sc->sc_dev); 743 const char *pin_data; 744 char grp_name[15], *pos; 745 int func, pud, pinnr; 746 int pi, i; 747 748 if (exynos_n_pin_groups == 0) 749 return false; 750 751 /* do we have a named pin description? */ 752 if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data)) 753 return false; 754 755 KASSERT(strlen(pin_data) < 10); 756 if (!(pin_data[0] == '>' || pin_data[0] == '<')) { 757 printf("%s: malformed pin data in '%s', missing direction\n", 758 __func__, pin_data); 759 return false; 760 } 761 762 func = (pin_data[0] == '<') ? 763 EXYNOS_GPIO_FUNC_INPUT : EXYNOS_GPIO_FUNC_OUTPUT; 764 765 /* find groupname */ 766 pi = 1; pos = grp_name; 767 while (pin_data[pi] && pin_data[pi] != '[') { 768 *pos++ = pin_data[pi++]; 769 } 770 if (pin_data[pi] != '[') { 771 printf("%s: malformed pin data in '%s', missing '['\n", 772 __func__, pin_data); 773 return false; 774 } 775 *pos++ = (char) 0; 776 777 /* skip '[' */ 778 pi++; 779 if (!(pin_data[pi] >= '0' && pin_data[pi] <= '7')) { 780 printf("%s: malformed pin data in '%s', bad pin number\n", 781 __func__, pin_data); 782 return false; 783 } 784 pinnr = pin_data[pi] - '0'; 785 786 /* skip digit */ 787 pi++; 788 if ((pin_data[pi] != ']')) { 789 printf("%s: malformed pin data in '%s', missing end ']'\n", 790 __func__, pin_data); 791 return false; 792 } 793 794 /* skip ']' */ 795 pi++; 796 pud = EXYNOS_GPIO_PIN_FLOAT; 797 switch (tolower(pin_data[pi])) { 798 case (char) 0: 799 break; 800 case 'f': 801 pud = EXYNOS_GPIO_PIN_FLOAT; 802 break; 803 case 'u': 804 pud = EXYNOS_GPIO_PIN_PULL_UP; 805 break; 806 case 'd': 807 pud = EXYNOS_GPIO_PIN_PULL_DOWN; 808 break; 809 default: 810 printf("%s: malformed pin data in '%s', expecting " 811 "optional pull up/down or float argument\n", 812 __func__, pin_data); 813 return false; 814 } 815 816 /* determine which group is requested */ 817 grp = NULL; 818 for (i = 0; i < exynos_n_pin_groups; i++) { 819 grp = &exynos_pin_groups[i]; 820 if (strcmp(grp_name, grp->grp_name) == 0) 821 break; 822 } 823 824 /* found? */ 825 if (i >= exynos_n_pin_groups) { 826 printf("%s: malformed pin data in '%s', " 827 "no such pin group name\n", 828 __func__, grp_name); 829 return false; 830 } 831 KASSERT(grp); 832 833 /* in range? */ 834 if (pinnr >= grp->grp_bits) 835 return false; 836 837 /* marked as connected? */ 838 if ((grp->grp_pin_mask & __BIT(pinnr)) == 0) 839 return false; 840 841 /* it better not be used!! this is not taken lightly */ 842 KASSERT((grp->grp_pin_inuse_mask & __BIT(pinnr)) == 0); 843 844 /* update our pin configuration */ 845 ncfg = grp->grp_cfg; 846 exynos_gpio_set_pin_func(&ncfg, pinnr, func); 847 exynos_gpio_set_pin_pull(&ncfg, pinnr, pud); 848 exynos_gpio_update_cfg_regs(grp, &ncfg); 849 850 grp->grp_pin_inuse_mask |= __BIT(pinnr); 851 grp->grp_pin_mask &= ~__BIT(pinnr); 852 853 pd->pd_gc = &grp->grp_gc_tag; 854 pd->pd_pin = pinnr; 855 856 return true; 857 } 858 859 860 /* bootstrapping */ 861 void 862 exynos_gpio_bootstrap(void) 863 { 864 bus_space_tag_t bst = &exynos_bs_tag; 865 struct exynos_gpio_pin_group *grp; 866 struct gpio_chipset_tag *gc_tag; 867 int i; 868 869 /* determine what we're running on */ 870 #ifdef EXYNOS4 871 if (IS_EXYNOS4_P()) { 872 exynos_pin_groups = exynos4_pin_groups; 873 exynos_n_pin_groups = __arraycount(exynos4_pin_groups); 874 } 875 #endif 876 #ifdef EXYNOS5 877 if (IS_EXYNOS5_P()) { 878 exynos_pin_groups = exynos5_pin_groups; 879 exynos_n_pin_groups = __arraycount(exynos5_pin_groups); 880 } 881 #endif 882 883 if (exynos_n_pin_groups == 0) 884 return; 885 886 /* init groups */ 887 for (i = 0; i < exynos_n_pin_groups; i++) { 888 grp = &exynos_pin_groups[i]; 889 gc_tag = &grp->grp_gc_tag; 890 891 bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 892 grp->grp_core_offset, EXYNOS_GPIO_GRP_SIZE, 893 &grp->grp_bsh); 894 KASSERT(&grp->grp_bsh); 895 896 grp->grp_pin_mask = __BIT(grp->grp_bits) - 1; 897 grp->grp_pin_inuse_mask = 0; 898 899 gc_tag->gp_cookie = grp; 900 gc_tag->gp_pin_read = exynos_gpio_pin_read; 901 gc_tag->gp_pin_write = exynos_gpio_pin_write; 902 gc_tag->gp_pin_ctl = exynos_gpio_pin_ctl; 903 904 /* read in our initial settings */ 905 grp->grp_cfg.cfg = bus_space_read_4(bst, grp->grp_bsh, 906 EXYNOS_GPIO_CON); 907 grp->grp_cfg.pud = bus_space_read_4(bst, grp->grp_bsh, 908 EXYNOS_GPIO_PUD); 909 grp->grp_cfg.drv = bus_space_read_4(bst, grp->grp_bsh, 910 EXYNOS_GPIO_DRV); 911 grp->grp_cfg.conpwd = bus_space_read_4(bst, grp->grp_bsh, 912 EXYNOS_GPIO_CONPWD); 913 grp->grp_cfg.pudpwd = bus_space_read_4(bst, grp->grp_bsh, 914 EXYNOS_GPIO_PUDPWD); 915 916 /* 917 * Normally we would count the busy pins. 918 * 919 * We can't check inuse here since uboot has used pins for its 920 * own use and left them configured forbidding us to use pins 921 * for our own sake. 922 */ 923 #if 0 924 for (int j = 0, int mask = 1; 925 (mask & grp->grp_pin_mask) != 0; 926 j++, mask <<= 1) { 927 int func = exynos_gpio_get_pin_func(&grp->grp_cfg, j); 928 if (func > EXYNOS_GPIO_FUNC_INPUT) { 929 printf("%s: %s[%d] func %d\n", __func__, 930 grp->grp_name, j, func); 931 } 932 } 933 #endif 934 } 935 #if 0 936 printf("\n"); 937 printf("default NC pin list generated: \n"); 938 /* enable this for default NC pins list generation */ 939 for (i = 0; i < exynos_n_pin_groups; i++) { 940 grp = &exynos_pin_groups[i]; 941 printf("prop_dictionary_set_uint32(dict, \"nc-%s\", " 942 "0x%02x - 0b00000000);\n", 943 grp->grp_name, grp->grp_pin_mask); 944 } 945 #endif 946 } 947 948
Indexes created Tue Sep 30 11:09:46 GMT 2025