exynos_gpio.c revision 1.9
1 /* $NetBSD: exynos_gpio.c,v 1.9 2014/09/05 08:01:05 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_exynos.h" 33 #include "opt_arm_debug.h" 34 #include "gpio.h" 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.9 2014/09/05 08:01:05 skrll Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/device.h> 42 #include <sys/intr.h> 43 #include <sys/systm.h> 44 #include <sys/kmem.h> 45 46 #include <arm/samsung/exynos_reg.h> 47 #include <arm/samsung/exynos_io.h> 48 #include <arm/samsung/exynos_intr.h> 49 50 #include <sys/gpio.h> 51 #include <dev/gpio/gpiovar.h> 52 53 static int exynos_gpio_match(device_t, cfdata_t, void *); 54 static void exynos_gpio_attach(device_t, device_t, void *); 55 56 static int exynos_gpio_pin_read(void *, int); 57 static void exynos_gpio_pin_write(void *, int, int); 58 static void exynos_gpio_pin_ctl(void *, int, int); 59 60 struct exynos_gpio_pin_cfg { 61 uint32_t cfg; 62 uint32_t pud; 63 uint32_t drv; 64 uint32_t conpwd; 65 uint32_t pudpwd; 66 }; 67 68 struct exynos_gpio_pin_group { 69 const char grp_name[6]; 70 const bus_addr_t grp_core_offset; 71 const uint8_t grp_bits; 72 73 uint8_t grp_pin_mask; 74 uint8_t grp_pin_inuse_mask; 75 bus_space_handle_t grp_bsh; 76 struct exynos_gpio_pin_cfg grp_cfg; 77 struct gpio_chipset_tag grp_gc_tag; 78 }; 79 80 81 #define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o)) 82 #define GPIO_GRP(v, s, o, n, b) \ 83 { \ 84 .grp_name = #n, \ 85 .grp_core_offset = GPIO_REG(v,s,o), \ 86 .grp_bits = b,\ 87 } 88 89 #ifdef EXYNOS4 90 /* 91 * Exynos 4412 contains 304 multi-functional input/output port pins and 164 92 * memory port pins. There are 37 general port groups and two memory port 93 * groups. They are: 94 * 95 * GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow 96 * control, and/or 2xI2C 97 * 98 * GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM 99 * 100 * GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 101 * and/or SPI 102 * 103 * GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI 104 * 105 * GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F, 106 * HSI, and/ or Trace I/F 107 * 108 * GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F 109 * 110 * GPJ0, GPJ1: 13 in/out ports-CAM I/F 111 * 112 * GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC 113 * (8-bit MMC)), and/or GPS debugging I/F 114 * 115 * GPL0, GPL1: 11 in/out ports-GPS I/F 116 * 117 * GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F 118 * 119 * GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad 120 * I/F 121 * 122 * GPZ: 7 in/out ports-low Power I2S and/or PCM 123 * 124 * GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One 125 * NAND) 126 * 127 * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information 128 * about EBI configuration, refer to Chapter 5, and 6) 129 * 130 * MP1_0-MP1_9: 78 DRAM1 ports. NOTE: GPIO registers does not control these 131 * ports. 132 * 133 * MP2_0-MP2_9: 78 DRAM2 ports. NOTE: GPIO registers does not control these 134 * ports. 135 * 136 * ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK 137 * 138 * ETC7, ETC8 : 4 clock port for C2C 139 * 140 */ 141 142 static struct exynos_gpio_pin_group exynos4_pin_groups[] = { 143 GPIO_GRP(4, LEFT, 0x0000, GPA0, 8), 144 GPIO_GRP(4, LEFT, 0x0020, GPA1, 6), 145 GPIO_GRP(4, LEFT, 0x0040, GPB, 8), 146 GPIO_GRP(4, LEFT, 0x0060, GPC0, 5), 147 GPIO_GRP(4, LEFT, 0x0080, GPC1, 5), 148 GPIO_GRP(4, LEFT, 0x00A0, GPD0, 4), 149 GPIO_GRP(4, LEFT, 0x00C0, GPD1, 4), 150 GPIO_GRP(4, LEFT, 0x0180, GPF0, 8), 151 GPIO_GRP(4, LEFT, 0x01A0, GPF1, 8), 152 GPIO_GRP(4, LEFT, 0x01C0, GPF2, 8), 153 GPIO_GRP(4, LEFT, 0x01E0, GPF3, 8), 154 GPIO_GRP(4, LEFT, 0x0240, GPJ0, 8), 155 GPIO_GRP(4, LEFT, 0x0260, GPJ1, 5), 156 /* EXTINT skipped */ 157 158 GPIO_GRP(4, RIGHT, 0x0040, GPK0, 8), 159 GPIO_GRP(4, RIGHT, 0x0060, GPK1, 8), 160 GPIO_GRP(4, RIGHT, 0x0080, GPK2, 7), 161 GPIO_GRP(4, RIGHT, 0x00A0, GPK3, 7), 162 GPIO_GRP(4, RIGHT, 0x00C0, GPL0, 7), 163 GPIO_GRP(4, RIGHT, 0x00E0, GPL1, 2), 164 GPIO_GRP(4, RIGHT, 0x0100, GPL2, 8), 165 GPIO_GRP(4, RIGHT, 0x0120, GPY0, 6), 166 GPIO_GRP(4, RIGHT, 0x0140, GPY1, 4), 167 GPIO_GRP(4, RIGHT, 0x0160, GPY2, 6), 168 GPIO_GRP(4, RIGHT, 0x0180, GPY3, 8), 169 GPIO_GRP(4, RIGHT, 0x01A0, GPY4, 8), 170 GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8), 171 GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8), 172 GPIO_GRP(4, RIGHT, 0x0200, ETC0, 6), 173 GPIO_GRP(4, RIGHT, 0x0220, ETC6, 7), 174 GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8), 175 GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7), 176 GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5), 177 GPIO_GRP(4, RIGHT, 0x02C0, GPM3, 8), 178 GPIO_GRP(4, RIGHT, 0x02E0, GPM4, 8), 179 /* EXTINT skipped */ 180 GPIO_GRP(4, RIGHT, 0x0C00, GPX0, 8), 181 GPIO_GRP(4, RIGHT, 0x0C20, GPX1, 8), 182 GPIO_GRP(4, RIGHT, 0x0C40, GPX2, 8), 183 GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8), 184 /* EXTINT skipped */ 185 186 GPIO_GRP(4, I2S0, 0x0000, GPZ, 8), 187 /* EXTINT skipped */ 188 189 GPIO_GRP(4, C2C, 0x0000, GPV0, 8), 190 GPIO_GRP(4, C2C, 0x0020, GPV1, 8), 191 GPIO_GRP(4, C2C, 0x0040, ETC7, 2), 192 GPIO_GRP(4, C2C, 0x0060, GPV2, 8), 193 GPIO_GRP(4, C2C, 0x0080, GPV3, 8), 194 GPIO_GRP(4, C2C, 0x00A0, ETC8, 2), 195 GPIO_GRP(4, C2C, 0x00C0, GPV4, 2), 196 /* EXTINT skipped */ 197 }; 198 #endif 199 200 201 #ifdef EXYNOS5 202 203 /* 204 * Exynos 5250 contains 253 multi-functional input/output port pins and 160 205 * memory port pins. There are 39 general port groups and 2 memory port 206 * groups. They are: 207 * 208 * GPA0, GPA1: 14 in/out ports-2xUART with flow control, UART without flow 209 * control, and/or 2xI2C , and/or2xHS-I2C 210 * 211 * GPA2: 8 in/out ports-2xSPI, and/or I2C 212 * 213 * GPB0, GPB1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, 214 * and/or SPI 215 * 216 * GPB2, GPB3: 8 in/out ports-PWM, I2C, and/or I2C ,and/or HS-I2C 217 * 218 * GPC0, GPC1: 11 in/out ports-1xMMC (8-bit MMC) I/F 219 * 220 * GPC2: 7 in/out ports-1xMMC (4-bit MMC) I/F 221 * 222 * GPC3, GPC4: 14 in/out ports-2xMMC (4-bit MMC) and/or 1xMMC (8-bit MMC) I/F 223 * 224 * GPD0: 4 pin/out ports-1xUART with flow control I/F 225 * 226 * GPD1: 8 pin/out ports-HSI I/F 227 * 228 * GPE0, GPE1, GPF0, GPF1, GPG0, GPG1, GPG2, GPH0, GPH1: 48 in/out ports-CAM 229 * I/F, and/or Trace I/F 230 * 231 * GPV0, GPV1, GPV2, GPV3, GPV4: 34 in/out ports-C2C I/F 232 * 233 * GPX0, 1, 2, 3: 32 in/out port-external wake-up interrupts (up-to 32-bit), 234 * and/or AUD I/F, and/or MFC I/F (GPX groups are in alive region) 235 * 236 * GPY0, GPY1, GPY2: 16 in/out ports-control signals of EBI (SROM) 237 * 238 * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI 239 * 240 * GPZ: 7 in/out ports-low power I2S and/or PCM 241 * 242 * MP1_0-MP1_10: 80 DRAM1 ports NOTE: GPIO registers do not control these 243 * ports. 244 * 245 * MP2_0-MP2_10: 80 DRAM2 ports NOTE: GPIO registers do not control these 246 * ports. 247 * 248 * ETC0, ETC5, ETC6, ETC7, ETC8: 22 in/out ETC ports-JTAG, C2C_CLK (Rx), 249 * RESET, CLOCK, USBOTG and USB3, C2C_CLK (Tx) 250 */ 251 252 static struct exynos_gpio_pin_group exynos5_pin_groups[] = { 253 GPIO_GRP(5, LEFT, 0x0000, GPA0, 8), 254 GPIO_GRP(5, LEFT, 0x0020, GPA1, 6), 255 GPIO_GRP(5, LEFT, 0x0040, GPA2, 8), 256 GPIO_GRP(5, LEFT, 0x0060, GPB0, 5), 257 GPIO_GRP(5, LEFT, 0x0080, GPB1, 5), 258 GPIO_GRP(5, LEFT, 0x00A0, GPB2, 4), 259 GPIO_GRP(5, LEFT, 0x00C0, GPB3, 4), 260 GPIO_GRP(5, LEFT, 0x00E0, GPC0, 7), 261 GPIO_GRP(5, LEFT, 0x0100, GPC1, 4), 262 GPIO_GRP(5, LEFT, 0x0120, GPC2, 7), 263 GPIO_GRP(5, LEFT, 0x0140, GPC3, 7), 264 GPIO_GRP(5, LEFT, 0x0160, GPD0, 4), 265 GPIO_GRP(5, LEFT, 0x0180, GPD1, 8), 266 GPIO_GRP(5, LEFT, 0x01A0, GPY0, 6), 267 GPIO_GRP(5, LEFT, 0x01C0, GPY1, 4), 268 GPIO_GRP(5, LEFT, 0x01E0, GPY2, 6), 269 GPIO_GRP(5, LEFT, 0x0200, GPY3, 8), 270 GPIO_GRP(5, LEFT, 0x0220, GPY4, 8), 271 GPIO_GRP(5, LEFT, 0x0240, GPY5, 8), 272 GPIO_GRP(5, LEFT, 0x0260, GPY6, 8), 273 GPIO_GRP(5, LEFT, 0x0280, ETC0, 6), 274 GPIO_GRP(5, LEFT, 0x02A0, ETC6, 7), 275 GPIO_GRP(5, LEFT, 0x02C0, ETC7, 5), 276 GPIO_GRP(5, LEFT, 0x02E0, GPC4, 7), 277 /* EXTINT skipped */ 278 GPIO_GRP(5, LEFT, 0x0C00, GPX0, 8), 279 GPIO_GRP(5, LEFT, 0x0C20, GPX1, 8), 280 GPIO_GRP(5, LEFT, 0x0C40, GPX2, 8), 281 GPIO_GRP(5, LEFT, 0x0C60, GPX3, 8), 282 /* EXTINT skipped */ 283 284 GPIO_GRP(5, RIGHT, 0x0000, GPE0, 8), 285 GPIO_GRP(5, RIGHT, 0x0020, GPE1, 2), 286 GPIO_GRP(5, RIGHT, 0x0040, GPF0, 4), 287 GPIO_GRP(5, RIGHT, 0x0060, GPF1, 4), 288 GPIO_GRP(5, RIGHT, 0x0080, GPG0, 8), 289 GPIO_GRP(5, RIGHT, 0x00A0, GPG1, 8), 290 GPIO_GRP(5, RIGHT, 0x00C0, GPG2, 2), 291 GPIO_GRP(5, RIGHT, 0x00E0, GPH0, 4), 292 GPIO_GRP(5, RIGHT, 0x0100, GPH1, 8), 293 /* EXTINT skipped */ 294 295 GPIO_GRP(5, C2C, 0x0000, GPV0, 8), 296 GPIO_GRP(5, C2C, 0x0020, GPV1, 8), 297 GPIO_GRP(5, C2C, 0x0040, ETC5, 2), 298 GPIO_GRP(5, C2C, 0x0060, GPV2, 8), 299 GPIO_GRP(5, C2C, 0x0080, GPV3, 8), 300 GPIO_GRP(5, C2C, 0x00A0, ETC8, 2), 301 GPIO_GRP(5, C2C, 0x00C0, GPV4, 2), 302 /* EXTINT skipped */ 303 304 GPIO_GRP(5, I2S, 0x0000, GPZ, 7), 305 /* EXTINT skipped */ 306 }; 307 #endif 308 309 310 struct exynos_gpio_softc { 311 device_t sc_dev; 312 bus_space_tag_t sc_bst; 313 bus_space_handle_t sc_bsh; 314 }; 315 316 317 /* force these structures in DATA segment */ 318 static struct exynos_gpio_pin_group *exynos_pin_groups = NULL; 319 static int exynos_n_pin_groups = 0; 320 321 static struct exynos_gpio_softc exynos_gpio_sc = {}; 322 323 324 CFATTACH_DECL_NEW(exynos_gpio, sizeof(struct exynos_gpio_softc), 325 exynos_gpio_match, exynos_gpio_attach, NULL, NULL); 326 327 328 static int 329 exynos_gpio_match(device_t parent, cfdata_t cf, void *aux) 330 { 331 #ifdef DIAGNOSTIC 332 struct exyo_attach_args * const exyoaa = aux; 333 struct exyo_locators *loc = &exyoaa->exyo_loc; 334 #endif 335 336 /* no locators expected */ 337 KASSERT(loc->loc_offset == 0); 338 KASSERT(loc->loc_size == 0); 339 KASSERT(loc->loc_port == EXYOCF_PORT_DEFAULT); 340 341 /* there can only be one */ 342 if (exynos_gpio_sc.sc_dev != NULL) 343 return 0; 344 return 1; 345 } 346 347 348 #if NGPIO > 0 349 static void 350 exynos_gpio_config_pins(device_t self) 351 { 352 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 353 struct exynos_gpio_pin_group *grp; 354 struct gpiobus_attach_args gba; 355 gpio_pin_t *pin, *pins; 356 size_t pin_count = 0; 357 int i, bit, mask, pincaps, data; 358 359 if (exynos_n_pin_groups == 0) 360 return; 361 362 /* find out how many pins we can offer */ 363 pin_count = 0; 364 for (i = 0; i < exynos_n_pin_groups; i++) { 365 grp = &exynos_pin_groups[i]; 366 mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 367 pin_count += popcount32(mask); 368 } 369 370 /* if no pins available, don't proceed */ 371 if (pin_count == 0) 372 return; 373 374 /* allocate pin data */ 375 pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count, KM_SLEEP); 376 KASSERT(pins); 377 378 pincaps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 379 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 380 381 /* add all pins */ 382 pin = pins; 383 for (i = 0; i < exynos_n_pin_groups; i++) { 384 grp = &exynos_pin_groups[i]; 385 mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask; 386 if (mask == 0) 387 continue; 388 gba.gba_gc = &grp->grp_gc_tag; 389 gba.gba_pins = pin; 390 data = bus_space_read_1(sc->sc_bst, grp->grp_bsh, 391 EXYNOS_GPIO_DAT); 392 for (bit = 0; mask != 0; mask >>= 1, data >>= 1, bit++) { 393 if (mask & 1) { 394 pin->pin_num = bit + (i << 3); 395 pin->pin_caps = pincaps; 396 pin->pin_flags = pincaps; 397 pin->pin_state = (data & 1) != 0; 398 pin++; 399 } 400 } 401 gba.gba_npins = pin - gba.gba_pins; 402 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 403 } 404 } 405 #endif 406 407 408 static void 409 exynos_gpio_attach(device_t parent, device_t self, void *aux) 410 { 411 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 412 struct exyo_attach_args * const exyoaa = aux; 413 struct exynos_gpio_pin_group *grp; 414 prop_dictionary_t dict = device_properties(self); 415 uint32_t nc; 416 char scrap[16]; 417 int i; 418 419 /* construct softc */ 420 sc->sc_dev = self; 421 422 /* we use the core bushandle here */ 423 sc->sc_bst = exyoaa->exyo_core_bst; 424 sc->sc_bsh = exyoaa->exyo_core_bsh; 425 426 exynos_gpio_bootstrap(); 427 if (exynos_n_pin_groups == 0) { 428 printf(": disabled, no pins defined\n"); 429 return; 430 } 431 432 KASSERT(exynos_pin_groups); 433 KASSERT(exynos_n_pin_groups); 434 435 aprint_naive("\n"); 436 aprint_normal("\n"); 437 438 /* go trough all pin groups */ 439 for (i = 0; i < exynos_n_pin_groups; i++) { 440 grp = &exynos_pin_groups[i]; 441 snprintf(scrap, sizeof(scrap), "nc-%s", grp->grp_name); 442 if (prop_dictionary_get_uint32(dict, scrap, &nc)) { 443 KASSERT((~grp->grp_pin_mask & nc) == 0); 444 /* switch off the pins we have signalled NC */ 445 grp->grp_pin_mask &= ~nc; 446 #if 0 447 printf("%s: %-4s inuse_mask %02x, pin_mask %02x\n", 448 __func__, grp->grp_name, 449 grp->grp_pin_inuse_mask, grp->grp_pin_mask); 450 #endif 451 } 452 } 453 454 #if NGPIO > 0 455 config_defer(self, exynos_gpio_config_pins); 456 #endif 457 } 458 459 460 /* pin access functions */ 461 static u_int 462 exynos_gpio_get_pin_func(const struct exynos_gpio_pin_cfg *cfg, int pin) 463 { 464 const u_int shift = (pin & 7) << 2; 465 466 return (cfg->cfg >> shift) & 0x0f; 467 } 468 469 470 static void 471 exynos_gpio_set_pin_func(struct exynos_gpio_pin_cfg *cfg, 472 int pin, int func) 473 { 474 const u_int shift = (pin & 7) << 2; 475 476 cfg->cfg &= ~(0x0f << shift); 477 cfg->cfg |= func << shift; 478 } 479 480 481 static void 482 exynos_gpio_set_pin_pull(struct exynos_gpio_pin_cfg *cfg, int pin, int pull) 483 { 484 const u_int shift = (pin & 7) << 1; 485 486 cfg->pud &= ~(0x3 << shift); 487 cfg->pud |= pull << shift; 488 } 489 490 491 static int 492 exynos_gpio_pin_read(void *cookie, int pin) 493 { 494 struct exynos_gpio_pin_group * const grp = cookie; 495 496 KASSERT(pin < grp->grp_bits); 497 return (bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 498 EXYNOS_GPIO_DAT) >> pin) & 1; 499 } 500 501 502 static void 503 exynos_gpio_pin_write(void *cookie, int pin, int value) 504 { 505 struct exynos_gpio_pin_group * const grp = cookie; 506 int val; 507 508 KASSERT(pin < grp->grp_bits); 509 val = bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 510 EXYNOS_GPIO_DAT); 511 val &= ~__BIT(pin); 512 if (value) 513 val |= __BIT(pin); 514 bus_space_write_1(exynos_gpio_sc.sc_bst, grp->grp_bsh, 515 EXYNOS_GPIO_DAT, val); 516 } 517 518 519 static void 520 exynos_gpio_update_cfg_regs(struct exynos_gpio_pin_group *grp, 521 const struct exynos_gpio_pin_cfg *ncfg) 522 { 523 bus_space_tag_t bst = &exynos_bs_tag; 524 525 if (grp->grp_cfg.cfg != ncfg->cfg) { 526 bus_space_write_4(bst, grp->grp_bsh, 527 EXYNOS_GPIO_CON, ncfg->cfg); 528 grp->grp_cfg.cfg = ncfg->cfg; 529 } 530 if (grp->grp_cfg.pud != ncfg->pud) { 531 bus_space_write_4(bst, grp->grp_bsh, 532 EXYNOS_GPIO_PUD, ncfg->pud); 533 grp->grp_cfg.pud = ncfg->pud; 534 } 535 536 /* the following attributes are not yet setable */ 537 #if 0 538 if (grp->grp_cfg.drv != ncfg->drv) { 539 bus_space_write_4(bst, grp->grp_bsh, 540 EXYNOS_GPIO_DRV, ncfg->drv); 541 grp->grp_cfg.drv = ncfg->drv; 542 } 543 if (grp->grp_cfg.conpwd != ncfg->conpwd) { 544 bus_space_write_4(bst, grp->grp_bsh, 545 EXYNOS_GPIO_CONPWD, ncfg->conpwd); 546 grp->grp_cfg.conpwd = ncfg->conpwd; 547 } 548 if (grp->grp_cfg.pudpwd != ncfg->pudpwd) { 549 bus_space_write_4(bst, grp->grp_bsh, 550 EXYNOS_GPIO_PUDPWD, ncfg->pudpwd); 551 grp->grp_cfg.pudpwd = ncfg->pudpwd; 552 } 553 #endif 554 } 555 556 557 static void 558 exynos_gpio_pin_ctl(void *cookie, int pin, int flags) 559 { 560 struct exynos_gpio_pin_group * const grp = cookie; 561 struct exynos_gpio_pin_cfg ncfg = grp->grp_cfg; 562 int pull; 563 564 /* honour pullup requests */ 565 pull = EXYNOS_GPIO_PIN_FLOAT; 566 if (flags & GPIO_PIN_PULLUP) 567 pull = EXYNOS_GPIO_PIN_PULL_UP; 568 if (flags & GPIO_PIN_PULLDOWN) 569 pull = EXYNOS_GPIO_PIN_PULL_DOWN; 570 exynos_gpio_set_pin_pull(&ncfg, pin, pull); 571 572 /* honour i/o */ 573 if (flags & GPIO_PIN_INPUT) 574 exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_INPUT); 575 if (flags & GPIO_PIN_OUTPUT) 576 exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_OUTPUT); 577 578 /* update any config registers that changed */ 579 exynos_gpio_update_cfg_regs(grp, &ncfg); 580 } 581 582 583 bool 584 exynos_gpio_pinset_available(const struct exynos_gpio_pinset *req) 585 { 586 struct exynos_gpio_pin_group *grp; 587 int i, n, inuse; 588 589 KASSERT(req); 590 if (exynos_n_pin_groups == 0) 591 return false; 592 593 /* we need a pinset group */ 594 if (strlen(req->pinset_group) == 0) 595 return false; 596 597 /* determine which group is requested */ 598 grp = NULL; 599 for (i = 0; i < exynos_n_pin_groups; i++) { 600 grp = &exynos_pin_groups[i]; 601 if (strcmp(req->pinset_group, grp->grp_name) == 0) 602 break; 603 } 604 /* found? */ 605 if (i == exynos_n_pin_groups) 606 return false; 607 KASSERT(grp); 608 609 /* fail unconnected pins */ 610 if (req->pinset_mask & ~grp->grp_pin_mask) 611 return false; 612 613 /* if none in use, they are available */ 614 if (req->pinset_mask & ~grp->grp_pin_inuse_mask) 615 return true; 616 617 /* OK, so some are in use; now see if the request is compatible */ 618 inuse = req->pinset_mask & grp->grp_pin_inuse_mask; 619 for (i = 0; inuse; i++, inuse >>= 1) { 620 /* try to be smart by skipping zero's */ 621 n = ffs(inuse) -1; 622 i += n; 623 inuse >>= n; 624 /* this pin is in use, check its usage */ 625 if (exynos_gpio_get_pin_func(&grp->grp_cfg, i) != req->pinset_func) 626 return false; 627 } 628 629 /* seems to be OK */ 630 return true; 631 } 632 633 634 void 635 exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *req) 636 { 637 struct exynos_gpio_pin_group *grp; 638 struct exynos_gpio_pin_cfg ncfg; 639 int i, n, todo; 640 641 KASSERT(req); 642 KASSERT(exynos_gpio_pinset_available(req)); 643 644 /* determine which group is requested */ 645 grp = NULL; 646 for (i = 0; i < exynos_n_pin_groups; i++) { 647 grp = &exynos_pin_groups[i]; 648 if (strcmp(req->pinset_group, grp->grp_name) == 0) 649 break; 650 } 651 KASSERT(grp); 652 653 /* check if all the pins have the right function */ 654 if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0) 655 return; 656 657 /* copy current config for update routine */ 658 ncfg = grp->grp_cfg; 659 660 /* update the function of each pin that is not in use */ 661 todo = req->pinset_mask & grp->grp_pin_inuse_mask; 662 for (i = 0; todo; i++, todo >>= 1) { 663 /* try to be smart by skipping zero's */ 664 n = ffs(todo) -1; 665 i += n; 666 todo >>= n; 667 /* change the function of this pin */ 668 exynos_gpio_set_pin_func(&ncfg, i, req->pinset_func); 669 } 670 671 /* update config registers */ 672 exynos_gpio_update_cfg_regs(grp, &ncfg); 673 674 /* mark pins in use */ 675 grp->grp_pin_inuse_mask |= req->pinset_mask; 676 } 677 678 679 /* get a pindata structure from a pinset structure */ 680 void 681 exynos_gpio_pinset_to_pindata(const struct exynos_gpio_pinset *req, int pinnr, 682 struct exynos_gpio_pindata *pd) 683 { 684 struct exynos_gpio_pin_group *grp; 685 int i; 686 687 KASSERT(req); 688 KASSERT(pd); 689 KASSERT(req->pinset_mask & __BIT(pinnr)); 690 691 /* determine which group is requested */ 692 grp = NULL; 693 for (i = 0; i < exynos_n_pin_groups; i++) { 694 grp = &exynos_pin_groups[i]; 695 if (strcmp(req->pinset_group, grp->grp_name) == 0) 696 break; 697 } 698 KASSERT(grp); 699 700 pd->pd_gc = &grp->grp_gc_tag; 701 pd->pd_pin = pinnr; 702 } 703 704 705 /* XXXRPZ This release doesn't grock multiple usages! */ 706 void 707 exynos_gpio_pinset_release(const struct exynos_gpio_pinset *req) 708 { 709 struct exynos_gpio_pin_group *grp; 710 int i; 711 712 KASSERT(!exynos_gpio_pinset_available(req)); 713 714 /* determine which group is requested */ 715 grp = NULL; 716 for (i = 0; i < exynos_n_pin_groups; i++) { 717 grp = &exynos_pin_groups[i]; 718 if (strcmp(req->pinset_group, grp->grp_name) == 0) 719 break; 720 } 721 KASSERT(grp); 722 723 /* bluntly mark as not being in use */ 724 grp->grp_pin_inuse_mask &= ~req->pinset_mask; 725 } 726 727 728 /* 729 * name convention : 730 * pin = <func><groupname><pinnr>[<pud>] 731 * func = '<' | '>' 732 * pinnr = '['['0'-'7']']' 733 * pud = 'F' | 'U' | 'D' 734 * 735 * example "<GPC1[0]", ">GPB[0]" 736 */ 737 738 bool 739 exynos_gpio_pin_reserve(const char *name, struct exynos_gpio_pindata *pd) 740 { 741 struct exynos_gpio_softc * const sc = &exynos_gpio_sc; 742 struct exynos_gpio_pin_group *grp; 743 struct exynos_gpio_pin_cfg ncfg; 744 prop_dictionary_t dict = device_properties(sc->sc_dev); 745 const char *pin_data; 746 char grp_name[15], *pos; 747 int func, pud, pinnr; 748 int pi, i; 749 750 if (exynos_n_pin_groups == 0) 751 return false; 752 753 /* do we have a named pin description? */ 754 if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data)) 755 return false; 756 757 KASSERT(strlen(pin_data) < 10); 758 if (!(pin_data[0] == '>' || pin_data[0] == '<')) { 759 printf("%s: malformed pin data in '%s', missing direction\n", 760 __func__, pin_data); 761 return false; 762 } 763 764 func = (pin_data[0] == '<') ? 765 EXYNOS_GPIO_FUNC_INPUT : EXYNOS_GPIO_FUNC_OUTPUT; 766 767 /* find groupname */ 768 pi = 1; pos = grp_name; 769 while (pin_data[pi] && pin_data[pi] != '[') { 770 *pos++ = pin_data[pi++]; 771 } 772 if (pin_data[pi] != '[') { 773 printf("%s: malformed pin data in '%s', missing '['\n", 774 __func__, pin_data); 775 return false; 776 } 777 *pos++ = (char) 0; 778 779 /* skip '[' */ 780 pi++; 781 if (!(pin_data[pi] >= '0' && pin_data[pi] <= '7')) { 782 printf("%s: malformed pin data in '%s', bad pin number\n", 783 __func__, pin_data); 784 return false; 785 } 786 pinnr = pin_data[pi] - '0'; 787 788 /* skip digit */ 789 pi++; 790 if ((pin_data[pi] != ']')) { 791 printf("%s: malformed pin data in '%s', missing end ']'\n", 792 __func__, pin_data); 793 return false; 794 } 795 796 /* skip ']' */ 797 pi++; 798 pud = EXYNOS_GPIO_PIN_FLOAT; 799 switch (tolower(pin_data[pi])) { 800 case (char) 0: 801 break; 802 case 'f': 803 pud = EXYNOS_GPIO_PIN_FLOAT; 804 break; 805 case 'u': 806 pud = EXYNOS_GPIO_PIN_PULL_UP; 807 break; 808 case 'd': 809 pud = EXYNOS_GPIO_PIN_PULL_DOWN; 810 break; 811 default: 812 printf("%s: malformed pin data in '%s', expecting " 813 "optional pull up/down or float argument\n", 814 __func__, pin_data); 815 return false; 816 } 817 818 /* determine which group is requested */ 819 grp = NULL; 820 for (i = 0; i < exynos_n_pin_groups; i++) { 821 grp = &exynos_pin_groups[i]; 822 if (strcmp(grp_name, grp->grp_name) == 0) 823 break; 824 } 825 826 /* found? */ 827 if (i >= exynos_n_pin_groups) { 828 printf("%s: malformed pin data in '%s', " 829 "no such pin group name\n", 830 __func__, grp_name); 831 return false; 832 } 833 KASSERT(grp); 834 835 /* in range? */ 836 if (pinnr >= grp->grp_bits) 837 return false; 838 839 /* marked as connected? */ 840 if ((grp->grp_pin_mask & __BIT(pinnr)) == 0) 841 return false; 842 843 /* it better not be used!! this is not taken lightly */ 844 KASSERT((grp->grp_pin_inuse_mask & __BIT(pinnr)) == 0); 845 846 /* update our pin configuration */ 847 ncfg = grp->grp_cfg; 848 exynos_gpio_set_pin_func(&ncfg, pinnr, func); 849 exynos_gpio_set_pin_pull(&ncfg, pinnr, pud); 850 exynos_gpio_update_cfg_regs(grp, &ncfg); 851 852 grp->grp_pin_inuse_mask |= __BIT(pinnr); 853 grp->grp_pin_mask &= ~__BIT(pinnr); 854 855 pd->pd_gc = &grp->grp_gc_tag; 856 pd->pd_pin = pinnr; 857 858 return true; 859 } 860 861 862 /* bootstrapping */ 863 void 864 exynos_gpio_bootstrap(void) 865 { 866 bus_space_tag_t bst = &exynos_bs_tag; 867 struct exynos_gpio_pin_group *grp; 868 struct gpio_chipset_tag *gc_tag; 869 int i; 870 871 /* determine what we're running on */ 872 #ifdef EXYNOS4 873 if (IS_EXYNOS4_P()) { 874 exynos_pin_groups = exynos4_pin_groups; 875 exynos_n_pin_groups = __arraycount(exynos4_pin_groups); 876 } 877 #endif 878 #ifdef EXYNOS5 879 if (IS_EXYNOS5_P()) { 880 exynos_pin_groups = exynos5_pin_groups; 881 exynos_n_pin_groups = __arraycount(exynos5_pin_groups); 882 } 883 #endif 884 885 if (exynos_n_pin_groups == 0) 886 return; 887 888 /* init groups */ 889 for (i = 0; i < exynos_n_pin_groups; i++) { 890 grp = &exynos_pin_groups[i]; 891 gc_tag = &grp->grp_gc_tag; 892 893 bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 894 grp->grp_core_offset, EXYNOS_GPIO_GRP_SIZE, 895 &grp->grp_bsh); 896 KASSERT(&grp->grp_bsh); 897 898 grp->grp_pin_mask = __BIT(grp->grp_bits) - 1; 899 grp->grp_pin_inuse_mask = 0; 900 901 gc_tag->gp_cookie = grp; 902 gc_tag->gp_pin_read = exynos_gpio_pin_read; 903 gc_tag->gp_pin_write = exynos_gpio_pin_write; 904 gc_tag->gp_pin_ctl = exynos_gpio_pin_ctl; 905 906 /* read in our initial settings */ 907 grp->grp_cfg.cfg = bus_space_read_4(bst, grp->grp_bsh, 908 EXYNOS_GPIO_CON); 909 grp->grp_cfg.pud = bus_space_read_4(bst, grp->grp_bsh, 910 EXYNOS_GPIO_PUD); 911 grp->grp_cfg.drv = bus_space_read_4(bst, grp->grp_bsh, 912 EXYNOS_GPIO_DRV); 913 grp->grp_cfg.conpwd = bus_space_read_4(bst, grp->grp_bsh, 914 EXYNOS_GPIO_CONPWD); 915 grp->grp_cfg.pudpwd = bus_space_read_4(bst, grp->grp_bsh, 916 EXYNOS_GPIO_PUDPWD); 917 918 /* 919 * Normally we would count the busy pins. 920 * 921 * We can't check inuse here since uboot has used pins for its 922 * own use and left them configured forbidding us to use pins 923 * for our own sake. 924 */ 925 #if 0 926 for (int j = 0, int mask = 1; 927 (mask & grp->grp_pin_mask) != 0; 928 j++, mask <<= 1) { 929 int func = exynos_gpio_get_pin_func(&grp->grp_cfg, j); 930 if (func > EXYNOS_GPIO_FUNC_INPUT) { 931 printf("%s: %s[%d] func %d\n", __func__, 932 grp->grp_name, j, func); 933 } 934 } 935 #endif 936 } 937 #if 0 938 printf("\n"); 939 printf("default NC pin list generated: \n"); 940 /* enable this for default NC pins list generation */ 941 for (i = 0; i < exynos_n_pin_groups; i++) { 942 grp = &exynos_pin_groups[i]; 943 printf("prop_dictionary_set_uint32(dict, \"nc-%s\", " 944 "0x%02x - 0b00000000);\n", 945 grp->grp_name, grp->grp_pin_mask); 946 } 947 #endif 948 } 949 950
Indexes created Tue Sep 30 11:09:46 GMT 2025