exynos_i2c.c revision 1.11.10.1
1 /* $NetBSD: exynos_i2c.c,v 1.11.10.1 2017/07/18 19:13:08 snj Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #include "opt_exynos.h" 31 #include "opt_arm_debug.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.11.10.1 2017/07/18 19:13:08 snj Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/kmem.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_var.h> 46 #include <arm/samsung/exynos_intr.h> 47 48 #include <sys/gpio.h> 49 #include <dev/gpio/gpiovar.h> 50 51 #include <dev/i2c/i2cvar.h> 52 #include <dev/i2c/i2c_bitbang.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 struct exynos_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 63 struct fdtbus_pinctrl_pin *sc_sda; 64 struct fdtbus_pinctrl_pin *sc_scl; 65 bool sc_sda_is_output; 66 67 struct i2c_controller sc_ic; 68 kmutex_t sc_lock; 69 kcondvar_t sc_cv; 70 device_t sc_i2cdev; 71 }; 72 73 static int exynos_i2c_intr(void *); 74 75 static int exynos_i2c_acquire_bus(void *, int); 76 static void exynos_i2c_release_bus(void *, int); 77 78 static int exynos_i2c_send_start(void *, int); 79 static int exynos_i2c_send_stop(void *, int); 80 static int exynos_i2c_initiate_xfer(void *, i2c_addr_t, int); 81 static int exynos_i2c_read_byte(void *, uint8_t *, int); 82 static int exynos_i2c_write_byte(void *, uint8_t , int); 83 84 static int exynos_i2c_wait(struct exynos_i2c_softc *, int); 85 86 87 static int exynos_i2c_match(device_t, cfdata_t, void *); 88 static void exynos_i2c_attach(device_t, device_t, void *); 89 90 static i2c_tag_t exynos_i2c_get_tag(device_t); 91 92 struct fdtbus_i2c_controller_func exynos_i2c_funcs = { 93 .get_tag = exynos_i2c_get_tag 94 }; 95 96 CFATTACH_DECL_NEW(exynos_i2c, sizeof(struct exynos_i2c_softc), 97 exynos_i2c_match, exynos_i2c_attach, NULL, NULL); 98 99 #define I2C_WRITE(sc, reg, val) \ 100 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 101 #define I2C_READ(sc, reg) \ 102 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 103 104 #define IICCON 0x00 105 #define IICSTAT 0x04 106 #define IICADD 0x08 107 #define IICDS 0x0C 108 109 #define ACKENABLE (1<<7) 110 #define TXPRESCALE (1<<6) 111 #define INTENABLE (1<<5) 112 #define IRQPEND (1<<4) 113 #define PRESCALE (0x0f) 114 115 #define MODESELECT (3<<6) 116 #define BUSYSTART (1<<5) 117 #define BUSENABLE (1<<4) 118 #define ARBITRATION (1<<3) 119 #define SLAVESTATUS (1<<2) 120 #define ZEROSTATUS (1<<1) 121 #define LASTBIT (1<<0) 122 123 #define READBIT (1<<7) 124 125 static int 126 exynos_i2c_match(device_t self, cfdata_t cf, void *aux) 127 { 128 const char * const compatible[] = { "samsung,s3c2440-i2c", NULL }; 129 struct fdt_attach_args * const faa = aux; 130 131 return of_match_compatible(faa->faa_phandle, compatible); 132 } 133 134 static void 135 exynos_i2c_attach(device_t parent, device_t self, void *aux) 136 { 137 struct exynos_i2c_softc * const sc = device_private(self); 138 struct fdt_attach_args * const faa = aux; 139 const int phandle = faa->faa_phandle; 140 struct i2cbus_attach_args iba; 141 prop_dictionary_t devs; 142 uint32_t address_cells; 143 char intrstr[128]; 144 bus_addr_t addr; 145 bus_size_t size; 146 int error; 147 148 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 149 aprint_error(": couldn't get registers\n"); 150 return; 151 } 152 153 sc->sc_dev = self; 154 sc->sc_bst = faa->faa_bst; 155 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 156 if (error) { 157 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, 158 error); 159 return; 160 } 161 162 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 163 cv_init(&sc->sc_cv, device_xname(self)); 164 aprint_normal(" @ 0x%08x\n", (uint)addr); 165 166 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 167 aprint_error_dev(self, "failed to decode interrupt\n"); 168 return; 169 } 170 171 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 172 FDT_INTR_MPSAFE, exynos_i2c_intr, sc); 173 if (sc->sc_ih == NULL) { 174 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 175 intrstr); 176 return; 177 } 178 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 179 180 sc->sc_ic.ic_cookie = sc; 181 sc->sc_ic.ic_acquire_bus = exynos_i2c_acquire_bus; 182 sc->sc_ic.ic_release_bus = exynos_i2c_release_bus; 183 sc->sc_ic.ic_send_start = exynos_i2c_send_start; 184 sc->sc_ic.ic_send_stop = exynos_i2c_send_stop; 185 sc->sc_ic.ic_initiate_xfer = exynos_i2c_initiate_xfer; 186 sc->sc_ic.ic_read_byte = exynos_i2c_read_byte; 187 sc->sc_ic.ic_write_byte = exynos_i2c_write_byte; 188 189 fdtbus_register_i2c_controller(self, phandle, &exynos_i2c_funcs); 190 191 devs = prop_dictionary_create(); 192 if (of_getprop_uint32(phandle, "#address-cells", &address_cells)) 193 address_cells = 1; 194 of_enter_i2c_devs(devs, phandle, address_cells * 4, 0); 195 196 memset(&iba, 0, sizeof(iba)); 197 iba.iba_tag = &sc->sc_ic; 198 iba.iba_child_devices = prop_dictionary_get(devs, "i2c-child-devices"); 199 if (iba.iba_child_devices != NULL) 200 prop_object_retain(iba.iba_child_devices); 201 else 202 iba.iba_child_devices = prop_array_create(); 203 prop_object_release(devs); 204 205 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 206 } 207 208 static i2c_tag_t 209 exynos_i2c_get_tag(device_t dev) 210 { 211 struct exynos_i2c_softc * const sc = device_private(dev); 212 213 return &sc->sc_ic; 214 } 215 216 static int 217 exynos_i2c_intr(void *priv) 218 { 219 struct exynos_i2c_softc * const sc = priv; 220 221 uint8_t istatus = I2C_READ(sc, IICCON); 222 if (!(istatus & IRQPEND)) 223 return 0; 224 istatus &= ~IRQPEND; 225 I2C_WRITE(sc, IICCON, istatus); 226 227 mutex_enter(&sc->sc_lock); 228 cv_broadcast(&sc->sc_cv); 229 mutex_exit(&sc->sc_lock); 230 231 return 1; 232 } 233 234 static int 235 exynos_i2c_acquire_bus(void *cookie, int flags) 236 { 237 struct exynos_i2c_softc *i2c_sc = cookie; 238 239 mutex_enter(&i2c_sc->sc_lock); 240 return 0; 241 } 242 243 static void 244 exynos_i2c_release_bus(void *cookie, int flags) 245 { 246 struct exynos_i2c_softc *i2c_sc = cookie; 247 248 mutex_exit(&i2c_sc->sc_lock); 249 } 250 251 static int 252 exynos_i2c_wait(struct exynos_i2c_softc *sc, int flags) 253 { 254 int error, retry; 255 uint8_t stat = 0; 256 257 retry = (flags & I2C_F_POLL) ? 100000 : 100; 258 259 while (--retry > 0) { 260 if ((flags & I2C_F_POLL) == 0) { 261 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 262 max(mstohz(10), 1)); 263 if (error) { 264 return error; 265 } 266 } 267 stat = I2C_READ(sc, IICSTAT); 268 if (!(stat & BUSYSTART)) { 269 break; 270 } 271 if (flags & I2C_F_POLL) { 272 delay(10); 273 } 274 } 275 if (retry == 0) { 276 stat = I2C_READ(sc, IICSTAT); 277 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 278 return ETIMEDOUT; 279 } 280 281 return 0; 282 } 283 284 285 static int 286 exynos_i2c_send_start(void *cookie, int flags) 287 { 288 struct exynos_i2c_softc *sc = cookie; 289 I2C_WRITE(sc, IICSTAT, 0xF0); 290 return 0; 291 } 292 293 static int 294 exynos_i2c_send_stop(void *cookie, int flags) 295 { 296 struct exynos_i2c_softc *sc = cookie; 297 I2C_WRITE(sc, IICSTAT, 0xD0); 298 return 0; 299 } 300 301 static int 302 exynos_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 303 { 304 struct exynos_i2c_softc *sc = cookie; 305 uint8_t byte = addr & 0x7f; 306 if (flags & I2C_F_READ) 307 byte |= READBIT; 308 else 309 byte &= ~READBIT; 310 I2C_WRITE(sc, IICADD, addr); 311 exynos_i2c_send_start(cookie, flags); 312 exynos_i2c_write_byte(cookie, byte, flags); 313 return exynos_i2c_wait(cookie, flags); 314 } 315 316 static int 317 exynos_i2c_read_byte(void *cookie, uint8_t *bytep, int flags) 318 { 319 struct exynos_i2c_softc *sc = cookie; 320 int error = exynos_i2c_wait(sc, flags); 321 if (error) 322 return error; 323 *bytep = I2C_READ(sc, IICDS) & 0xff; 324 if (flags & I2C_F_STOP) 325 exynos_i2c_send_stop(cookie, flags); 326 return 0; 327 } 328 329 static int 330 exynos_i2c_write_byte(void *cookie, uint8_t byte, int flags) 331 { 332 struct exynos_i2c_softc *sc = cookie; 333 int error = exynos_i2c_wait(sc, flags); 334 if (error) 335 return error; 336 I2C_WRITE(sc, IICDS, byte); 337 return 0; 338 } 339
Indexes created Mon Oct 20 20:10:13 GMT 2025