exynos_i2c.c revision 1.17
1 /* $NetBSD: exynos_i2c.c,v 1.17 2019/10/18 06:13:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #include "opt_exynos.h" 31 #include "opt_arm_debug.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.17 2019/10/18 06:13:38 skrll Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/kmem.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_var.h> 46 #include <arm/samsung/exynos_intr.h> 47 48 #include <sys/gpio.h> 49 #include <dev/gpio/gpiovar.h> 50 51 #include <dev/i2c/i2cvar.h> 52 #include <dev/i2c/i2c_bitbang.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 struct exynos_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 63 struct fdtbus_pinctrl_pin *sc_sda; 64 struct fdtbus_pinctrl_pin *sc_scl; 65 bool sc_sda_is_output; 66 67 struct i2c_controller sc_ic; 68 kmutex_t sc_lock; 69 kcondvar_t sc_cv; 70 }; 71 72 static int exynos_i2c_intr(void *); 73 74 static int exynos_i2c_acquire_bus(void *, int); 75 static void exynos_i2c_release_bus(void *, int); 76 77 static int exynos_i2c_send_start(void *, int); 78 static int exynos_i2c_send_stop(void *, int); 79 static int exynos_i2c_initiate_xfer(void *, i2c_addr_t, int); 80 static int exynos_i2c_read_byte(void *, uint8_t *, int); 81 static int exynos_i2c_write_byte(void *, uint8_t , int); 82 83 static int exynos_i2c_wait(struct exynos_i2c_softc *, int); 84 85 86 static int exynos_i2c_match(device_t, cfdata_t, void *); 87 static void exynos_i2c_attach(device_t, device_t, void *); 88 89 static i2c_tag_t exynos_i2c_get_tag(device_t); 90 91 struct fdtbus_i2c_controller_func exynos_i2c_funcs = { 92 .get_tag = exynos_i2c_get_tag 93 }; 94 95 CFATTACH_DECL_NEW(exynos_i2c, sizeof(struct exynos_i2c_softc), 96 exynos_i2c_match, exynos_i2c_attach, NULL, NULL); 97 98 #define I2C_WRITE(sc, reg, val) \ 99 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 100 #define I2C_READ(sc, reg) \ 101 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 102 103 #define IICCON 0x00 104 #define IICSTAT 0x04 105 #define IICADD 0x08 106 #define IICDS 0x0C 107 108 #define ACKENABLE (1<<7) 109 #define TXPRESCALE (1<<6) 110 #define INTENABLE (1<<5) 111 #define IRQPEND (1<<4) 112 #define PRESCALE (0x0f) 113 114 #define MODESELECT (3<<6) 115 #define BUSYSTART (1<<5) 116 #define BUSENABLE (1<<4) 117 #define ARBITRATION (1<<3) 118 #define SLAVESTATUS (1<<2) 119 #define ZEROSTATUS (1<<1) 120 #define LASTBIT (1<<0) 121 122 #define READBIT (1<<7) 123 124 static int 125 exynos_i2c_match(device_t self, cfdata_t cf, void *aux) 126 { 127 const char * const compatible[] = { "samsung,s3c2440-i2c", NULL }; 128 struct fdt_attach_args * const faa = aux; 129 130 return of_match_compatible(faa->faa_phandle, compatible); 131 } 132 133 static void 134 exynos_i2c_attach(device_t parent, device_t self, void *aux) 135 { 136 struct exynos_i2c_softc * const sc = device_private(self); 137 struct fdt_attach_args * const faa = aux; 138 const int phandle = faa->faa_phandle; 139 char intrstr[128]; 140 bus_addr_t addr; 141 bus_size_t size; 142 int error; 143 144 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 145 aprint_error(": couldn't get registers\n"); 146 return; 147 } 148 149 sc->sc_dev = self; 150 sc->sc_bst = faa->faa_bst; 151 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 152 if (error) { 153 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, 154 error); 155 return; 156 } 157 158 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 159 cv_init(&sc->sc_cv, device_xname(self)); 160 aprint_normal(" @ 0x%08x\n", (uint)addr); 161 162 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 163 aprint_error_dev(self, "failed to decode interrupt\n"); 164 return; 165 } 166 167 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 168 FDT_INTR_MPSAFE, exynos_i2c_intr, sc); 169 if (sc->sc_ih == NULL) { 170 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 171 intrstr); 172 return; 173 } 174 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 175 176 sc->sc_ic.ic_cookie = sc; 177 sc->sc_ic.ic_acquire_bus = exynos_i2c_acquire_bus; 178 sc->sc_ic.ic_release_bus = exynos_i2c_release_bus; 179 sc->sc_ic.ic_send_start = exynos_i2c_send_start; 180 sc->sc_ic.ic_send_stop = exynos_i2c_send_stop; 181 sc->sc_ic.ic_initiate_xfer = exynos_i2c_initiate_xfer; 182 sc->sc_ic.ic_read_byte = exynos_i2c_read_byte; 183 sc->sc_ic.ic_write_byte = exynos_i2c_write_byte; 184 185 fdtbus_register_i2c_controller(self, phandle, &exynos_i2c_funcs); 186 187 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 188 } 189 190 static i2c_tag_t 191 exynos_i2c_get_tag(device_t dev) 192 { 193 struct exynos_i2c_softc * const sc = device_private(dev); 194 195 return &sc->sc_ic; 196 } 197 198 static int 199 exynos_i2c_intr(void *priv) 200 { 201 struct exynos_i2c_softc * const sc = priv; 202 203 uint8_t istatus = I2C_READ(sc, IICCON); 204 if (!(istatus & IRQPEND)) 205 return 0; 206 istatus &= ~IRQPEND; 207 I2C_WRITE(sc, IICCON, istatus); 208 209 mutex_enter(&sc->sc_lock); 210 cv_broadcast(&sc->sc_cv); 211 mutex_exit(&sc->sc_lock); 212 213 return 1; 214 } 215 216 static int 217 exynos_i2c_acquire_bus(void *cookie, int flags) 218 { 219 struct exynos_i2c_softc *i2c_sc = cookie; 220 221 mutex_enter(&i2c_sc->sc_lock); 222 return 0; 223 } 224 225 static void 226 exynos_i2c_release_bus(void *cookie, int flags) 227 { 228 struct exynos_i2c_softc *i2c_sc = cookie; 229 230 mutex_exit(&i2c_sc->sc_lock); 231 } 232 233 static int 234 exynos_i2c_wait(struct exynos_i2c_softc *sc, int flags) 235 { 236 int error, retry; 237 uint8_t stat = 0; 238 239 retry = (flags & I2C_F_POLL) ? 100000 : 100; 240 241 while (--retry > 0) { 242 if ((flags & I2C_F_POLL) == 0) { 243 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 244 uimax(mstohz(10), 1)); 245 if (error) { 246 return error; 247 } 248 } 249 stat = I2C_READ(sc, IICSTAT); 250 if (!(stat & BUSYSTART)) { 251 break; 252 } 253 if (flags & I2C_F_POLL) { 254 delay(10); 255 } 256 } 257 if (retry == 0) { 258 stat = I2C_READ(sc, IICSTAT); 259 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 260 return ETIMEDOUT; 261 } 262 263 return 0; 264 } 265 266 267 static int 268 exynos_i2c_send_start(void *cookie, int flags) 269 { 270 struct exynos_i2c_softc *sc = cookie; 271 I2C_WRITE(sc, IICSTAT, 0xF0); 272 return 0; 273 } 274 275 static int 276 exynos_i2c_send_stop(void *cookie, int flags) 277 { 278 struct exynos_i2c_softc *sc = cookie; 279 I2C_WRITE(sc, IICSTAT, 0xD0); 280 return 0; 281 } 282 283 static int 284 exynos_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 285 { 286 struct exynos_i2c_softc *sc = cookie; 287 uint8_t byte = addr & 0x7f; 288 if (flags & I2C_F_READ) 289 byte |= READBIT; 290 else 291 byte &= ~READBIT; 292 I2C_WRITE(sc, IICADD, addr); 293 exynos_i2c_send_start(cookie, flags); 294 exynos_i2c_write_byte(cookie, byte, flags); 295 return exynos_i2c_wait(cookie, flags); 296 } 297 298 static int 299 exynos_i2c_read_byte(void *cookie, uint8_t *bytep, int flags) 300 { 301 struct exynos_i2c_softc *sc = cookie; 302 int error = exynos_i2c_wait(sc, flags); 303 if (error) 304 return error; 305 *bytep = I2C_READ(sc, IICDS) & 0xff; 306 if (flags & I2C_F_STOP) 307 exynos_i2c_send_stop(cookie, flags); 308 return 0; 309 } 310 311 static int 312 exynos_i2c_write_byte(void *cookie, uint8_t byte, int flags) 313 { 314 struct exynos_i2c_softc *sc = cookie; 315 int error = exynos_i2c_wait(sc, flags); 316 if (error) 317 return error; 318 I2C_WRITE(sc, IICDS, byte); 319 return 0; 320 } 321
Indexes created Thu Oct 02 07:10:07 GMT 2025