exynos_i2c.c revision 1.18
1 /* $NetBSD: exynos_i2c.c,v 1.18 2019/12/22 23:50:43 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #include "opt_exynos.h" 31 #include "opt_arm_debug.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.18 2019/12/22 23:50:43 thorpej Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/kmem.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_var.h> 46 #include <arm/samsung/exynos_intr.h> 47 48 #include <sys/gpio.h> 49 #include <dev/gpio/gpiovar.h> 50 51 #include <dev/i2c/i2cvar.h> 52 #include <dev/i2c/i2c_bitbang.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 struct exynos_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 63 struct fdtbus_pinctrl_pin *sc_sda; 64 struct fdtbus_pinctrl_pin *sc_scl; 65 bool sc_sda_is_output; 66 67 struct i2c_controller sc_ic; 68 kmutex_t sc_intr_lock; 69 kcondvar_t sc_intr_wait; 70 }; 71 72 static int exynos_i2c_intr(void *); 73 74 static int exynos_i2c_send_start(void *, int); 75 static int exynos_i2c_send_stop(void *, int); 76 static int exynos_i2c_initiate_xfer(void *, i2c_addr_t, int); 77 static int exynos_i2c_read_byte(void *, uint8_t *, int); 78 static int exynos_i2c_write_byte(void *, uint8_t , int); 79 80 static int exynos_i2c_wait(struct exynos_i2c_softc *, int); 81 82 83 static int exynos_i2c_match(device_t, cfdata_t, void *); 84 static void exynos_i2c_attach(device_t, device_t, void *); 85 86 static i2c_tag_t exynos_i2c_get_tag(device_t); 87 88 struct fdtbus_i2c_controller_func exynos_i2c_funcs = { 89 .get_tag = exynos_i2c_get_tag 90 }; 91 92 CFATTACH_DECL_NEW(exynos_i2c, sizeof(struct exynos_i2c_softc), 93 exynos_i2c_match, exynos_i2c_attach, NULL, NULL); 94 95 #define I2C_WRITE(sc, reg, val) \ 96 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 97 #define I2C_READ(sc, reg) \ 98 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 99 100 #define IICCON 0x00 101 #define IICSTAT 0x04 102 #define IICADD 0x08 103 #define IICDS 0x0C 104 105 #define ACKENABLE (1<<7) 106 #define TXPRESCALE (1<<6) 107 #define INTENABLE (1<<5) 108 #define IRQPEND (1<<4) 109 #define PRESCALE (0x0f) 110 111 #define MODESELECT (3<<6) 112 #define BUSYSTART (1<<5) 113 #define BUSENABLE (1<<4) 114 #define ARBITRATION (1<<3) 115 #define SLAVESTATUS (1<<2) 116 #define ZEROSTATUS (1<<1) 117 #define LASTBIT (1<<0) 118 119 #define READBIT (1<<7) 120 121 static int 122 exynos_i2c_match(device_t self, cfdata_t cf, void *aux) 123 { 124 const char * const compatible[] = { "samsung,s3c2440-i2c", NULL }; 125 struct fdt_attach_args * const faa = aux; 126 127 return of_match_compatible(faa->faa_phandle, compatible); 128 } 129 130 static void 131 exynos_i2c_attach(device_t parent, device_t self, void *aux) 132 { 133 struct exynos_i2c_softc * const sc = device_private(self); 134 struct fdt_attach_args * const faa = aux; 135 const int phandle = faa->faa_phandle; 136 char intrstr[128]; 137 bus_addr_t addr; 138 bus_size_t size; 139 int error; 140 141 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 142 aprint_error(": couldn't get registers\n"); 143 return; 144 } 145 146 sc->sc_dev = self; 147 sc->sc_bst = faa->faa_bst; 148 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 149 if (error) { 150 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, 151 error); 152 return; 153 } 154 155 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 156 cv_init(&sc->sc_intr_wait, device_xname(self)); 157 aprint_normal(" @ 0x%08x\n", (uint)addr); 158 159 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 160 aprint_error_dev(self, "failed to decode interrupt\n"); 161 return; 162 } 163 164 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 165 FDT_INTR_MPSAFE, exynos_i2c_intr, sc); 166 if (sc->sc_ih == NULL) { 167 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 168 intrstr); 169 return; 170 } 171 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 172 173 iic_tag_init(&sc->sc_ic); 174 sc->sc_ic.ic_cookie = sc; 175 sc->sc_ic.ic_send_start = exynos_i2c_send_start; 176 sc->sc_ic.ic_send_stop = exynos_i2c_send_stop; 177 sc->sc_ic.ic_initiate_xfer = exynos_i2c_initiate_xfer; 178 sc->sc_ic.ic_read_byte = exynos_i2c_read_byte; 179 sc->sc_ic.ic_write_byte = exynos_i2c_write_byte; 180 181 fdtbus_register_i2c_controller(self, phandle, &exynos_i2c_funcs); 182 183 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 184 } 185 186 static i2c_tag_t 187 exynos_i2c_get_tag(device_t dev) 188 { 189 struct exynos_i2c_softc * const sc = device_private(dev); 190 191 return &sc->sc_ic; 192 } 193 194 static int 195 exynos_i2c_intr(void *priv) 196 { 197 struct exynos_i2c_softc * const sc = priv; 198 199 uint8_t istatus = I2C_READ(sc, IICCON); 200 if (!(istatus & IRQPEND)) 201 return 0; 202 istatus &= ~IRQPEND; 203 I2C_WRITE(sc, IICCON, istatus); 204 205 mutex_enter(&sc->sc_intr_lock); 206 cv_broadcast(&sc->sc_intr_wait); 207 mutex_exit(&sc->sc_intr_lock); 208 209 return 1; 210 } 211 212 static int 213 exynos_i2c_wait(struct exynos_i2c_softc *sc, int flags) 214 { 215 int error, retry; 216 uint8_t stat = 0; 217 218 retry = (flags & I2C_F_POLL) ? 100000 : 100; 219 220 while (--retry > 0) { 221 if ((flags & I2C_F_POLL) == 0) { 222 error = cv_timedwait_sig(&sc->sc_intr_wait, 223 &sc->sc_intr_lock, 224 uimax(mstohz(10), 1)); 225 if (error) { 226 return error; 227 } 228 } 229 stat = I2C_READ(sc, IICSTAT); 230 if (!(stat & BUSYSTART)) { 231 break; 232 } 233 if (flags & I2C_F_POLL) { 234 delay(10); 235 } 236 } 237 if (retry == 0) { 238 stat = I2C_READ(sc, IICSTAT); 239 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 240 return ETIMEDOUT; 241 } 242 243 return 0; 244 } 245 246 247 static int 248 exynos_i2c_send_start_locked(struct exynos_i2c_softc *sc, int flags) 249 { 250 I2C_WRITE(sc, IICSTAT, 0xF0); 251 return 0; 252 } 253 254 static int 255 exynos_i2c_send_stop_locked(struct exynos_i2c_softc *sc, int flags) 256 { 257 I2C_WRITE(sc, IICSTAT, 0xD0); 258 return 0; 259 } 260 261 static int 262 exynos_i2c_write_byte_locked(struct exynos_i2c_softc *sc, uint8_t byte, 263 int flags) 264 { 265 int error = exynos_i2c_wait(sc, flags); 266 if (error) { 267 return error; 268 } 269 I2C_WRITE(sc, IICDS, byte); 270 return 0; 271 } 272 273 static int 274 exynos_i2c_send_start(void *cookie, int flags) 275 { 276 struct exynos_i2c_softc *sc = cookie; 277 278 mutex_enter(&sc->sc_intr_lock); 279 int error = exynos_i2c_send_start_locked(sc, flags); 280 mutex_exit(&sc->sc_intr_lock); 281 return error; 282 } 283 284 static int 285 exynos_i2c_send_stop(void *cookie, int flags) 286 { 287 struct exynos_i2c_softc *sc = cookie; 288 289 mutex_enter(&sc->sc_intr_lock); 290 int error = exynos_i2c_send_stop_locked(sc, flags); 291 mutex_exit(&sc->sc_intr_lock); 292 return error; 293 } 294 295 static int 296 exynos_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 297 { 298 struct exynos_i2c_softc *sc = cookie; 299 uint8_t byte = addr & 0x7f; 300 int error; 301 302 if (flags & I2C_F_READ) 303 byte |= READBIT; 304 else 305 byte &= ~READBIT; 306 307 mutex_enter(&sc->sc_intr_lock); 308 I2C_WRITE(sc, IICADD, addr); 309 exynos_i2c_send_start_locked(sc, flags); 310 exynos_i2c_write_byte_locked(sc, byte, flags); 311 error = exynos_i2c_wait(cookie, flags); 312 mutex_exit(&sc->sc_intr_lock); 313 314 return error; 315 } 316 317 static int 318 exynos_i2c_read_byte(void *cookie, uint8_t *bytep, int flags) 319 { 320 struct exynos_i2c_softc *sc = cookie; 321 322 mutex_enter(&sc->sc_intr_lock); 323 int error = exynos_i2c_wait(sc, flags); 324 if (error) { 325 mutex_exit(&sc->sc_intr_lock); 326 return error; 327 } 328 *bytep = I2C_READ(sc, IICDS) & 0xff; 329 if (flags & I2C_F_STOP) 330 exynos_i2c_send_stop_locked(sc, flags); 331 mutex_exit(&sc->sc_intr_lock); 332 return 0; 333 } 334 335 static int 336 exynos_i2c_write_byte(void *cookie, uint8_t byte, int flags) 337 { 338 struct exynos_i2c_softc *sc = cookie; 339 340 mutex_enter(&sc->sc_intr_lock); 341 int error = exynos_i2c_write_byte_locked(sc, byte, flags); 342 mutex_exit(&sc->sc_intr_lock); 343 return error; 344 } 345
Indexes created Thu Oct 02 07:10:07 GMT 2025