exynos_i2c.c revision 1.20
1 /* $NetBSD: exynos_i2c.c,v 1.20 2020/12/23 16:02:11 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #include "opt_exynos.h" 31 #include "opt_arm_debug.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.20 2020/12/23 16:02:11 thorpej Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/kmem.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_var.h> 46 #include <arm/samsung/exynos_intr.h> 47 48 #include <sys/gpio.h> 49 #include <dev/gpio/gpiovar.h> 50 51 #include <dev/i2c/i2cvar.h> 52 #include <dev/i2c/i2c_bitbang.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 struct exynos_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 63 struct fdtbus_pinctrl_pin *sc_sda; 64 struct fdtbus_pinctrl_pin *sc_scl; 65 bool sc_sda_is_output; 66 67 struct i2c_controller sc_ic; 68 kmutex_t sc_intr_lock; 69 kcondvar_t sc_intr_wait; 70 }; 71 72 static int exynos_i2c_intr(void *); 73 74 static int exynos_i2c_send_start(void *, int); 75 static int exynos_i2c_send_stop(void *, int); 76 static int exynos_i2c_initiate_xfer(void *, i2c_addr_t, int); 77 static int exynos_i2c_read_byte(void *, uint8_t *, int); 78 static int exynos_i2c_write_byte(void *, uint8_t , int); 79 80 static int exynos_i2c_wait(struct exynos_i2c_softc *, int); 81 82 83 static int exynos_i2c_match(device_t, cfdata_t, void *); 84 static void exynos_i2c_attach(device_t, device_t, void *); 85 86 CFATTACH_DECL_NEW(exynos_i2c, sizeof(struct exynos_i2c_softc), 87 exynos_i2c_match, exynos_i2c_attach, NULL, NULL); 88 89 #define I2C_WRITE(sc, reg, val) \ 90 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 91 #define I2C_READ(sc, reg) \ 92 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 93 94 #define IICCON 0x00 95 #define IICSTAT 0x04 96 #define IICADD 0x08 97 #define IICDS 0x0C 98 99 #define ACKENABLE (1<<7) 100 #define TXPRESCALE (1<<6) 101 #define INTENABLE (1<<5) 102 #define IRQPEND (1<<4) 103 #define PRESCALE (0x0f) 104 105 #define MODESELECT (3<<6) 106 #define BUSYSTART (1<<5) 107 #define BUSENABLE (1<<4) 108 #define ARBITRATION (1<<3) 109 #define SLAVESTATUS (1<<2) 110 #define ZEROSTATUS (1<<1) 111 #define LASTBIT (1<<0) 112 113 #define READBIT (1<<7) 114 115 static int 116 exynos_i2c_match(device_t self, cfdata_t cf, void *aux) 117 { 118 const char * const compatible[] = { "samsung,s3c2440-i2c", NULL }; 119 struct fdt_attach_args * const faa = aux; 120 121 return of_match_compatible(faa->faa_phandle, compatible); 122 } 123 124 static void 125 exynos_i2c_attach(device_t parent, device_t self, void *aux) 126 { 127 struct exynos_i2c_softc * const sc = device_private(self); 128 struct fdt_attach_args * const faa = aux; 129 const int phandle = faa->faa_phandle; 130 char intrstr[128]; 131 bus_addr_t addr; 132 bus_size_t size; 133 int error; 134 135 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 136 aprint_error(": couldn't get registers\n"); 137 return; 138 } 139 140 sc->sc_dev = self; 141 sc->sc_bst = faa->faa_bst; 142 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 143 if (error) { 144 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, 145 error); 146 return; 147 } 148 149 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 150 cv_init(&sc->sc_intr_wait, device_xname(self)); 151 aprint_normal(" @ 0x%08x\n", (uint)addr); 152 153 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 154 aprint_error_dev(self, "failed to decode interrupt\n"); 155 return; 156 } 157 158 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 159 FDT_INTR_MPSAFE, exynos_i2c_intr, sc); 160 if (sc->sc_ih == NULL) { 161 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 162 intrstr); 163 return; 164 } 165 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 166 167 iic_tag_init(&sc->sc_ic); 168 sc->sc_ic.ic_cookie = sc; 169 sc->sc_ic.ic_send_start = exynos_i2c_send_start; 170 sc->sc_ic.ic_send_stop = exynos_i2c_send_stop; 171 sc->sc_ic.ic_initiate_xfer = exynos_i2c_initiate_xfer; 172 sc->sc_ic.ic_read_byte = exynos_i2c_read_byte; 173 sc->sc_ic.ic_write_byte = exynos_i2c_write_byte; 174 175 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 176 177 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 178 } 179 180 static int 181 exynos_i2c_intr(void *priv) 182 { 183 struct exynos_i2c_softc * const sc = priv; 184 185 uint8_t istatus = I2C_READ(sc, IICCON); 186 if (!(istatus & IRQPEND)) 187 return 0; 188 istatus &= ~IRQPEND; 189 I2C_WRITE(sc, IICCON, istatus); 190 191 mutex_enter(&sc->sc_intr_lock); 192 cv_broadcast(&sc->sc_intr_wait); 193 mutex_exit(&sc->sc_intr_lock); 194 195 return 1; 196 } 197 198 static int 199 exynos_i2c_wait(struct exynos_i2c_softc *sc, int flags) 200 { 201 int error, retry; 202 uint8_t stat = 0; 203 204 retry = (flags & I2C_F_POLL) ? 100000 : 100; 205 206 while (--retry > 0) { 207 if ((flags & I2C_F_POLL) == 0) { 208 error = cv_timedwait_sig(&sc->sc_intr_wait, 209 &sc->sc_intr_lock, 210 uimax(mstohz(10), 1)); 211 if (error) { 212 return error; 213 } 214 } 215 stat = I2C_READ(sc, IICSTAT); 216 if (!(stat & BUSYSTART)) { 217 break; 218 } 219 if (flags & I2C_F_POLL) { 220 delay(10); 221 } 222 } 223 if (retry == 0) { 224 stat = I2C_READ(sc, IICSTAT); 225 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 226 return ETIMEDOUT; 227 } 228 229 return 0; 230 } 231 232 233 static int 234 exynos_i2c_send_start_locked(struct exynos_i2c_softc *sc, int flags) 235 { 236 I2C_WRITE(sc, IICSTAT, 0xF0); 237 return 0; 238 } 239 240 static int 241 exynos_i2c_send_stop_locked(struct exynos_i2c_softc *sc, int flags) 242 { 243 I2C_WRITE(sc, IICSTAT, 0xD0); 244 return 0; 245 } 246 247 static int 248 exynos_i2c_write_byte_locked(struct exynos_i2c_softc *sc, uint8_t byte, 249 int flags) 250 { 251 int error = exynos_i2c_wait(sc, flags); 252 if (error) { 253 return error; 254 } 255 I2C_WRITE(sc, IICDS, byte); 256 return 0; 257 } 258 259 static int 260 exynos_i2c_send_start(void *cookie, int flags) 261 { 262 struct exynos_i2c_softc *sc = cookie; 263 264 mutex_enter(&sc->sc_intr_lock); 265 int error = exynos_i2c_send_start_locked(sc, flags); 266 mutex_exit(&sc->sc_intr_lock); 267 return error; 268 } 269 270 static int 271 exynos_i2c_send_stop(void *cookie, int flags) 272 { 273 struct exynos_i2c_softc *sc = cookie; 274 275 mutex_enter(&sc->sc_intr_lock); 276 int error = exynos_i2c_send_stop_locked(sc, flags); 277 mutex_exit(&sc->sc_intr_lock); 278 return error; 279 } 280 281 static int 282 exynos_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 283 { 284 struct exynos_i2c_softc *sc = cookie; 285 uint8_t byte = addr & 0x7f; 286 int error; 287 288 if (flags & I2C_F_READ) 289 byte |= READBIT; 290 else 291 byte &= ~READBIT; 292 293 mutex_enter(&sc->sc_intr_lock); 294 I2C_WRITE(sc, IICADD, addr); 295 exynos_i2c_send_start_locked(sc, flags); 296 exynos_i2c_write_byte_locked(sc, byte, flags); 297 error = exynos_i2c_wait(cookie, flags); 298 mutex_exit(&sc->sc_intr_lock); 299 300 return error; 301 } 302 303 static int 304 exynos_i2c_read_byte(void *cookie, uint8_t *bytep, int flags) 305 { 306 struct exynos_i2c_softc *sc = cookie; 307 308 mutex_enter(&sc->sc_intr_lock); 309 int error = exynos_i2c_wait(sc, flags); 310 if (error) { 311 mutex_exit(&sc->sc_intr_lock); 312 return error; 313 } 314 *bytep = I2C_READ(sc, IICDS) & 0xff; 315 if (flags & I2C_F_STOP) 316 exynos_i2c_send_stop_locked(sc, flags); 317 mutex_exit(&sc->sc_intr_lock); 318 return 0; 319 } 320 321 static int 322 exynos_i2c_write_byte(void *cookie, uint8_t byte, int flags) 323 { 324 struct exynos_i2c_softc *sc = cookie; 325 326 mutex_enter(&sc->sc_intr_lock); 327 int error = exynos_i2c_write_byte_locked(sc, byte, flags); 328 mutex_exit(&sc->sc_intr_lock); 329 return error; 330 } 331
Indexes created Thu Oct 02 10:09:58 GMT 2025