exynos_i2c.c revision 1.23
1 /* $NetBSD: exynos_i2c.c,v 1.23 2025/09/16 11:41:26 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #include "opt_exynos.h" 31 #include "opt_arm_debug.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.23 2025/09/16 11:41:26 thorpej Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/kmem.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_var.h> 46 #include <arm/samsung/exynos_intr.h> 47 48 #include <sys/gpio.h> 49 #include <dev/gpio/gpiovar.h> 50 51 #include <dev/i2c/i2cvar.h> 52 #include <dev/i2c/i2c_bitbang.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 struct exynos_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 63 struct fdtbus_pinctrl_pin *sc_sda; 64 struct fdtbus_pinctrl_pin *sc_scl; 65 bool sc_sda_is_output; 66 67 struct i2c_controller sc_ic; 68 kmutex_t sc_intr_lock; 69 kcondvar_t sc_intr_wait; 70 }; 71 72 static int exynos_i2c_intr(void *); 73 74 static int exynos_i2c_send_start(void *, int); 75 static int exynos_i2c_send_stop(void *, int); 76 static int exynos_i2c_initiate_xfer(void *, i2c_addr_t, int); 77 static int exynos_i2c_read_byte(void *, uint8_t *, int); 78 static int exynos_i2c_write_byte(void *, uint8_t , int); 79 80 static int exynos_i2c_wait(struct exynos_i2c_softc *, int); 81 82 83 static int exynos_i2c_match(device_t, cfdata_t, void *); 84 static void exynos_i2c_attach(device_t, device_t, void *); 85 86 CFATTACH_DECL_NEW(exynos_i2c, sizeof(struct exynos_i2c_softc), 87 exynos_i2c_match, exynos_i2c_attach, NULL, NULL); 88 89 #define I2C_WRITE(sc, reg, val) \ 90 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 91 #define I2C_READ(sc, reg) \ 92 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 93 94 #define IICCON 0x00 95 #define IICSTAT 0x04 96 #define IICADD 0x08 97 #define IICDS 0x0C 98 99 #define ACKENABLE (1<<7) 100 #define TXPRESCALE (1<<6) 101 #define INTENABLE (1<<5) 102 #define IRQPEND (1<<4) 103 #define PRESCALE (0x0f) 104 105 #define MODESELECT (3<<6) 106 #define BUSYSTART (1<<5) 107 #define BUSENABLE (1<<4) 108 #define ARBITRATION (1<<3) 109 #define SLAVESTATUS (1<<2) 110 #define ZEROSTATUS (1<<1) 111 #define LASTBIT (1<<0) 112 113 #define READBIT (1<<7) 114 115 static const struct device_compatible_entry compat_data[] = { 116 { .compat = "samsung,s3c2440-i2c" }, 117 DEVICE_COMPAT_EOL 118 }; 119 120 static int 121 exynos_i2c_match(device_t self, cfdata_t cf, void *aux) 122 { 123 struct fdt_attach_args * const faa = aux; 124 125 return of_compatible_match(faa->faa_phandle, compat_data); 126 } 127 128 static void 129 exynos_i2c_attach(device_t parent, device_t self, void *aux) 130 { 131 struct exynos_i2c_softc * const sc = device_private(self); 132 struct fdt_attach_args * const faa = aux; 133 const int phandle = faa->faa_phandle; 134 char intrstr[128]; 135 bus_addr_t addr; 136 bus_size_t size; 137 int error; 138 139 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 140 aprint_error(": couldn't get registers\n"); 141 return; 142 } 143 144 sc->sc_dev = self; 145 sc->sc_bst = faa->faa_bst; 146 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 147 if (error) { 148 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, 149 error); 150 return; 151 } 152 153 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 154 cv_init(&sc->sc_intr_wait, device_xname(self)); 155 aprint_normal(" @ 0x%08x\n", (uint)addr); 156 157 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 158 aprint_error_dev(self, "failed to decode interrupt\n"); 159 return; 160 } 161 162 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 163 FDT_INTR_MPSAFE, exynos_i2c_intr, sc, device_xname(self)); 164 if (sc->sc_ih == NULL) { 165 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 166 intrstr); 167 return; 168 } 169 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 170 171 iic_tag_init(&sc->sc_ic); 172 sc->sc_ic.ic_cookie = sc; 173 sc->sc_ic.ic_send_start = exynos_i2c_send_start; 174 sc->sc_ic.ic_send_stop = exynos_i2c_send_stop; 175 sc->sc_ic.ic_initiate_xfer = exynos_i2c_initiate_xfer; 176 sc->sc_ic.ic_read_byte = exynos_i2c_read_byte; 177 sc->sc_ic.ic_write_byte = exynos_i2c_write_byte; 178 179 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 180 181 iicbus_attach(self, &sc->sc_ic); 182 } 183 184 static int 185 exynos_i2c_intr(void *priv) 186 { 187 struct exynos_i2c_softc * const sc = priv; 188 189 uint8_t istatus = I2C_READ(sc, IICCON); 190 if (!(istatus & IRQPEND)) 191 return 0; 192 istatus &= ~IRQPEND; 193 I2C_WRITE(sc, IICCON, istatus); 194 195 mutex_enter(&sc->sc_intr_lock); 196 cv_broadcast(&sc->sc_intr_wait); 197 mutex_exit(&sc->sc_intr_lock); 198 199 return 1; 200 } 201 202 static int 203 exynos_i2c_wait(struct exynos_i2c_softc *sc, int flags) 204 { 205 int error, retry; 206 uint8_t stat = 0; 207 208 retry = (flags & I2C_F_POLL) ? 100000 : 100; 209 210 while (--retry > 0) { 211 if ((flags & I2C_F_POLL) == 0) { 212 error = cv_timedwait_sig(&sc->sc_intr_wait, 213 &sc->sc_intr_lock, 214 uimax(mstohz(10), 1)); 215 if (error) { 216 return error; 217 } 218 } 219 stat = I2C_READ(sc, IICSTAT); 220 if (!(stat & BUSYSTART)) { 221 break; 222 } 223 if (flags & I2C_F_POLL) { 224 delay(10); 225 } 226 } 227 if (retry == 0) { 228 stat = I2C_READ(sc, IICSTAT); 229 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 230 return ETIMEDOUT; 231 } 232 233 return 0; 234 } 235 236 237 static int 238 exynos_i2c_send_start_locked(struct exynos_i2c_softc *sc, int flags) 239 { 240 I2C_WRITE(sc, IICSTAT, 0xF0); 241 return 0; 242 } 243 244 static int 245 exynos_i2c_send_stop_locked(struct exynos_i2c_softc *sc, int flags) 246 { 247 I2C_WRITE(sc, IICSTAT, 0xD0); 248 return 0; 249 } 250 251 static int 252 exynos_i2c_write_byte_locked(struct exynos_i2c_softc *sc, uint8_t byte, 253 int flags) 254 { 255 int error = exynos_i2c_wait(sc, flags); 256 if (error) { 257 return error; 258 } 259 I2C_WRITE(sc, IICDS, byte); 260 return 0; 261 } 262 263 static int 264 exynos_i2c_send_start(void *cookie, int flags) 265 { 266 struct exynos_i2c_softc *sc = cookie; 267 268 mutex_enter(&sc->sc_intr_lock); 269 int error = exynos_i2c_send_start_locked(sc, flags); 270 mutex_exit(&sc->sc_intr_lock); 271 return error; 272 } 273 274 static int 275 exynos_i2c_send_stop(void *cookie, int flags) 276 { 277 struct exynos_i2c_softc *sc = cookie; 278 279 mutex_enter(&sc->sc_intr_lock); 280 int error = exynos_i2c_send_stop_locked(sc, flags); 281 mutex_exit(&sc->sc_intr_lock); 282 return error; 283 } 284 285 static int 286 exynos_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 287 { 288 struct exynos_i2c_softc *sc = cookie; 289 uint8_t byte = addr & 0x7f; 290 int error; 291 292 if (flags & I2C_F_READ) 293 byte |= READBIT; 294 else 295 byte &= ~READBIT; 296 297 mutex_enter(&sc->sc_intr_lock); 298 I2C_WRITE(sc, IICADD, addr); 299 exynos_i2c_send_start_locked(sc, flags); 300 exynos_i2c_write_byte_locked(sc, byte, flags); 301 error = exynos_i2c_wait(cookie, flags); 302 mutex_exit(&sc->sc_intr_lock); 303 304 return error; 305 } 306 307 static int 308 exynos_i2c_read_byte(void *cookie, uint8_t *bytep, int flags) 309 { 310 struct exynos_i2c_softc *sc = cookie; 311 312 mutex_enter(&sc->sc_intr_lock); 313 int error = exynos_i2c_wait(sc, flags); 314 if (error) { 315 mutex_exit(&sc->sc_intr_lock); 316 return error; 317 } 318 *bytep = I2C_READ(sc, IICDS) & 0xff; 319 if (flags & I2C_F_STOP) 320 exynos_i2c_send_stop_locked(sc, flags); 321 mutex_exit(&sc->sc_intr_lock); 322 return 0; 323 } 324 325 static int 326 exynos_i2c_write_byte(void *cookie, uint8_t byte, int flags) 327 { 328 struct exynos_i2c_softc *sc = cookie; 329 330 mutex_enter(&sc->sc_intr_lock); 331 int error = exynos_i2c_write_byte_locked(sc, byte, flags); 332 mutex_exit(&sc->sc_intr_lock); 333 return error; 334 } 335
Indexes created Thu Oct 02 07:10:07 GMT 2025