exynos_intr.h revision 1.1 
1/*-
2 * Copyright (c) 2014 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Nick Hudson
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef _ARM_SAMSUNG_EXYNOS_INTR_H_
31#define _ARM_SAMSUNG_EXYNOS_INTR_H_
32
33#define	PIC_MAXSOURCES			GIC_MAXSOURCES(224)
34#define	PIC_MAXMAXSOURCES		(PIC_MAXSOURCES + 32)	/* XXX */
35
36/*
37 * The Exynos uses a generic interrupt controller
38 */
39#include <arm/cortex/gic_intr.h>
40
41#ifdef _KERNEL_OPT
42#include "opt_exynos.h"
43#endif
44
45/*
46 * The GIC supports
47 *   - 16 Software Generated Interrupts (SGIs)
48 *   - 16 Private Peripheral Interrupts (PPIs)
49 *   - 127 Shared Peripheral Interrupts (SPIs)
50 */
51
52#define	EXYNOS_NSPI		128
53#define	EXYNOS_COMBINERBASE	EXYNOS_SPIBASE + EXYNOS_NSPI
54
55#define	EXYNOS_BITSPERGROUP	8
56
57#define	EXYNOS_COMBINERIRQ(g, b) \
58    (EXYNOS_COMBINERBASE + ((g) * EXYNOS_BITSPERGROUP + (b)))
59
60#define	IRQ_MCT_LTIMER		IRQ_PPI(12)
61
62#ifdef EXYNOS5
63#include <arm/cortex/gtmr_intr.h>
64#endif
65
66#endif /* _ARM_SAMSUNG_EXYNOS_INTR_H_ */
67
68