exynos_intr.h revision 1.2 
1/*	$NetBSD: exynos_intr.h,v 1.2 2014/09/05 08:01:05 skrll Exp $	*/
2
3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Nick Hudson
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _ARM_SAMSUNG_EXYNOS_INTR_H_
33#define _ARM_SAMSUNG_EXYNOS_INTR_H_
34
35#define	PIC_MAXSOURCES			GIC_MAXSOURCES(224)
36#define	PIC_MAXMAXSOURCES		(PIC_MAXSOURCES + 32)	/* XXX */
37
38/*
39 * The Exynos uses a generic interrupt controller
40 */
41#include <arm/cortex/gic_intr.h>
42
43#ifdef _KERNEL_OPT
44#include "opt_exynos.h"
45#endif
46
47/*
48 * The GIC supports
49 *   - 16 Software Generated Interrupts (SGIs)
50 *   - 16 Private Peripheral Interrupts (PPIs)
51 *   - 127 Shared Peripheral Interrupts (SPIs)
52 */
53
54#define	EXYNOS_NSPI		128
55#define	EXYNOS_COMBINERBASE	EXYNOS_SPIBASE + EXYNOS_NSPI
56
57#define	EXYNOS_BITSPERGROUP	8
58
59#define	EXYNOS_COMBINERIRQ(g, b) \
60    (EXYNOS_COMBINERBASE + ((g) * EXYNOS_BITSPERGROUP + (b)))
61
62#define	IRQ_MCT_LTIMER		IRQ_PPI(12)
63
64#ifdef EXYNOS5
65#include <arm/cortex/gtmr_intr.h>
66#endif
67
68#endif /* _ARM_SAMSUNG_EXYNOS_INTR_H_ */
69
70