exynos_platform.c revision 1.6.4.2 1 1.6.4.2 snj /* $NetBSD: exynos_platform.c,v 1.6.4.2 2017/07/18 19:13:08 snj Exp $ */
2 1.6.4.2 snj
3 1.6.4.2 snj /*-
4 1.6.4.2 snj * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca>
5 1.6.4.2 snj * All rights reserved.
6 1.6.4.2 snj *
7 1.6.4.2 snj * Redistribution and use in source and binary forms, with or without
8 1.6.4.2 snj * modification, are permitted provided that the following conditions
9 1.6.4.2 snj * are met:
10 1.6.4.2 snj * 1. Redistributions of source code must retain the above copyright
11 1.6.4.2 snj * notice, this list of conditions and the following disclaimer.
12 1.6.4.2 snj * 2. Redistributions in binary form must reproduce the above copyright
13 1.6.4.2 snj * notice, this list of conditions and the following disclaimer in the
14 1.6.4.2 snj * documentation and/or other materials provided with the distribution.
15 1.6.4.2 snj *
16 1.6.4.2 snj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.6.4.2 snj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.6.4.2 snj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.6.4.2 snj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.6.4.2 snj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.6.4.2 snj * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.6.4.2 snj * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.6.4.2 snj * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.6.4.2 snj * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.6.4.2 snj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.6.4.2 snj * SUCH DAMAGE.
27 1.6.4.2 snj */
28 1.6.4.2 snj
29 1.6.4.2 snj #include "opt_exynos.h"
30 1.6.4.2 snj #include "opt_multiprocessor.h"
31 1.6.4.2 snj #include "opt_fdt_arm.h"
32 1.6.4.2 snj
33 1.6.4.2 snj #include "ukbd.h"
34 1.6.4.2 snj
35 1.6.4.2 snj #include <sys/cdefs.h>
36 1.6.4.2 snj __KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.6.4.2 2017/07/18 19:13:08 snj Exp $");
37 1.6.4.2 snj
38 1.6.4.2 snj #include <sys/param.h>
39 1.6.4.2 snj #include <sys/bus.h>
40 1.6.4.2 snj #include <sys/cpu.h>
41 1.6.4.2 snj #include <sys/device.h>
42 1.6.4.2 snj #include <sys/termios.h>
43 1.6.4.2 snj
44 1.6.4.2 snj #include <dev/fdt/fdtvar.h>
45 1.6.4.2 snj
46 1.6.4.2 snj #include <uvm/uvm_extern.h>
47 1.6.4.2 snj
48 1.6.4.2 snj #include <machine/bootconfig.h>
49 1.6.4.2 snj #include <arm/cpufunc.h>
50 1.6.4.2 snj
51 1.6.4.2 snj #include <arm/samsung/exynos_reg.h>
52 1.6.4.2 snj #include <arm/samsung/exynos_var.h>
53 1.6.4.2 snj
54 1.6.4.2 snj #include <evbarm/exynos/platform.h>
55 1.6.4.2 snj
56 1.6.4.2 snj #include <arm/cortex/gtmr_var.h>
57 1.6.4.2 snj
58 1.6.4.2 snj #include <arm/fdt/arm_fdtvar.h>
59 1.6.4.2 snj
60 1.6.4.2 snj #define EXYNOS5_SWRESET_REG 0x10040400
61 1.6.4.2 snj
62 1.6.4.2 snj #define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET)
63 1.6.4.2 snj #define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE)
64 1.6.4.2 snj #define DEVMAP_ENTRY(va, pa, sz) \
65 1.6.4.2 snj { \
66 1.6.4.2 snj .pd_va = DEVMAP_ALIGN(va), \
67 1.6.4.2 snj .pd_pa = DEVMAP_ALIGN(pa), \
68 1.6.4.2 snj .pd_size = DEVMAP_SIZE(sz), \
69 1.6.4.2 snj .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \
70 1.6.4.2 snj .pd_cache = PTE_NOCACHE \
71 1.6.4.2 snj }
72 1.6.4.2 snj #define DEVMAP_ENTRY_END { 0 }
73 1.6.4.2 snj
74 1.6.4.2 snj static const struct pmap_devmap *
75 1.6.4.2 snj exynos_platform_devmap(void)
76 1.6.4.2 snj {
77 1.6.4.2 snj static const struct pmap_devmap devmap[] = {
78 1.6.4.2 snj DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
79 1.6.4.2 snj EXYNOS_CORE_PBASE,
80 1.6.4.2 snj EXYNOS5_CORE_SIZE),
81 1.6.4.2 snj DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE,
82 1.6.4.2 snj EXYNOS5_AUDIOCORE_PBASE,
83 1.6.4.2 snj EXYNOS5_AUDIOCORE_SIZE),
84 1.6.4.2 snj DEVMAP_ENTRY_END
85 1.6.4.2 snj };
86 1.6.4.2 snj
87 1.6.4.2 snj return devmap;
88 1.6.4.2 snj }
89 1.6.4.2 snj
90 1.6.4.2 snj #define EXYNOS_IOPHYSTOVIRT(a) \
91 1.6.4.2 snj ((vaddr_t)(((a) - EXYNOS_CORE_PBASE) + EXYNOS_CORE_VBASE))
92 1.6.4.2 snj
93 1.6.4.2 snj static void
94 1.6.4.2 snj exynos_platform_bootstrap(void)
95 1.6.4.2 snj {
96 1.6.4.2 snj paddr_t uart_address = armreg_tpidruro_read(); /* XXX */
97 1.6.4.2 snj exynos_bootstrap(EXYNOS_CORE_VBASE, EXYNOS_IOPHYSTOVIRT(uart_address));
98 1.6.4.2 snj }
99 1.6.4.2 snj
100 1.6.4.2 snj static void
101 1.6.4.2 snj exynos_platform_init_attach_args(struct fdt_attach_args *faa)
102 1.6.4.2 snj {
103 1.6.4.2 snj extern struct bus_space armv7_generic_bs_tag;
104 1.6.4.2 snj extern struct bus_space armv7_generic_a4x_bs_tag;
105 1.6.4.2 snj extern struct arm32_bus_dma_tag armv7_generic_dma_tag;
106 1.6.4.2 snj
107 1.6.4.2 snj faa->faa_bst = &armv7_generic_bs_tag;
108 1.6.4.2 snj faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
109 1.6.4.2 snj faa->faa_dmat = &armv7_generic_dma_tag;
110 1.6.4.2 snj }
111 1.6.4.2 snj
112 1.6.4.2 snj static void
113 1.6.4.2 snj exynos_platform_early_putchar(char c)
114 1.6.4.2 snj {
115 1.6.4.2 snj #if defined(VERBOSE_INIT_ARM)
116 1.6.4.2 snj extern void exynos_putchar(int); /* XXX from exynos_start.S */
117 1.6.4.2 snj
118 1.6.4.2 snj exynos_putchar(c);
119 1.6.4.2 snj #endif
120 1.6.4.2 snj }
121 1.6.4.2 snj
122 1.6.4.2 snj static void
123 1.6.4.2 snj exynos_platform_device_register(device_t self, void *aux)
124 1.6.4.2 snj {
125 1.6.4.2 snj exynos_device_register(self, aux);
126 1.6.4.2 snj }
127 1.6.4.2 snj
128 1.6.4.2 snj static void
129 1.6.4.2 snj exynos5_platform_reset(void)
130 1.6.4.2 snj {
131 1.6.4.2 snj bus_space_tag_t bst = &armv7_generic_bs_tag;
132 1.6.4.2 snj bus_space_handle_t bsh;
133 1.6.4.2 snj
134 1.6.4.2 snj bus_space_map(bst, EXYNOS5_SWRESET_REG, 4, 0, &bsh);
135 1.6.4.2 snj bus_space_write_4(bst, bsh, 0, 1);
136 1.6.4.2 snj }
137 1.6.4.2 snj
138 1.6.4.2 snj static void
139 1.6.4.2 snj exynos_platform_delay(u_int us)
140 1.6.4.2 snj {
141 1.6.4.2 snj gtmr_delay(us);
142 1.6.4.2 snj }
143 1.6.4.2 snj
144 1.6.4.2 snj static u_int
145 1.6.4.2 snj exynos_platform_uart_freq(void)
146 1.6.4.2 snj {
147 1.6.4.2 snj return EXYNOS_UART_FREQ;
148 1.6.4.2 snj }
149 1.6.4.2 snj
150 1.6.4.2 snj static const struct arm_platform exynos5_platform = {
151 1.6.4.2 snj .devmap = exynos_platform_devmap,
152 1.6.4.2 snj .bootstrap = exynos_platform_bootstrap,
153 1.6.4.2 snj .init_attach_args = exynos_platform_init_attach_args,
154 1.6.4.2 snj .early_putchar = exynos_platform_early_putchar,
155 1.6.4.2 snj .device_register = exynos_platform_device_register,
156 1.6.4.2 snj .reset = exynos5_platform_reset,
157 1.6.4.2 snj .delay = exynos_platform_delay,
158 1.6.4.2 snj .uart_freq = exynos_platform_uart_freq,
159 1.6.4.2 snj };
160 1.6.4.2 snj
161 1.6.4.2 snj ARM_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform);
162