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exynos_platform.c revision 1.23 
      1 /* $NetBSD: exynos_platform.c,v 1.23 2019/01/27 02:08:37 pgoyette Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_arm_debug.h"
     30 #include "opt_console.h"
     31 #include "opt_exynos.h"
     32 #include "opt_multiprocessor.h"
     33 #include "opt_console.h"
     34 
     35 #include "ukbd.h"
     36 
     37 #include <sys/cdefs.h>
     38 __KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.23 2019/01/27 02:08:37 pgoyette Exp $");
     39 
     40 /* XXXJDM
     41  * Booting a CA7 core on Exynos5422 is currently broken, disable starting CA7 secondaries.
     42  */
     43 #define	EXYNOS5422_DISABLE_CA7_CLUSTER
     44 
     45 /* XXXJDM
     46  * Booting a CA7 core on Exynos5422 is currently broken, disable starting CA7 secondaries.
     47  */
     48 #define	EXYNOS5422_DISABLE_CA7_CLUSTER
     49 
     50 #include <sys/param.h>
     51 #include <sys/bus.h>
     52 #include <sys/cpu.h>
     53 #include <sys/device.h>
     54 #include <sys/termios.h>
     55 
     56 #include <dev/fdt/fdtvar.h>
     57 
     58 #include <uvm/uvm_extern.h>
     59 
     60 #include <machine/bootconfig.h>
     61 #include <arm/cpufunc.h>
     62 
     63 #include <arm/samsung/exynos_reg.h>
     64 #include <arm/samsung/exynos_var.h>
     65 #include <arm/samsung/mct_var.h>
     66 #include <arm/samsung/sscom_reg.h>
     67 
     68 #include <evbarm/exynos/platform.h>
     69 #include <evbarm/fdt/machdep.h>
     70 
     71 #include <arm/fdt/arm_fdtvar.h>
     72 
     73 #include <libfdt.h>
     74 
     75 void exynos_platform_early_putchar(char);
     76 
     77 #define	EXYNOS5800_PMU_BASE		0x10040000
     78 #define	EXYNOS5800_PMU_SIZE		0x20000
     79 #define	 EXYNOS5800_PMU_SWRESET			0x0400
     80 #define	  EXYNOS5800_PMU_KFC_ETM_RESET(n)	__BIT(20 + (n))
     81 #define	  EXYNOS5800_PMU_KFC_CORE_RESET(n)	__BIT(8 + (n))
     82 #define	 EXYNOS5800_PMU_SPARE2			0x0908
     83 #define	 EXYNOS5800_PMU_SPARE3			0x090c
     84 #define	  EXYNOS5800_PMU_SWRESET_KFC_SEL	0x3
     85 #define	 EXYNOS5800_PMU_CORE_CONFIG(n)		(0x2000 + 0x80 * (n))
     86 #define	 EXYNOS5800_PMU_CORE_STATUS(n)		(0x2004 + 0x80 * (n))
     87 #define	  EXYNOS5800_PMU_CORE_POWER_EN		0x3
     88 #define	 EXYNOS5800_PMU_COMMON_CONFIG(n)	(0x2500 + 0x80 * (n))
     89 #define	  EXYNOS5800_PMU_COMMON_POWER_EN	0x3
     90 #define	 EXYNOS5800_PMU_COMMON_OPTION(n)	(0x2508 + 0x80 * (n))
     91 #define	  EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE		__BIT(30)
     92 #define	  EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE	__BIT(29)
     93 #define	  EXYNOS5800_PMU_AUTO_CORE_DOWN			__BIT(9)
     94 
     95 #define	EXYNOS5800_SYSRAM_BASE		0x02073000
     96 #define	EXYNOS5800_SYSRAM_SIZE		0x1000
     97 #define	 EXYNOS5800_SYSRAM_HOTPLUG		0x001c
     98 
     99 static void
    100 exynos5800_mpstart(void)
    101 {
    102 #if defined(MULTIPROCESSOR)
    103 	bus_space_tag_t bst = &armv7_generic_bs_tag;
    104 	bus_space_handle_t pmu_bsh, sysram_bsh;
    105 	uint64_t mpidr, bp_mpidr;
    106 	uint32_t val, started = 0;
    107 	u_int cpuindex, n;
    108 	int child;
    109 
    110 	bus_space_map(bst, EXYNOS5800_PMU_BASE, EXYNOS5800_PMU_SIZE, 0, &pmu_bsh);
    111 	bus_space_map(bst, EXYNOS5800_SYSRAM_BASE, EXYNOS5800_SYSRAM_SIZE, 0, &sysram_bsh);
    112 
    113 	const int cpus = OF_finddevice("/cpus");
    114 	if (cpus == -1) {
    115 		aprint_error("%s: no /cpus node found\n", __func__);
    116 		return;
    117 	}
    118 
    119 	/* MPIDR affinity levels of boot processor. */
    120 	bp_mpidr = cpu_mpidr_aff_read();
    121 
    122 	/* Setup KFC reset */
    123 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE3, EXYNOS5800_PMU_SWRESET_KFC_SEL);
    124 
    125 	const uint32_t option = EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE |
    126 	    EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE |
    127 	    EXYNOS5800_PMU_AUTO_CORE_DOWN;
    128 	val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0));
    129 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0), val | option);
    130 	val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1));
    131 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1), val | option);
    132 
    133 	bus_space_write_4(bst, sysram_bsh, EXYNOS5800_SYSRAM_HOTPLUG, KERN_VTOPHYS((vaddr_t)cpu_mpstart));
    134 	arm_dsb();
    135 
    136 	/* Power on clusters */
    137 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(0),
    138 	    EXYNOS5800_PMU_COMMON_POWER_EN);
    139 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(1),
    140 	    EXYNOS5800_PMU_COMMON_POWER_EN);
    141 
    142 	/* Boot APs */
    143 	cpuindex = 1;
    144 	for (child = OF_child(cpus); child; child = OF_peer(child)) {
    145 		if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
    146 			continue;
    147 
    148 		if (mpidr == bp_mpidr)
    149 			continue;	/* BP already started */
    150 
    151 		const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
    152 		const u_int aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
    153 		const u_int cpu = cluster * 4 + aff0;
    154 
    155 #if defined(EXYNOS5422_DISABLE_CA7_CLUSTER)
    156 		if (cluster == 1)
    157 			continue;
    158 #endif
    159 
    160 		val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu));
    161 		bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_CONFIG(cpu),
    162 		    EXYNOS5800_PMU_CORE_POWER_EN);
    163 
    164 		for (n = 0x100000; n > 0; n--) {
    165 			val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu));
    166 			if ((val & EXYNOS5800_PMU_CORE_POWER_EN) == EXYNOS5800_PMU_CORE_POWER_EN) {
    167 				started |= __BIT(cpuindex);
    168 				break;
    169 			}
    170 		}
    171 		if (n == 0)
    172 			aprint_error("cpu%d: WARNING: AP failed to power on\n", cpuindex);
    173 
    174 		if (cluster == 1 && __SHIFTOUT(bp_mpidr, MPIDR_AFF1) == 1) {
    175 			while (bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE2) == 0)
    176 				;
    177 			bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SWRESET,
    178 			    EXYNOS5800_PMU_KFC_CORE_RESET(aff0) |
    179 			    EXYNOS5800_PMU_KFC_ETM_RESET(aff0));
    180 		}
    181 
    182 		/* Wait for AP to start */
    183 		for (n = 0x100000; n > 0; n--) {
    184 			membar_consumer();
    185 			if (arm_cpu_hatched & __BIT(cpuindex))
    186 				break;
    187 		}
    188 		if (n == 0)
    189 			aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex);
    190 
    191 		cpuindex++;
    192 	}
    193 
    194 	bus_space_unmap(bst, sysram_bsh, EXYNOS5800_SYSRAM_SIZE);
    195 	bus_space_unmap(bst, pmu_bsh, EXYNOS5800_PMU_SIZE);
    196 #endif
    197 }
    198 
    199 static struct of_compat_data mp_compat_data[] = {
    200 	{ "samsung,exynos5800",		(uintptr_t)exynos5800_mpstart },
    201 	{ NULL }
    202 };
    203 
    204 static void
    205 exynos_platform_mpstart(void)
    206 {
    207 
    208 	void (*mp_start)(void) = NULL;
    209 
    210 	const struct of_compat_data *cd = of_search_compatible(OF_finddevice("/"), mp_compat_data);
    211 	if (cd)
    212 		mp_start = (void (*)(void))cd->data;
    213 
    214 	if (mp_start)
    215 		mp_start();
    216 }
    217 
    218 static void
    219 exynos_platform_init_attach_args(struct fdt_attach_args *faa)
    220 {
    221 	extern struct bus_space armv7_generic_bs_tag;
    222 	extern struct bus_space armv7_generic_a4x_bs_tag;
    223 	extern struct arm32_bus_dma_tag arm_generic_dma_tag;
    224 
    225 	faa->faa_bst = &armv7_generic_bs_tag;
    226 	faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
    227 	faa->faa_dmat = &arm_generic_dma_tag;
    228 }
    229 
    230 void
    231 exynos_platform_early_putchar(char c)
    232 {
    233 #ifdef CONSADDR
    234 #define CONSADDR_VA	(CONSADDR - EXYNOS_CORE_PBASE + EXYNOS_CORE_VBASE)
    235 
    236 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
    237 	    (volatile uint32_t *)CONSADDR_VA :
    238 	    (volatile uint32_t *)CONSADDR;
    239 
    240 	while ((uartaddr[SSCOM_UFSTAT / 4] & UFSTAT_TXFULL) != 0)
    241 		;
    242 
    243 	uartaddr[SSCOM_UTXH / 4] = c;
    244 #endif
    245 }
    246 
    247 static void
    248 exynos_platform_device_register(device_t self, void *aux)
    249 {
    250 	exynos_device_register(self, aux);
    251 }
    252 
    253 static void
    254 exynos5_platform_reset(void)
    255 {
    256 	bus_space_tag_t bst = &armv7_generic_bs_tag;
    257 	bus_space_handle_t bsh;
    258 
    259 	bus_space_map(bst, EXYNOS5800_PMU_BASE + EXYNOS5800_PMU_SWRESET, 4, 0, &bsh);
    260 	bus_space_write_4(bst, bsh, 0, 1);
    261 }
    262 
    263 static u_int
    264 exynos_platform_uart_freq(void)
    265 {
    266 	return EXYNOS_UART_FREQ;
    267 }
    268 
    269 
    270 #if defined(SOC_EXYNOS4)
    271 static const struct pmap_devmap *
    272 exynos4_platform_devmap(void)
    273 {
    274 	static const struct pmap_devmap devmap[] = {
    275 		DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
    276 			     EXYNOS_CORE_PBASE,
    277 			     EXYNOS4_CORE_SIZE),
    278 		DEVMAP_ENTRY(EXYNOS4_AUDIOCORE_VBASE,
    279 			     EXYNOS4_AUDIOCORE_PBASE,
    280 			     EXYNOS4_AUDIOCORE_SIZE),
    281 		DEVMAP_ENTRY_END
    282 	};
    283 
    284 	return devmap;
    285 }
    286 
    287 static void
    288 exynos4_platform_bootstrap(void)
    289 {
    290 
    291 	exynos_bootstrap(4);
    292 
    293 #if defined(MULTIPROCESSOR)
    294 	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
    295 #endif
    296 }
    297 
    298 static const struct arm_platform exynos4_platform = {
    299 	.ap_devmap = exynos4_platform_devmap,
    300 //	.ap_mpstart = exynos4_mpstart,
    301 	.ap_bootstrap = exynos4_platform_bootstrap,
    302 	.ap_init_attach_args = exynos_platform_init_attach_args,
    303 	.ap_device_register = exynos_platform_device_register,
    304 	.ap_reset = exynos5_platform_reset,
    305 	.ap_delay = mct_delay,
    306 	.ap_uart_freq = exynos_platform_uart_freq,
    307 };
    308 
    309 ARM_PLATFORM(exynos4, "samsung,exynos4", &exynos4_platform);
    310 #endif
    311 
    312 
    313 #if defined(SOC_EXYNOS5)
    314 static const struct pmap_devmap *
    315 exynos5_platform_devmap(void)
    316 {
    317 	static const struct pmap_devmap devmap[] = {
    318 		DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
    319 			     EXYNOS_CORE_PBASE,
    320 			     EXYNOS5_CORE_SIZE),
    321 		DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE,
    322 			     EXYNOS5_AUDIOCORE_PBASE,
    323 			     EXYNOS5_AUDIOCORE_SIZE),
    324 		DEVMAP_ENTRY(EXYNOS5_SYSRAM_VBASE,
    325 			     EXYNOS5_SYSRAM_PBASE,
    326 			     EXYNOS5_SYSRAM_SIZE),
    327 		DEVMAP_ENTRY_END
    328 	};
    329 
    330 	return devmap;
    331 }
    332 
    333 static void
    334 exynos5_platform_bootstrap(void)
    335 {
    336 
    337 	exynos_bootstrap(5);
    338 
    339 #if defined(MULTIPROCESSOR) && defined(EXYNOS5422_DISABLE_CA7_CLUSTER)
    340 	const struct of_compat_data *cd = of_search_compatible(OF_finddevice("/"), mp_compat_data);
    341 	if (cd && cd->data == (uintptr_t)exynos5800_mpstart) {
    342 		void *fdt_data = __UNCONST(fdtbus_get_data());
    343 		int cpu_off, cpus_off, len;
    344 
    345 		cpus_off = fdt_path_offset(fdt_data, "/cpus");
    346 		if (cpus_off < 0)
    347 			return;
    348 
    349 		fdt_for_each_subnode(cpu_off, fdt_data, cpus_off) {
    350 			const void *prop = fdt_getprop(fdt_data, cpu_off, "reg", &len);
    351 			if (len != 4)
    352 				continue;
    353 			const uint32_t mpidr = be32dec(prop);
    354 			if (mpidr != cpu_mpidr_aff_read() && __SHIFTOUT(mpidr, MPIDR_AFF1) == 1)
    355 				fdt_setprop_string(fdt_data, cpu_off, "status", "fail");
    356 		}
    357 	}
    358 #endif
    359 
    360 	arm_fdt_cpu_bootstrap();
    361 }
    362 
    363 static const struct arm_platform exynos5_platform = {
    364 	.ap_devmap = exynos5_platform_devmap,
    365 	.ap_bootstrap = exynos5_platform_bootstrap,
    366 	.ap_mpstart = exynos_platform_mpstart,
    367 	.ap_init_attach_args = exynos_platform_init_attach_args,
    368 	.ap_device_register = exynos_platform_device_register,
    369 	.ap_reset = exynos5_platform_reset,
    370 	.ap_delay = mct_delay,
    371 	.ap_uart_freq = exynos_platform_uart_freq,
    372 };
    373 
    374 ARM_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform);
    375 #endif
    376