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exynos_platform.c revision 1.25 
      1 /* $NetBSD: exynos_platform.c,v 1.25 2019/01/31 13:06:10 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_arm_debug.h"
     30 #include "opt_console.h"
     31 #include "opt_exynos.h"
     32 #include "opt_multiprocessor.h"
     33 #include "opt_console.h"
     34 
     35 #include "ukbd.h"
     36 
     37 #include <sys/cdefs.h>
     38 __KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.25 2019/01/31 13:06:10 skrll Exp $");
     39 
     40 /* XXXJDM
     41  * Booting a CA7 core on Exynos5422 is currently broken, disable starting CA7 secondaries.
     42  */
     43 #define	EXYNOS5422_DISABLE_CA7_CLUSTER
     44 
     45 #include <sys/param.h>
     46 #include <sys/bus.h>
     47 #include <sys/cpu.h>
     48 #include <sys/device.h>
     49 #include <sys/termios.h>
     50 
     51 #include <dev/fdt/fdtvar.h>
     52 
     53 #include <uvm/uvm_extern.h>
     54 
     55 #include <machine/bootconfig.h>
     56 #include <arm/cpufunc.h>
     57 
     58 #include <arm/samsung/exynos_reg.h>
     59 #include <arm/samsung/exynos_var.h>
     60 #include <arm/samsung/mct_var.h>
     61 #include <arm/samsung/sscom_reg.h>
     62 
     63 #include <evbarm/exynos/platform.h>
     64 #include <evbarm/fdt/machdep.h>
     65 
     66 #include <arm/fdt/arm_fdtvar.h>
     67 
     68 #include <libfdt.h>
     69 
     70 void exynos_platform_early_putchar(char);
     71 
     72 #define	EXYNOS5800_PMU_BASE		0x10040000
     73 #define	EXYNOS5800_PMU_SIZE		0x20000
     74 #define	 EXYNOS5800_PMU_SWRESET			0x0400
     75 #define	  EXYNOS5800_PMU_KFC_ETM_RESET(n)	__BIT(20 + (n))
     76 #define	  EXYNOS5800_PMU_KFC_CORE_RESET(n)	__BIT(8 + (n))
     77 #define	 EXYNOS5800_PMU_SPARE2			0x0908
     78 #define	 EXYNOS5800_PMU_SPARE3			0x090c
     79 #define	  EXYNOS5800_PMU_SWRESET_KFC_SEL	0x3
     80 #define	 EXYNOS5800_PMU_CORE_CONFIG(n)		(0x2000 + 0x80 * (n))
     81 #define	 EXYNOS5800_PMU_CORE_STATUS(n)		(0x2004 + 0x80 * (n))
     82 #define	  EXYNOS5800_PMU_CORE_POWER_EN		0x3
     83 #define	 EXYNOS5800_PMU_COMMON_CONFIG(n)	(0x2500 + 0x80 * (n))
     84 #define	  EXYNOS5800_PMU_COMMON_POWER_EN	0x3
     85 #define	 EXYNOS5800_PMU_COMMON_OPTION(n)	(0x2508 + 0x80 * (n))
     86 #define	  EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE		__BIT(30)
     87 #define	  EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE	__BIT(29)
     88 #define	  EXYNOS5800_PMU_AUTO_CORE_DOWN			__BIT(9)
     89 
     90 #define	EXYNOS5800_SYSRAM_BASE		0x02073000
     91 #define	EXYNOS5800_SYSRAM_SIZE		0x1000
     92 #define	 EXYNOS5800_SYSRAM_HOTPLUG		0x001c
     93 
     94 static int
     95 exynos5800_mpstart(void)
     96 {
     97 	int ret = 0;
     98 #if defined(MULTIPROCESSOR)
     99 	bus_space_tag_t bst = &armv7_generic_bs_tag;
    100 	bus_space_handle_t pmu_bsh, sysram_bsh;
    101 	uint64_t mpidr, bp_mpidr;
    102 	uint32_t val, started = 0;
    103 	u_int cpuindex, n;
    104 	int child;
    105 
    106 	bus_space_map(bst, EXYNOS5800_PMU_BASE, EXYNOS5800_PMU_SIZE, 0, &pmu_bsh);
    107 	bus_space_map(bst, EXYNOS5800_SYSRAM_BASE, EXYNOS5800_SYSRAM_SIZE, 0, &sysram_bsh);
    108 
    109 	const int cpus = OF_finddevice("/cpus");
    110 	if (cpus == -1) {
    111 		aprint_error("%s: no /cpus node found\n", __func__);
    112 		return ret;
    113 	}
    114 
    115 	/* MPIDR affinity levels of boot processor. */
    116 	bp_mpidr = cpu_mpidr_aff_read();
    117 
    118 	/* Setup KFC reset */
    119 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE3, EXYNOS5800_PMU_SWRESET_KFC_SEL);
    120 
    121 	const uint32_t option = EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE |
    122 	    EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE |
    123 	    EXYNOS5800_PMU_AUTO_CORE_DOWN;
    124 	val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0));
    125 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0), val | option);
    126 	val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1));
    127 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1), val | option);
    128 
    129 	bus_space_write_4(bst, sysram_bsh, EXYNOS5800_SYSRAM_HOTPLUG, KERN_VTOPHYS((vaddr_t)cpu_mpstart));
    130 	arm_dsb();
    131 
    132 	/* Power on clusters */
    133 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(0),
    134 	    EXYNOS5800_PMU_COMMON_POWER_EN);
    135 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(1),
    136 	    EXYNOS5800_PMU_COMMON_POWER_EN);
    137 
    138 	/* Boot APs */
    139 	cpuindex = 1;
    140 	for (child = OF_child(cpus); child; child = OF_peer(child)) {
    141 		if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
    142 			continue;
    143 
    144 		if (mpidr == bp_mpidr)
    145 			continue;	/* BP already started */
    146 
    147 		const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
    148 		const u_int aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
    149 		const u_int cpu = cluster * 4 + aff0;
    150 
    151 #if defined(EXYNOS5422_DISABLE_CA7_CLUSTER)
    152 		if (cluster == 1)
    153 			continue;
    154 #endif
    155 
    156 		val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu));
    157 		bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_CONFIG(cpu),
    158 		    EXYNOS5800_PMU_CORE_POWER_EN);
    159 
    160 		for (n = 0x100000; n > 0; n--) {
    161 			val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu));
    162 			if ((val & EXYNOS5800_PMU_CORE_POWER_EN) == EXYNOS5800_PMU_CORE_POWER_EN) {
    163 				started |= __BIT(cpuindex);
    164 				break;
    165 			}
    166 		}
    167 		if (n == 0)
    168 			aprint_error("cpu%d: WARNING: AP failed to power on\n", cpuindex);
    169 
    170 		if (cluster == 1 && __SHIFTOUT(bp_mpidr, MPIDR_AFF1) == 1) {
    171 			while (bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE2) == 0)
    172 				;
    173 			bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SWRESET,
    174 			    EXYNOS5800_PMU_KFC_CORE_RESET(aff0) |
    175 			    EXYNOS5800_PMU_KFC_ETM_RESET(aff0));
    176 		}
    177 
    178 		/* Wait for AP to start */
    179 		for (n = 0x100000; n > 0; n--) {
    180 			membar_consumer();
    181 			if (arm_cpu_hatched & __BIT(cpuindex))
    182 				break;
    183 		}
    184 		if (n == 0) {
    185 			ret++;
    186 			aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex);
    187 		}
    188 
    189 		cpuindex++;
    190 	}
    191 
    192 	bus_space_unmap(bst, sysram_bsh, EXYNOS5800_SYSRAM_SIZE);
    193 	bus_space_unmap(bst, pmu_bsh, EXYNOS5800_PMU_SIZE);
    194 #endif
    195 	return ret;
    196 }
    197 
    198 static struct of_compat_data mp_compat_data[] = {
    199 	{ "samsung,exynos5800",		(uintptr_t)exynos5800_mpstart },
    200 	{ NULL }
    201 };
    202 
    203 static int
    204 exynos_platform_mpstart(void)
    205 {
    206 
    207 	int (*mp_start)(void) = NULL;
    208 
    209 	const struct of_compat_data *cd = of_search_compatible(OF_finddevice("/"), mp_compat_data);
    210 	if (cd)
    211 		mp_start = (int (*)(void))cd->data;
    212 
    213 	if (mp_start)
    214 		return mp_start();
    215 
    216 	return 0;
    217 }
    218 
    219 static void
    220 exynos_platform_init_attach_args(struct fdt_attach_args *faa)
    221 {
    222 	extern struct bus_space armv7_generic_bs_tag;
    223 	extern struct bus_space armv7_generic_a4x_bs_tag;
    224 	extern struct arm32_bus_dma_tag arm_generic_dma_tag;
    225 
    226 	faa->faa_bst = &armv7_generic_bs_tag;
    227 	faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
    228 	faa->faa_dmat = &arm_generic_dma_tag;
    229 }
    230 
    231 void
    232 exynos_platform_early_putchar(char c)
    233 {
    234 #ifdef CONSADDR
    235 #define CONSADDR_VA	(CONSADDR - EXYNOS_CORE_PBASE + EXYNOS_CORE_VBASE)
    236 
    237 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
    238 	    (volatile uint32_t *)CONSADDR_VA :
    239 	    (volatile uint32_t *)CONSADDR;
    240 
    241 	while ((uartaddr[SSCOM_UFSTAT / 4] & UFSTAT_TXFULL) != 0)
    242 		;
    243 
    244 	uartaddr[SSCOM_UTXH / 4] = c;
    245 #endif
    246 }
    247 
    248 static void
    249 exynos_platform_device_register(device_t self, void *aux)
    250 {
    251 	exynos_device_register(self, aux);
    252 }
    253 
    254 static void
    255 exynos5_platform_reset(void)
    256 {
    257 	bus_space_tag_t bst = &armv7_generic_bs_tag;
    258 	bus_space_handle_t bsh;
    259 
    260 	bus_space_map(bst, EXYNOS5800_PMU_BASE + EXYNOS5800_PMU_SWRESET, 4, 0, &bsh);
    261 	bus_space_write_4(bst, bsh, 0, 1);
    262 }
    263 
    264 static u_int
    265 exynos_platform_uart_freq(void)
    266 {
    267 	return EXYNOS_UART_FREQ;
    268 }
    269 
    270 
    271 #if defined(SOC_EXYNOS4)
    272 static const struct pmap_devmap *
    273 exynos4_platform_devmap(void)
    274 {
    275 	static const struct pmap_devmap devmap[] = {
    276 		DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
    277 			     EXYNOS_CORE_PBASE,
    278 			     EXYNOS4_CORE_SIZE),
    279 		DEVMAP_ENTRY(EXYNOS4_AUDIOCORE_VBASE,
    280 			     EXYNOS4_AUDIOCORE_PBASE,
    281 			     EXYNOS4_AUDIOCORE_SIZE),
    282 		DEVMAP_ENTRY_END
    283 	};
    284 
    285 	return devmap;
    286 }
    287 
    288 static void
    289 exynos4_platform_bootstrap(void)
    290 {
    291 
    292 	exynos_bootstrap(4);
    293 
    294 #if defined(MULTIPROCESSOR)
    295 	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
    296 #endif
    297 }
    298 
    299 static const struct arm_platform exynos4_platform = {
    300 	.ap_devmap = exynos4_platform_devmap,
    301 //	.ap_mpstart = exynos4_mpstart,
    302 	.ap_bootstrap = exynos4_platform_bootstrap,
    303 	.ap_init_attach_args = exynos_platform_init_attach_args,
    304 	.ap_device_register = exynos_platform_device_register,
    305 	.ap_reset = exynos5_platform_reset,
    306 	.ap_delay = mct_delay,
    307 	.ap_uart_freq = exynos_platform_uart_freq,
    308 };
    309 
    310 ARM_PLATFORM(exynos4, "samsung,exynos4", &exynos4_platform);
    311 #endif
    312 
    313 
    314 #if defined(SOC_EXYNOS5)
    315 static const struct pmap_devmap *
    316 exynos5_platform_devmap(void)
    317 {
    318 	static const struct pmap_devmap devmap[] = {
    319 		DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
    320 			     EXYNOS_CORE_PBASE,
    321 			     EXYNOS5_CORE_SIZE),
    322 		DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE,
    323 			     EXYNOS5_AUDIOCORE_PBASE,
    324 			     EXYNOS5_AUDIOCORE_SIZE),
    325 		DEVMAP_ENTRY(EXYNOS5_SYSRAM_VBASE,
    326 			     EXYNOS5_SYSRAM_PBASE,
    327 			     EXYNOS5_SYSRAM_SIZE),
    328 		DEVMAP_ENTRY_END
    329 	};
    330 
    331 	return devmap;
    332 }
    333 
    334 static void
    335 exynos5_platform_bootstrap(void)
    336 {
    337 
    338 	exynos_bootstrap(5);
    339 
    340 #if defined(MULTIPROCESSOR) && defined(EXYNOS5422_DISABLE_CA7_CLUSTER)
    341 	const struct of_compat_data *cd = of_search_compatible(OF_finddevice("/"), mp_compat_data);
    342 	if (cd && cd->data == (uintptr_t)exynos5800_mpstart) {
    343 		void *fdt_data = __UNCONST(fdtbus_get_data());
    344 		int cpu_off, cpus_off, len;
    345 
    346 		cpus_off = fdt_path_offset(fdt_data, "/cpus");
    347 		if (cpus_off < 0)
    348 			return;
    349 
    350 		fdt_for_each_subnode(cpu_off, fdt_data, cpus_off) {
    351 			const void *prop = fdt_getprop(fdt_data, cpu_off, "reg", &len);
    352 			if (len != 4)
    353 				continue;
    354 			const uint32_t mpidr = be32dec(prop);
    355 			if (mpidr != cpu_mpidr_aff_read() && __SHIFTOUT(mpidr, MPIDR_AFF1) == 1)
    356 				fdt_setprop_string(fdt_data, cpu_off, "status", "fail");
    357 		}
    358 	}
    359 #endif
    360 
    361 	arm_fdt_cpu_bootstrap();
    362 }
    363 
    364 static const struct arm_platform exynos5_platform = {
    365 	.ap_devmap = exynos5_platform_devmap,
    366 	.ap_bootstrap = exynos5_platform_bootstrap,
    367 	.ap_mpstart = exynos_platform_mpstart,
    368 	.ap_init_attach_args = exynos_platform_init_attach_args,
    369 	.ap_device_register = exynos_platform_device_register,
    370 	.ap_reset = exynos5_platform_reset,
    371 	.ap_delay = mct_delay,
    372 	.ap_uart_freq = exynos_platform_uart_freq,
    373 };
    374 
    375 ARM_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform);
    376 #endif
    377