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exynos_platform.c revision 1.27 
      1 /* $NetBSD: exynos_platform.c,v 1.27 2020/02/15 08:16:11 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_arm_debug.h"
     30 #include "opt_console.h"
     31 #include "opt_exynos.h"
     32 #include "opt_multiprocessor.h"
     33 #include "opt_console.h"
     34 
     35 #include "ukbd.h"
     36 
     37 #include <sys/cdefs.h>
     38 __KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.27 2020/02/15 08:16:11 skrll Exp $");
     39 
     40 #include <sys/param.h>
     41 #include <sys/bus.h>
     42 #include <sys/cpu.h>
     43 #include <sys/device.h>
     44 #include <sys/termios.h>
     45 
     46 #include <dev/fdt/fdtvar.h>
     47 
     48 #include <uvm/uvm_extern.h>
     49 
     50 #include <machine/bootconfig.h>
     51 #include <arm/cpufunc.h>
     52 
     53 #include <arm/samsung/exynos_reg.h>
     54 #include <arm/samsung/exynos_var.h>
     55 #include <arm/samsung/mct_var.h>
     56 #include <arm/samsung/sscom_reg.h>
     57 
     58 #include <evbarm/exynos/platform.h>
     59 #include <evbarm/fdt/machdep.h>
     60 
     61 #include <arm/fdt/arm_fdtvar.h>
     62 
     63 #include <libfdt.h>
     64 
     65 void exynos_platform_early_putchar(char);
     66 
     67 #define	EXYNOS5800_PMU_BASE		0x10040000
     68 #define	EXYNOS5800_PMU_SIZE		0x20000
     69 #define	 EXYNOS5800_PMU_SWRESET			0x0400
     70 #define	  EXYNOS5800_PMU_KFC_ETM_RESET(n)	__BIT(20 + (n))
     71 #define	  EXYNOS5800_PMU_KFC_CORE_RESET(n)	__BIT(8 + (n))
     72 #define	 EXYNOS5800_PMU_SPARE2			0x0908
     73 #define	 EXYNOS5800_PMU_SPARE3			0x090c
     74 #define	  EXYNOS5800_PMU_SWRESET_KFC_SEL	0x3
     75 #define	 EXYNOS5800_PMU_CORE_CONFIG(n)		(0x2000 + 0x80 * (n))
     76 #define	 EXYNOS5800_PMU_CORE_STATUS(n)		(0x2004 + 0x80 * (n))
     77 #define	  EXYNOS5800_PMU_CORE_POWER_EN		0x3
     78 #define	 EXYNOS5800_PMU_COMMON_CONFIG(n)	(0x2500 + 0x80 * (n))
     79 #define	  EXYNOS5800_PMU_COMMON_POWER_EN	0x3
     80 #define	 EXYNOS5800_PMU_COMMON_OPTION(n)	(0x2508 + 0x80 * (n))
     81 #define	  EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE		__BIT(30)
     82 #define	  EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE	__BIT(29)
     83 #define	  EXYNOS5800_PMU_AUTO_CORE_DOWN			__BIT(9)
     84 
     85 #define	EXYNOS5800_SYSRAM_BASE		0x02073000
     86 #define	EXYNOS5800_SYSRAM_SIZE		0x1000
     87 #define	 EXYNOS5800_SYSRAM_HOTPLUG		0x001c
     88 
     89 static int
     90 exynos5800_mpstart(void)
     91 {
     92 	int ret = 0;
     93 #if defined(MULTIPROCESSOR)
     94 	bus_space_tag_t bst = &armv7_generic_bs_tag;
     95 	bus_space_handle_t pmu_bsh, sysram_bsh;
     96 	uint64_t mpidr, bp_mpidr;
     97 	uint32_t val, started = 0;
     98 	u_int cpuindex, n;
     99 	int child;
    100 
    101 	bus_space_map(bst, EXYNOS5800_PMU_BASE, EXYNOS5800_PMU_SIZE, 0, &pmu_bsh);
    102 	bus_space_map(bst, EXYNOS5800_SYSRAM_BASE, EXYNOS5800_SYSRAM_SIZE, 0, &sysram_bsh);
    103 
    104 	const int cpus = OF_finddevice("/cpus");
    105 	if (cpus == -1) {
    106 		aprint_error("%s: no /cpus node found\n", __func__);
    107 		return ret;
    108 	}
    109 
    110 	/* MPIDR affinity levels of boot processor. */
    111 	bp_mpidr = cpu_mpidr_aff_read();
    112 
    113 	/* Setup KFC reset */
    114 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE3, EXYNOS5800_PMU_SWRESET_KFC_SEL);
    115 
    116 	const uint32_t option = EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE |
    117 	    EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE |
    118 	    EXYNOS5800_PMU_AUTO_CORE_DOWN;
    119 	val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0));
    120 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0), val | option);
    121 	val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1));
    122 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1), val | option);
    123 
    124 	bus_space_write_4(bst, sysram_bsh, EXYNOS5800_SYSRAM_HOTPLUG, KERN_VTOPHYS((vaddr_t)cpu_mpstart));
    125 	arm_dsb();
    126 
    127 	/* Power on clusters */
    128 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(0),
    129 	    EXYNOS5800_PMU_COMMON_POWER_EN);
    130 	bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(1),
    131 	    EXYNOS5800_PMU_COMMON_POWER_EN);
    132 
    133 	/* Boot APs */
    134 	cpuindex = 1;
    135 	for (child = OF_child(cpus); child; child = OF_peer(child)) {
    136 		if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
    137 			continue;
    138 
    139 		if (mpidr == bp_mpidr)
    140 			continue;	/* BP already started */
    141 
    142 		const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
    143 		const u_int aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
    144 		const u_int cpu = cluster * 4 + aff0;
    145 
    146 		val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu));
    147 		bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_CONFIG(cpu),
    148 		    EXYNOS5800_PMU_CORE_POWER_EN);
    149 
    150 		for (n = 0x100000; n > 0; n--) {
    151 			val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu));
    152 			if ((val & EXYNOS5800_PMU_CORE_POWER_EN) == EXYNOS5800_PMU_CORE_POWER_EN) {
    153 				started |= __BIT(cpuindex);
    154 				break;
    155 			}
    156 		}
    157 		if (n == 0)
    158 			aprint_error("cpu%d: WARNING: AP failed to power on\n", cpuindex);
    159 
    160 		if (cluster == 1 && __SHIFTOUT(bp_mpidr, MPIDR_AFF1) == 1) {
    161 			while (bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE2) == 0)
    162 				;
    163 			bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SWRESET,
    164 			    EXYNOS5800_PMU_KFC_CORE_RESET(aff0) |
    165 			    EXYNOS5800_PMU_KFC_ETM_RESET(aff0));
    166 		}
    167 
    168 		/* Wait for AP to start */
    169 		for (n = 0x100000; n > 0; n--) {
    170 			membar_consumer();
    171 			if (cpu_hatched_p(cpuindex))
    172 				break;
    173 		}
    174 		if (n == 0) {
    175 			ret++;
    176 			aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex);
    177 		}
    178 
    179 		cpuindex++;
    180 	}
    181 
    182 	bus_space_unmap(bst, sysram_bsh, EXYNOS5800_SYSRAM_SIZE);
    183 	bus_space_unmap(bst, pmu_bsh, EXYNOS5800_PMU_SIZE);
    184 #endif
    185 	return ret;
    186 }
    187 
    188 static struct of_compat_data mp_compat_data[] = {
    189 	{ "samsung,exynos5800",		(uintptr_t)exynos5800_mpstart },
    190 	{ NULL }
    191 };
    192 
    193 static int
    194 exynos_platform_mpstart(void)
    195 {
    196 
    197 	int (*mp_start)(void) = NULL;
    198 
    199 	const struct of_compat_data *cd = of_search_compatible(OF_finddevice("/"), mp_compat_data);
    200 	if (cd)
    201 		mp_start = (int (*)(void))cd->data;
    202 
    203 	if (mp_start)
    204 		return mp_start();
    205 
    206 	return 0;
    207 }
    208 
    209 static void
    210 exynos_platform_init_attach_args(struct fdt_attach_args *faa)
    211 {
    212 	extern struct bus_space armv7_generic_bs_tag;
    213 	extern struct bus_space armv7_generic_a4x_bs_tag;
    214 	extern struct arm32_bus_dma_tag arm_generic_dma_tag;
    215 
    216 	faa->faa_bst = &armv7_generic_bs_tag;
    217 	faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
    218 	faa->faa_dmat = &arm_generic_dma_tag;
    219 }
    220 
    221 void
    222 exynos_platform_early_putchar(char c)
    223 {
    224 #ifdef CONSADDR
    225 #define CONSADDR_VA	(CONSADDR - EXYNOS_CORE_PBASE + EXYNOS_CORE_VBASE)
    226 
    227 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
    228 	    (volatile uint32_t *)CONSADDR_VA :
    229 	    (volatile uint32_t *)CONSADDR;
    230 
    231 	while ((uartaddr[SSCOM_UFSTAT / 4] & UFSTAT_TXFULL) != 0)
    232 		;
    233 
    234 	uartaddr[SSCOM_UTXH / 4] = c;
    235 #endif
    236 }
    237 
    238 static void
    239 exynos_platform_device_register(device_t self, void *aux)
    240 {
    241 	exynos_device_register(self, aux);
    242 }
    243 
    244 static void
    245 exynos5_platform_reset(void)
    246 {
    247 	bus_space_tag_t bst = &armv7_generic_bs_tag;
    248 	bus_space_handle_t bsh;
    249 
    250 	bus_space_map(bst, EXYNOS5800_PMU_BASE + EXYNOS5800_PMU_SWRESET, 4, 0, &bsh);
    251 	bus_space_write_4(bst, bsh, 0, 1);
    252 }
    253 
    254 static u_int
    255 exynos_platform_uart_freq(void)
    256 {
    257 	return EXYNOS_UART_FREQ;
    258 }
    259 
    260 
    261 #if defined(SOC_EXYNOS4)
    262 static const struct pmap_devmap *
    263 exynos4_platform_devmap(void)
    264 {
    265 	static const struct pmap_devmap devmap[] = {
    266 		DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
    267 			     EXYNOS_CORE_PBASE,
    268 			     EXYNOS4_CORE_SIZE),
    269 		DEVMAP_ENTRY(EXYNOS4_AUDIOCORE_VBASE,
    270 			     EXYNOS4_AUDIOCORE_PBASE,
    271 			     EXYNOS4_AUDIOCORE_SIZE),
    272 		DEVMAP_ENTRY_END
    273 	};
    274 
    275 	return devmap;
    276 }
    277 
    278 static void
    279 exynos4_platform_bootstrap(void)
    280 {
    281 
    282 	exynos_bootstrap(4);
    283 
    284 #if defined(MULTIPROCESSOR)
    285 	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
    286 #endif
    287 }
    288 
    289 static const struct arm_platform exynos4_platform = {
    290 	.ap_devmap = exynos4_platform_devmap,
    291 //	.ap_mpstart = exynos4_mpstart,
    292 	.ap_bootstrap = exynos4_platform_bootstrap,
    293 	.ap_init_attach_args = exynos_platform_init_attach_args,
    294 	.ap_device_register = exynos_platform_device_register,
    295 	.ap_reset = exynos5_platform_reset,
    296 	.ap_delay = mct_delay,
    297 	.ap_uart_freq = exynos_platform_uart_freq,
    298 };
    299 
    300 ARM_PLATFORM(exynos4, "samsung,exynos4", &exynos4_platform);
    301 #endif
    302 
    303 
    304 #if defined(SOC_EXYNOS5)
    305 static const struct pmap_devmap *
    306 exynos5_platform_devmap(void)
    307 {
    308 	static const struct pmap_devmap devmap[] = {
    309 		DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
    310 			     EXYNOS_CORE_PBASE,
    311 			     EXYNOS5_CORE_SIZE),
    312 		DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE,
    313 			     EXYNOS5_AUDIOCORE_PBASE,
    314 			     EXYNOS5_AUDIOCORE_SIZE),
    315 		DEVMAP_ENTRY(EXYNOS5_SYSRAM_VBASE,
    316 			     EXYNOS5_SYSRAM_PBASE,
    317 			     EXYNOS5_SYSRAM_SIZE),
    318 		DEVMAP_ENTRY_END
    319 	};
    320 
    321 	return devmap;
    322 }
    323 
    324 static void
    325 exynos5_platform_bootstrap(void)
    326 {
    327 
    328 	exynos_bootstrap(5);
    329 
    330 	arm_fdt_cpu_bootstrap();
    331 }
    332 
    333 static const struct arm_platform exynos5_platform = {
    334 	.ap_devmap = exynos5_platform_devmap,
    335 	.ap_bootstrap = exynos5_platform_bootstrap,
    336 	.ap_mpstart = exynos_platform_mpstart,
    337 	.ap_init_attach_args = exynos_platform_init_attach_args,
    338 	.ap_device_register = exynos_platform_device_register,
    339 	.ap_reset = exynos5_platform_reset,
    340 	.ap_delay = mct_delay,
    341 	.ap_uart_freq = exynos_platform_uart_freq,
    342 };
    343 
    344 ARM_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform);
    345 #endif
    346