exynos_reg.h revision 1.5.4.2
1 1.5.4.2 yamt /* $NetBSD */ 2 1.5.4.2 yamt /*- 3 1.5.4.2 yamt * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 1.5.4.2 yamt * All rights reserved. 5 1.5.4.2 yamt * 6 1.5.4.2 yamt * This code is derived from software contributed to The NetBSD Foundation 7 1.5.4.2 yamt * by Reinoud Zandijk. 8 1.5.4.2 yamt * 9 1.5.4.2 yamt * Redistribution and use in source and binary forms, with or without 10 1.5.4.2 yamt * modification, are permitted provided that the following conditions 11 1.5.4.2 yamt * are met: 12 1.5.4.2 yamt * 1. Redistributions of source code must retain the above copyright 13 1.5.4.2 yamt * notice, this list of conditions and the following disclaimer. 14 1.5.4.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 15 1.5.4.2 yamt * notice, this list of conditions and the following disclaimer in the 16 1.5.4.2 yamt * documentation and/or other materials provided with the distribution. 17 1.5.4.2 yamt * 18 1.5.4.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.5.4.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.5.4.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.5.4.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.5.4.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.5.4.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.5.4.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.5.4.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.5.4.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.5.4.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.5.4.2 yamt * POSSIBILITY OF SUCH DAMAGE. 29 1.5.4.2 yamt */ 30 1.5.4.2 yamt 31 1.5.4.2 yamt #ifndef _ARM_SAMSUNG_EXYNOS_REG_H_ 32 1.5.4.2 yamt #define _ARM_SAMSUNG_EXYNOS_REG_H_ 33 1.5.4.2 yamt 34 1.5.4.2 yamt /* 35 1.5.4.2 yamt * 36 1.5.4.2 yamt * The exynos can boot from its iROM or from an external Nand memory. Since 37 1.5.4.2 yamt * these are normally hardly used they are excluded from the normal register 38 1.5.4.2 yamt * space here. 39 1.5.4.2 yamt * 40 1.5.4.2 yamt * XXX What about the audio subsystem region. Where are the docs? 41 1.5.4.2 yamt * 42 1.5.4.2 yamt * EXYNOS_CORE_PBASE points to the main SFR region. 43 1.5.4.2 yamt * 44 1.5.4.2 yamt * Notes: 45 1.5.4.2 yamt * 46 1.5.4.2 yamt * SFR Special Function Register 47 1.5.4.2 yamt * ISP In-System Programming, like a JTAG 48 1.5.4.2 yamt * ACP Accelerator Coherency Port 49 1.5.4.2 yamt * SSS Security Sub System 50 1.5.4.2 yamt * GIC Generic Interurrupt Controller 51 1.5.4.2 yamt * PMU Power Management Unit 52 1.5.4.2 yamt * DMC 2D Graphics engine 53 1.5.4.2 yamt * LEFTBUS Data bus / Peripheral bus 54 1.5.4.2 yamt * RIGHTBUS ,, 55 1.5.4.2 yamt * G3D 3D Graphics engine 56 1.5.4.2 yamt * MFC Multi-Format Codec 57 1.5.4.2 yamt * LCD0 LCD display 58 1.5.4.2 yamt * MCT Multi Core Timer 59 1.5.4.2 yamt * CMU Clock Management Unit 60 1.5.4.2 yamt * TMU Thermal Management Unit 61 1.5.4.2 yamt * PPMU Pin Parametric Measurement Unit (?) 62 1.5.4.2 yamt * MMU Memory Management Unit 63 1.5.4.2 yamt * MCTimer ? 64 1.5.4.2 yamt * WDT Watch Dog Timer 65 1.5.4.2 yamt * RTC Real Time Clock 66 1.5.4.2 yamt * KEYIF Keypad interface 67 1.5.4.2 yamt * SECKEY ? 68 1.5.4.2 yamt * TZPC TrustZone Protection Controller 69 1.5.4.2 yamt * UART Universal asynchronous receiver/transmitter 70 1.5.4.2 yamt * I2C Inter IC Connect 71 1.5.4.2 yamt * SPI Serial Peripheral Interface Bus 72 1.5.4.2 yamt * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS 73 1.5.4.2 yamt * PCM Pulse-code modulation, audio stream at set fixed rate 74 1.5.4.2 yamt * SPDIF Sony/Philips Digital Interface Format 75 1.5.4.2 yamt * Slimbus Serial Low-power Inter-chip Media Bus 76 1.5.4.2 yamt * SMMU System mmu. No idea as how its programmed (or not) 77 1.5.4.2 yamt * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus 78 1.5.4.2 yamt * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, 79 1.5.4.2 yamt * SECKEY, TZPC 80 1.5.4.2 yamt */ 81 1.5.4.2 yamt 82 1.5.4.2 yamt /* 83 1.5.4.2 yamt * Common to Exynos4 and Exynos 5 84 1.5.4.2 yamt * */ 85 1.5.4.2 yamt #define EXYNOS_CORE_PBASE 0x10000000 /* SFR */ 86 1.5.4.2 yamt #define EXYNOS_CORE_SIZE 0x10000000 87 1.5.4.2 yamt 88 1.5.4.2 yamt 89 1.5.4.2 yamt #define EXYNOS_CHIPID_OFFSET 0x00000000 90 1.5.4.2 yamt #define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0) 91 1.5.4.2 yamt #define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4) 92 1.5.4.2 yamt 93 1.5.4.2 yamt #define EXYNOS_PACKAGE_ID_2_GIG 0x06030058 94 1.5.4.2 yamt 95 1.5.4.2 yamt /* standard block size for offsets defined below */ 96 1.5.4.2 yamt #define EXYNOS_BLOCK_SIZE 0x00010000 97 1.5.4.2 yamt 98 1.5.4.2 yamt 99 1.5.4.2 yamt #if defined(EXYNOS5) 100 1.5.4.2 yamt #include <arm/samsung/exynos5_reg.h> 101 1.5.4.2 yamt #endif 102 1.5.4.2 yamt #if defined(EXYNOS4) 103 1.5.4.2 yamt #include <arm/samsung/exynos4_reg.h> 104 1.5.4.2 yamt #endif 105 1.5.4.2 yamt 106 1.5.4.2 yamt 107 1.5.4.2 yamt /* standard frequency settings */ 108 1.5.4.2 yamt #define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */ 109 1.5.4.2 yamt #define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */ 110 1.5.4.2 yamt 111 1.5.4.2 yamt #define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */ 112 1.5.4.2 yamt #define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */ 113 1.5.4.2 yamt 114 1.5.4.2 yamt 115 1.5.4.2 yamt /* Watchdog register definitions */ 116 1.5.4.2 yamt #define EXYNOS_WDT_WTCON 0x0000 117 1.5.4.2 yamt #define WTCON_PRESCALER __BITS(15,8) 118 1.5.4.2 yamt #define WTCON_ENABLE __BIT(5) 119 1.5.4.2 yamt #define WTCON_CLOCK_SELECT __BITS(4,3) 120 1.5.4.2 yamt #define WTCON_CLOCK_SELECT_16 __SHIFTIN(0, WTCON_CLOCK_SELECT) 121 1.5.4.2 yamt #define WTCON_CLOCK_SELECT_32 __SHIFTIN(1, WTCON_CLOCK_SELECT) 122 1.5.4.2 yamt #define WTCON_CLOCK_SELECT_64 __SHIFTIN(2, WTCON_CLOCK_SELECT) 123 1.5.4.2 yamt #define WTCON_CLOCK_SELECT_128 __SHIFTIN(3, WTCON_CLOCK_SELECT) 124 1.5.4.2 yamt #define WTCON_INT_ENABLE __BIT(2) 125 1.5.4.2 yamt #define WTCON_RESET_ENABLE __BIT(0) 126 1.5.4.2 yamt #define EXYNOS_WDT_WTDAT 0x0004 127 1.5.4.2 yamt #define WTDAT_RELOAD __BITS(15,0) 128 1.5.4.2 yamt #define EXYNOS_WDT_WTCNT 0x0008 129 1.5.4.2 yamt #define WTCNT_COUNT __BITS(15,0) 130 1.5.4.2 yamt #define EXYNOS_WDT_WTCLRINT 0x000C 131 1.5.4.2 yamt 132 1.5.4.2 yamt 133 1.5.4.2 yamt /* GPIO register definitions */ 134 1.5.4.2 yamt #define EXYNOS_GPIO_GRP_SIZE 0x20 135 1.5.4.2 yamt #define EXYNOS_GPIO_CON 0x00 136 1.5.4.2 yamt #define EXYNOS_GPIO_DAT 0x04 137 1.5.4.2 yamt #define EXYNOS_GPIO_PUD 0x08 138 1.5.4.2 yamt #define EXYNOS_GPIO_DRV 0x0C 139 1.5.4.2 yamt #define EXYNOS_GPIO_CONPWD 0x10 140 1.5.4.2 yamt #define EXYNOS_GPIO_PUDPWD 0x14 141 1.5.4.2 yamt /* rest of space is not used */ 142 1.5.4.2 yamt 143 1.5.4.2 yamt #define EXYNOS_GPIO_FUNC_INPUT 0x0 144 1.5.4.2 yamt #define EXYNOS_GPIO_FUNC_OUTPUT 0x1 145 1.5.4.2 yamt /* intermediate values are devices, defintions dependent on pin */ 146 1.5.4.2 yamt #define EXYNOS_GPIO_FUNC_EXTINT 0xF 147 1.5.4.2 yamt 148 1.5.4.2 yamt #define EXYNOS_GPIO_PIN_FLOAT 0 149 1.5.4.2 yamt #define EXYNOS_GPIO_PIN_PULL_DOWN 1 150 1.5.4.2 yamt #define EXYNOS_GPIO_PIN_PULL_UP 3 151 1.5.4.2 yamt 152 1.5.4.2 yamt 153 1.5.4.2 yamt #endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */ 154
Indexes created Sat Nov 01 05:10:12 GMT 2025