exynos_reg.h revision 1.7.2.2
1 1.7.2.2 tls /* $NetBSD */ 2 1.7.2.2 tls /*- 3 1.7.2.2 tls * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 1.7.2.2 tls * All rights reserved. 5 1.7.2.2 tls * 6 1.7.2.2 tls * This code is derived from software contributed to The NetBSD Foundation 7 1.7.2.2 tls * by Reinoud Zandijk. 8 1.7.2.2 tls * 9 1.7.2.2 tls * Redistribution and use in source and binary forms, with or without 10 1.7.2.2 tls * modification, are permitted provided that the following conditions 11 1.7.2.2 tls * are met: 12 1.7.2.2 tls * 1. Redistributions of source code must retain the above copyright 13 1.7.2.2 tls * notice, this list of conditions and the following disclaimer. 14 1.7.2.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.7.2.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.7.2.2 tls * documentation and/or other materials provided with the distribution. 17 1.7.2.2 tls * 18 1.7.2.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.7.2.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.7.2.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.7.2.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.7.2.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.7.2.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.7.2.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.7.2.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.7.2.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.7.2.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.7.2.2 tls * POSSIBILITY OF SUCH DAMAGE. 29 1.7.2.2 tls */ 30 1.7.2.2 tls 31 1.7.2.2 tls #ifndef _ARM_SAMSUNG_EXYNOS_REG_H_ 32 1.7.2.2 tls #define _ARM_SAMSUNG_EXYNOS_REG_H_ 33 1.7.2.2 tls 34 1.7.2.2 tls /* 35 1.7.2.2 tls * 36 1.7.2.2 tls * The exynos can boot from its iROM or from an external Nand memory. Since 37 1.7.2.2 tls * these are normally hardly used they are excluded from the normal register 38 1.7.2.2 tls * space here. 39 1.7.2.2 tls * 40 1.7.2.2 tls * XXX What about the audio subsystem region. Where are the docs? 41 1.7.2.2 tls * 42 1.7.2.2 tls * EXYNOS_CORE_PBASE points to the main SFR region. 43 1.7.2.2 tls * 44 1.7.2.2 tls * Notes: 45 1.7.2.2 tls * 46 1.7.2.2 tls * SFR Special Function Register 47 1.7.2.2 tls * ISP In-System Programming, like a JTAG 48 1.7.2.2 tls * ACP Accelerator Coherency Port 49 1.7.2.2 tls * SSS Security Sub System 50 1.7.2.2 tls * GIC Generic Interurrupt Controller 51 1.7.2.2 tls * PMU Power Management Unit 52 1.7.2.2 tls * DMC 2D Graphics engine 53 1.7.2.2 tls * LEFTBUS Data bus / Peripheral bus 54 1.7.2.2 tls * RIGHTBUS ,, 55 1.7.2.2 tls * G3D 3D Graphics engine 56 1.7.2.2 tls * MFC Multi-Format Codec 57 1.7.2.2 tls * LCD0 LCD display 58 1.7.2.2 tls * MCT Multi Core Timer 59 1.7.2.2 tls * CMU Clock Management Unit 60 1.7.2.2 tls * TMU Thermal Management Unit 61 1.7.2.2 tls * PPMU Pin Parametric Measurement Unit (?) 62 1.7.2.2 tls * MMU Memory Management Unit 63 1.7.2.2 tls * MCTimer ? 64 1.7.2.2 tls * WDT Watch Dog Timer 65 1.7.2.2 tls * RTC Real Time Clock 66 1.7.2.2 tls * KEYIF Keypad interface 67 1.7.2.2 tls * SECKEY ? 68 1.7.2.2 tls * TZPC TrustZone Protection Controller 69 1.7.2.2 tls * UART Universal asynchronous receiver/transmitter 70 1.7.2.2 tls * I2C Inter IC Connect 71 1.7.2.2 tls * SPI Serial Peripheral Interface Bus 72 1.7.2.2 tls * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS 73 1.7.2.2 tls * PCM Pulse-code modulation, audio stream at set fixed rate 74 1.7.2.2 tls * SPDIF Sony/Philips Digital Interface Format 75 1.7.2.2 tls * Slimbus Serial Low-power Inter-chip Media Bus 76 1.7.2.2 tls * SMMU System mmu. No idea as how its programmed (or not) 77 1.7.2.2 tls * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus 78 1.7.2.2 tls * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, 79 1.7.2.2 tls * SECKEY, TZPC 80 1.7.2.2 tls */ 81 1.7.2.2 tls 82 1.7.2.2 tls /* 83 1.7.2.2 tls * Common to Exynos4 and Exynos 5 84 1.7.2.2 tls * */ 85 1.7.2.2 tls #define EXYNOS_CORE_PBASE 0x10000000 /* SFR */ 86 1.7.2.2 tls #define EXYNOS_CORE_SIZE 0x10000000 87 1.7.2.2 tls 88 1.7.2.2 tls 89 1.7.2.2 tls #define EXYNOS_CHIPID_OFFSET 0x00000000 90 1.7.2.2 tls #define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0) 91 1.7.2.2 tls #define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4) 92 1.7.2.2 tls 93 1.7.2.2 tls #define EXYNOS_PACKAGE_ID_2_GIG 0x06030058 94 1.7.2.2 tls 95 1.7.2.2 tls /* standard block size for offsets defined below */ 96 1.7.2.2 tls #define EXYNOS_BLOCK_SIZE 0x00010000 97 1.7.2.2 tls 98 1.7.2.2 tls 99 1.7.2.2 tls #if defined(EXYNOS5) 100 1.7.2.2 tls #include <arm/samsung/exynos5_reg.h> 101 1.7.2.2 tls #endif 102 1.7.2.2 tls #if defined(EXYNOS4) 103 1.7.2.2 tls #include <arm/samsung/exynos4_reg.h> 104 1.7.2.2 tls #endif 105 1.7.2.2 tls 106 1.7.2.2 tls 107 1.7.2.2 tls /* standard frequency settings */ 108 1.7.2.2 tls #define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */ 109 1.7.2.2 tls #define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */ 110 1.7.2.2 tls 111 1.7.2.2 tls #define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */ 112 1.7.2.2 tls #define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */ 113 1.7.2.2 tls 114 1.7.2.2 tls 115 1.7.2.2 tls /* Watchdog register definitions */ 116 1.7.2.2 tls #define EXYNOS_WDT_WTCON 0x0000 117 1.7.2.2 tls #define WTCON_PRESCALER __BITS(15,8) 118 1.7.2.2 tls #define WTCON_ENABLE __BIT(5) 119 1.7.2.2 tls #define WTCON_CLOCK_SELECT __BITS(4,3) 120 1.7.2.2 tls #define WTCON_CLOCK_SELECT_16 __SHIFTIN(0, WTCON_CLOCK_SELECT) 121 1.7.2.2 tls #define WTCON_CLOCK_SELECT_32 __SHIFTIN(1, WTCON_CLOCK_SELECT) 122 1.7.2.2 tls #define WTCON_CLOCK_SELECT_64 __SHIFTIN(2, WTCON_CLOCK_SELECT) 123 1.7.2.2 tls #define WTCON_CLOCK_SELECT_128 __SHIFTIN(3, WTCON_CLOCK_SELECT) 124 1.7.2.2 tls #define WTCON_INT_ENABLE __BIT(2) 125 1.7.2.2 tls #define WTCON_RESET_ENABLE __BIT(0) 126 1.7.2.2 tls #define EXYNOS_WDT_WTDAT 0x0004 127 1.7.2.2 tls #define WTDAT_RELOAD __BITS(15,0) 128 1.7.2.2 tls #define EXYNOS_WDT_WTCNT 0x0008 129 1.7.2.2 tls #define WTCNT_COUNT __BITS(15,0) 130 1.7.2.2 tls #define EXYNOS_WDT_WTCLRINT 0x000C 131 1.7.2.2 tls 132 1.7.2.2 tls 133 1.7.2.2 tls /* GPIO register definitions */ 134 1.7.2.2 tls #define EXYNOS_GPIO_GRP_SIZE 0x20 135 1.7.2.2 tls #define EXYNOS_GPIO_CON 0x00 136 1.7.2.2 tls #define EXYNOS_GPIO_DAT 0x04 137 1.7.2.2 tls #define EXYNOS_GPIO_PUD 0x08 138 1.7.2.2 tls #define EXYNOS_GPIO_DRV 0x0C 139 1.7.2.2 tls #define EXYNOS_GPIO_CONPWD 0x10 140 1.7.2.2 tls #define EXYNOS_GPIO_PUDPWD 0x14 141 1.7.2.2 tls /* rest of space is not used */ 142 1.7.2.2 tls 143 1.7.2.2 tls #define EXYNOS_GPIO_FUNC_INPUT 0x0 144 1.7.2.2 tls #define EXYNOS_GPIO_FUNC_OUTPUT 0x1 145 1.7.2.2 tls /* intermediate values are devices, definitions dependent on pin */ 146 1.7.2.2 tls #define EXYNOS_GPIO_FUNC_EXTINT 0xF 147 1.7.2.2 tls 148 1.7.2.2 tls #define EXYNOS_GPIO_PIN_FLOAT 0 149 1.7.2.2 tls #define EXYNOS_GPIO_PIN_PULL_DOWN 1 150 1.7.2.2 tls #define EXYNOS_GPIO_PIN_PULL_UP 3 151 1.7.2.2 tls 152 1.7.2.2 tls 153 1.7.2.2 tls /* used PMU registers */ 154 1.7.2.2 tls /* Exynos 4210 or Exynos 5 */ 155 1.7.2.2 tls #define EXYNOS_PMU_USBDEV_PHY_CTRL 0x704 156 1.7.2.2 tls #define EXYNOS_PMU_USBHOST_PHY_CTRL 0x708 157 1.7.2.2 tls /* Exynos 4x12 */ 158 1.7.2.2 tls #define EXYNOS_PMU_USB_PHY_CTRL 0x704 159 1.7.2.2 tls #define EXYNOS_PMU_USB_HSIC_1_PHY_CTRL 0x708 160 1.7.2.2 tls #define EXYNOS_PMU_USB_HSIC_2_PHY_CTRL 0x70C 161 1.7.2.2 tls 162 1.7.2.2 tls #define PMU_PHY_ENABLE (1<< 0) 163 1.7.2.2 tls #define PMU_PHY_DISABLE (0) 164 1.7.2.2 tls 165 1.7.2.2 tls 166 1.7.2.2 tls /* used SYSREG registers */ 167 1.7.2.2 tls #define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230 168 1.7.2.2 tls 169 1.7.2.2 tls 170 1.7.2.2 tls /* used USB PHY registers */ 171 1.7.2.2 tls #define USB_PHYPWR 0x00 172 1.7.2.2 tls #define PHYPWR_FORCE_SUSPEND __BIT(1) 173 1.7.2.2 tls #define PHYPWR_ANALOG_POWERDOWN __BIT(3) 174 1.7.2.2 tls #define PHYPWR_OTG_DISABLE __BIT(4) 175 1.7.2.2 tls #define PHYPWR_SLEEP_PHY0 __BIT(5) 176 1.7.2.2 tls #define PHYPWR_NORMAL_MASK 0x19 177 1.7.2.2 tls #define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1) 178 1.7.2.2 tls #define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3) 179 1.7.2.2 tls #define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3) 180 1.7.2.2 tls #define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3) 181 1.7.2.2 tls #define USB_PHYCLK 0x04 182 1.7.2.2 tls #define USB_RSTCON 0x08 183 1.7.2.2 tls #define RSTCON_SWRST __BIT(0) 184 1.7.2.2 tls #define RSTCON_HLINK_RWRST __BIT(1) 185 1.7.2.2 tls #define RSTCON_DEVPHYLINK_SWRST __BIT(2) 186 1.7.2.2 tls #define RSTCON_DEVPHY_SWRST __BITS(0,3) 187 1.7.2.2 tls #define RSTCON_HOSTPHY_SWRST __BITS(3,4) 188 1.7.2.2 tls #define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4) 189 1.7.2.2 tls 190 1.7.2.2 tls #endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */ 191
Indexes created Sat Nov 01 21:09:44 GMT 2025