exynos_reg.h revision 1.8
1 /* $NetBSD */ 2 /*- 3 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Reinoud Zandijk. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM_SAMSUNG_EXYNOS_REG_H_ 32 #define _ARM_SAMSUNG_EXYNOS_REG_H_ 33 34 /* 35 * 36 * The exynos can boot from its iROM or from an external Nand memory. Since 37 * these are normally hardly used they are excluded from the normal register 38 * space here. 39 * 40 * XXX What about the audio subsystem region. Where are the docs? 41 * 42 * EXYNOS_CORE_PBASE points to the main SFR region. 43 * 44 * Notes: 45 * 46 * SFR Special Function Register 47 * ISP In-System Programming, like a JTAG 48 * ACP Accelerator Coherency Port 49 * SSS Security Sub System 50 * GIC Generic Interurrupt Controller 51 * PMU Power Management Unit 52 * DMC 2D Graphics engine 53 * LEFTBUS Data bus / Peripheral bus 54 * RIGHTBUS ,, 55 * G3D 3D Graphics engine 56 * MFC Multi-Format Codec 57 * LCD0 LCD display 58 * MCT Multi Core Timer 59 * CMU Clock Management Unit 60 * TMU Thermal Management Unit 61 * PPMU Pin Parametric Measurement Unit (?) 62 * MMU Memory Management Unit 63 * MCTimer ? 64 * WDT Watch Dog Timer 65 * RTC Real Time Clock 66 * KEYIF Keypad interface 67 * SECKEY ? 68 * TZPC TrustZone Protection Controller 69 * UART Universal asynchronous receiver/transmitter 70 * I2C Inter IC Connect 71 * SPI Serial Peripheral Interface Bus 72 * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS 73 * PCM Pulse-code modulation, audio stream at set fixed rate 74 * SPDIF Sony/Philips Digital Interface Format 75 * Slimbus Serial Low-power Inter-chip Media Bus 76 * SMMU System mmu. No idea as how its programmed (or not) 77 * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus 78 * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, 79 * SECKEY, TZPC 80 */ 81 82 /* 83 * Common to Exynos4 and Exynos 5 84 * */ 85 #define EXYNOS_CORE_PBASE 0x10000000 /* SFR */ 86 #define EXYNOS_CORE_SIZE 0x10000000 87 88 89 #define EXYNOS_CHIPID_OFFSET 0x00000000 90 #define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0) 91 #define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4) 92 93 #define EXYNOS_PACKAGE_ID_2_GIG 0x06030058 94 95 /* standard block size for offsets defined below */ 96 #define EXYNOS_BLOCK_SIZE 0x00010000 97 98 99 #if defined(EXYNOS5) 100 #include <arm/samsung/exynos5_reg.h> 101 #endif 102 #if defined(EXYNOS4) 103 #include <arm/samsung/exynos4_reg.h> 104 #endif 105 106 107 /* standard frequency settings */ 108 #define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */ 109 #define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */ 110 111 #define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */ 112 #define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */ 113 114 115 /* PLLs */ 116 #define PLL_LOCK_OFFSET 0x000 117 #define PLL_CON0_OFFSET 0x100 118 #define PLL_CON1_OFFSET 0x104 119 120 #define PLL_CON0_ENABLE __BIT(31) 121 #define PLL_CON0_LOCKED __BIT(29) /* has the PLL locked on */ 122 #define PLL_CON0_M __BITS(16,25) /* PLL M divide value */ 123 #define PLL_CON0_P __BITS( 8,13) /* PLL P divide value */ 124 #define PLL_CON0_S __BITS( 0, 2) /* PLL S divide value */ 125 126 #define PLL_PMS2FREQ(F, M, P, S) (((M)*(F))/((P)*(1<<(S)))) 127 #define PLL_FREQ(f, v) PLL_PMS2FREQ( \ 128 (f),\ 129 __SHIFTOUT((v), PLL_CON0_M),\ 130 __SHIFTOUT((v), PLL_CON0_P),\ 131 __SHIFTOUT((v), PLL_CON0_S)) 132 133 134 /* Watchdog register definitions */ 135 #define EXYNOS_WDT_WTCON 0x0000 136 #define WTCON_PRESCALER __BITS(15,8) 137 #define WTCON_ENABLE __BIT(5) 138 #define WTCON_CLOCK_SELECT __BITS(4,3) 139 #define WTCON_CLOCK_SELECT_16 __SHIFTIN(0, WTCON_CLOCK_SELECT) 140 #define WTCON_CLOCK_SELECT_32 __SHIFTIN(1, WTCON_CLOCK_SELECT) 141 #define WTCON_CLOCK_SELECT_64 __SHIFTIN(2, WTCON_CLOCK_SELECT) 142 #define WTCON_CLOCK_SELECT_128 __SHIFTIN(3, WTCON_CLOCK_SELECT) 143 #define WTCON_INT_ENABLE __BIT(2) 144 #define WTCON_RESET_ENABLE __BIT(0) 145 #define EXYNOS_WDT_WTDAT 0x0004 146 #define WTDAT_RELOAD __BITS(15,0) 147 #define EXYNOS_WDT_WTCNT 0x0008 148 #define WTCNT_COUNT __BITS(15,0) 149 #define EXYNOS_WDT_WTCLRINT 0x000C 150 151 152 /* GPIO register definitions */ 153 #define EXYNOS_GPIO_GRP_SIZE 0x20 154 #define EXYNOS_GPIO_CON 0x00 155 #define EXYNOS_GPIO_DAT 0x04 156 #define EXYNOS_GPIO_PUD 0x08 157 #define EXYNOS_GPIO_DRV 0x0C 158 #define EXYNOS_GPIO_CONPWD 0x10 159 #define EXYNOS_GPIO_PUDPWD 0x14 160 /* rest of space is not used */ 161 162 #define EXYNOS_GPIO_FUNC_INPUT 0x0 163 #define EXYNOS_GPIO_FUNC_OUTPUT 0x1 164 /* intermediate values are devices, definitions dependent on pin */ 165 #define EXYNOS_GPIO_FUNC_EXTINT 0xF 166 167 #define EXYNOS_GPIO_PIN_FLOAT 0 168 #define EXYNOS_GPIO_PIN_PULL_DOWN 1 169 #define EXYNOS_GPIO_PIN_PULL_UP 3 170 171 172 /* used PMU registers */ 173 /* Exynos 4210 or Exynos 5 */ 174 #define EXYNOS_PMU_USBDEV_PHY_CTRL 0x704 175 #define EXYNOS_PMU_USBHOST_PHY_CTRL 0x708 176 /* Exynos 4x12 */ 177 #define EXYNOS_PMU_USB_PHY_CTRL 0x704 178 #define EXYNOS_PMU_USB_HSIC_1_PHY_CTRL 0x708 179 #define EXYNOS_PMU_USB_HSIC_2_PHY_CTRL 0x70C 180 181 #define PMU_PHY_ENABLE (1<< 0) 182 #define PMU_PHY_DISABLE (0) 183 184 185 /* used SYSREG registers */ 186 #define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230 187 188 189 /* used USB PHY registers */ 190 #define USB_PHYPWR 0x00 191 #define PHYPWR_FORCE_SUSPEND __BIT(1) 192 #define PHYPWR_ANALOG_POWERDOWN __BIT(3) 193 #define PHYPWR_OTG_DISABLE __BIT(4) 194 #define PHYPWR_SLEEP_PHY0 __BIT(5) 195 #define PHYPWR_NORMAL_MASK 0x19 196 #define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1) 197 #define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3) 198 #define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3) 199 #define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3) 200 #define USB_PHYCLK 0x04 201 #define USB_RSTCON 0x08 202 #define RSTCON_SWRST __BIT(0) 203 #define RSTCON_HLINK_RWRST __BIT(1) 204 #define RSTCON_DEVPHYLINK_SWRST __BIT(2) 205 #define RSTCON_DEVPHY_SWRST __BITS(0,3) 206 #define RSTCON_HOSTPHY_SWRST __BITS(3,4) 207 #define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4) 208 209 #endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */ 210
Indexes created Fri Oct 03 02:09:57 GMT 2025