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exynos_soc.c revision 1.1 
      1 /*	$NetBSD: exynos_soc.c,v 1.1 2014/04/13 02:26:26 matt Exp $	*/
      2 /*-
      3  * Copyright (c) 2014 The NetBSD Foundation, Inc.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by Reinoud Zandijk.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #include "opt_exynos.h"
     32 
     33 #define	_ARM32_BUS_DMA_PRIVATE
     34 
     35 #include <sys/cdefs.h>
     36 __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.1 2014/04/13 02:26:26 matt Exp $");
     37 
     38 #include <sys/param.h>
     39 #include <sys/bus.h>
     40 #include <sys/cpu.h>
     41 #include <sys/device.h>
     42 
     43 #include <prop/proplib.h>
     44 
     45 #include <net/if.h>
     46 #include <net/if_ether.h>
     47 
     48 #include <arm/locore.h>
     49 
     50 #include <arm/mainbus/mainbus.h>
     51 #include <arm/cortex/mpcore_var.h>
     52 #ifdef ARM_TRUSTZONE_FIRMWARE
     53 #include <arm/trustzone/firmware.h>
     54 #endif
     55 
     56 #include <arm/samsung/exynos_reg.h>
     57 #include <arm/samsung/exynos_var.h>
     58 #include <arm/samsung/smc.h>
     59 
     60 #include <arm/cortex/pl310_var.h>
     61 #include <arm/cortex/pl310_reg.h>
     62 
     63 /* XXXNH */
     64 #include <evbarm/odroid/platform.h>
     65 
     66 bus_space_handle_t exynos_core_bsh;
     67 
     68 /* these variables are retrieved in start.S and stored in .data */
     69 uint32_t  exynos_soc_id = 0;
     70 uint32_t  exynos_pop_id = 0;
     71 
     72 
     73 /*
     74  * the early serial console
     75  */
     76 #ifdef EXYNOS_CONSOLE_EARLY
     77 
     78 #include "opt_sscom.h"
     79 #include <arm/samsung/sscom_reg.h>
     80 #include <arm/samsung/sscom_var.h>
     81 #include <dev/cons.h>
     82 
     83 static volatile uint8_t *uart_base;
     84 
     85 #define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a))))
     86 
     87 static int
     88 exynos_cngetc(dev_t dv)
     89 {
     90         if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0)
     91 		return -1;
     92 
     93 	return CON_REG(SSCOM_URXH);
     94 }
     95 
     96 static void
     97 exynos_cnputc(dev_t dv, int c)
     98 {
     99 	int timo = 150000;
    100 
    101 	while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0);
    102 
    103 	CON_REG(SSCOM_UTXH) = c & 0xff;
    104 }
    105 
    106 static struct consdev exynos_earlycons = {
    107 	.cn_putc = exynos_cnputc,
    108 	.cn_getc = exynos_cngetc,
    109 	.cn_pollc = nullcnpollc,
    110 };
    111 #endif /* EXYNOS_CONSOLE_EARLY */
    112 
    113 
    114 #ifdef ARM_TRUSTZONE_FIRMWARE
    115 static int
    116 exynos_do_idle(void)
    117 {
    118         exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
    119 
    120 	return 0;
    121 }
    122 
    123 
    124 static int
    125 exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr)
    126 {
    127 #if 0
    128         void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
    129 
    130         if (!soc_is_exynos5420())
    131                 boot_reg += 4 * cpu;
    132 
    133         writel_relaxed(boot_addr, boot_reg);
    134         return 0;
    135 #endif
    136 	return 0;
    137 }
    138 
    139 
    140 static int
    141 exynos_cpu_boot(int cpu)
    142 {
    143 	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
    144 
    145 	return 0;
    146 }
    147 
    148 
    149 /*
    150  * The latency values used below are `magic' and probably chosen empiricaly.
    151  * For the 4210 variant the data latency is lower, a 0x110. This is currently
    152  * not enforced.
    153  *
    154  * The prefetch values are also different for the revision 0 of the
    155  * Exynos4412, but why?
    156  */
    157 
    158 static int
    159 exynos_l2cc_init(void)
    160 {
    161 	const uint32_t tag_latency  = 0x110;
    162 	const uint32_t data_latency = IS_EXYNOS4410 ? 0x110 : 0x120;
    163 	const uint32_t prefetch4412   = /* 0111 0001 0000 0000 0000 0000 0000 0111 */
    164 				PREFETCHCTL_DBLLINEF_EN  |
    165 				PREFETCHCTL_INSTRPREF_EN |
    166 				PREFETCHCTL_DATAPREF_EN  |
    167 				PREFETCHCTL_PREF_DROP_EN |
    168 				PREFETCHCTL_PREFETCH_OFFSET_7;
    169 	const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */
    170 				PREFETCHCTL_INSTRPREF_EN |
    171 				PREFETCHCTL_DATAPREF_EN  |
    172 				PREFETCHCTL_PREFETCH_OFFSET_7;
    173 	const uint32_t aux_val      =    /* 0111 1100 0100 0111 0000 0000 0000 0001 */
    174 				AUXCTL_EARLY_BRESP_EN |
    175 				AUXCTL_I_PREFETCH     |
    176 				AUXCTL_D_PREFETCH     |
    177 				AUXCTL_NS_INT_ACC_CTL |
    178 				AUXCTL_NS_INT_LOCK_EN |
    179 				AUXCTL_SHARED_ATT_OVR |
    180 				AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */
    181 				AUXCTL_FULL_LINE_WR0;
    182 	const uint32_t aux_keepmask =    /* 1100 0010 0000 0000 1111 1111 1111 1111  */
    183 				AUXCTL_RSVD31         |
    184 				AUXCTL_EARLY_BRESP_EN |
    185 				AUXCTL_CACHE_REPL_RR  |
    186 
    187 				AUXCTL_SH_ATTR_INV_ENA|
    188 				AUXCTL_EXCL_CACHE_CFG |
    189 				AUXCTL_ST_BUF_DEV_LIM_EN |
    190 				AUXCTL_HIPRO_SO_DEV_EN |
    191 				AUXCTL_FULL_LINE_WR0  |
    192 				0xffff;
    193 	uint32_t prefetch;
    194 
    195 	/* check the bitmaps are the same as the linux implementation uses */
    196 	KASSERT(prefetch4412    == 0x71000007);
    197 	KASSERT(prefetch4412_r0 == 0x30000007);
    198 	KASSERT(aux_val         == 0x7C470001);
    199 	KASSERT(aux_keepmask    == 0xC200FFFF);
    200 
    201 	if (IS_EXYNOS4412_R0)
    202 		prefetch = prefetch4412_r0;
    203 	else
    204 		prefetch = prefetch4412;	/* newer than >= r1_0 */
    205 	;
    206 
    207 	exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch);
    208 	exynos_smc(SMC_CMD_L2X0SETUP2,
    209 		POWERCTL_DYNCLKGATE | POWERCTL_STANDBY,
    210 		aux_val, aux_keepmask);
    211 	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
    212 	exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
    213 
    214 	return 0;
    215 }
    216 
    217 static struct trustzone_firmware_handlers exynos_firmware_handlers = {
    218 	.do_idle           = exynos_do_idle,
    219 	.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
    220 	.cpu_boot          = exynos_cpu_boot,
    221 	.l2cc_init         = exynos_l2cc_init
    222 };
    223 #endif /* ARM_TRUSTZONE_FIRMWARE */
    224 
    225 void
    226 exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
    227 {
    228 // 	int error;
    229 
    230 	/* set up early console so we can use printf() and friends */
    231 #ifdef EXYNOS_CONSOLE_EARLY
    232 	uart_base = (volatile uint8_t *) uartbase;
    233 	cn_tab = &exynos_earlycons;
    234 	printf("Exynos early console operational\n\n");
    235 #endif
    236 #if 0
    237 	/* map in the exynos io registers */
    238 	error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE,
    239 	    0x04000000 /*EXYNOS_CORE_SIZE*/, 0, &exynos_core_bsh);
    240 	if (error)
    241 		panic("%s: failed to map in Exynos io registers: %d",
    242 			__func__, error);
    243 	KASSERT(exynos_core_bsh == iobase);
    244 #endif
    245 #ifdef ARM_TRUSTZONE_FIRMWARE
    246 	/* setup trustzone handlers */
    247 	trustzone_firmware_handlers = &exynos_firmware_handlers;
    248 #endif
    249 }
    250 
    251 
    252 void
    253 exynos_device_register(device_t self, void *aux)
    254 {
    255 	if (device_is_a(self, "armperiph")
    256 	    && device_is_a(device_parent(self), "mainbus")) {
    257 		/*
    258 		 * XXX KLUDGE ALERT XXX
    259 		 * The iot mainbus supplies is completely wrong since it scales
    260 		 * addresses by 2.  The simpliest remedy is to replace with our
    261 		 * bus space used for the armcore regisers (which armperiph uses).
    262 		 */
    263 		struct mainbus_attach_args * const mb = aux;
    264 		mb->mb_iot = &exynos_bs_tag;
    265 		return;
    266 	}
    267 	if (device_is_a(self, "armgic")
    268 	    && device_is_a(device_parent(self), "armperiph")) {
    269 		/*
    270 		 * The Exynos4420 armgic is located at a different location!
    271 		 */
    272 
    273 		extern uint32_t exynos_soc_id;
    274 		switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) {
    275 #if defined(EXYNOS5)
    276 		case 0xe5410:
    277 #if 0
    278 			mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET;
    279 			mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET;
    280 #endif
    281 			break;
    282 #endif
    283 #if defined(EXYNOS4)
    284 		case 0xe4410:
    285 		case 0xe4412: {
    286 			struct mpcore_attach_args * const mpcaa = aux;
    287 			mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE;
    288 			mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET;
    289 			mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET;
    290 			break;
    291 		}
    292 #endif
    293 		default:
    294 			panic("%s: unknown SoC product id %#x", __func__,
    295 			    (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id));
    296 		}
    297 		return;
    298 	}
    299 #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
    300 	if (device_is_a(self, "armgtmr")) {
    301 		/*
    302 		 * The frequency of the generic timer is the reference
    303 		 * frequency.
    304 		 */
    305 		prop_dictionary_set_uint32(device_properties(self),
    306 		    "frequency", 24000000);
    307 		return;
    308 	}
    309 #endif
    310 
    311 	exyo_device_register(self, aux);
    312 }
    313 
    314