exynos_soc.c revision 1.13
1 /* $NetBSD: exynos_soc.c,v 1.13 2014/06/11 05:43:39 matt Exp $ */ 2 /*- 3 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Reinoud Zandijk. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_exynos.h" 32 33 #define _ARM32_BUS_DMA_PRIVATE 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.13 2014/06/11 05:43:39 matt Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 43 #include <prop/proplib.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 48 #include <arm/locore.h> 49 50 #include <arm/mainbus/mainbus.h> 51 #include <arm/cortex/mpcore_var.h> 52 53 #include <arm/samsung/exynos_reg.h> 54 #include <arm/samsung/exynos_var.h> 55 #include <arm/samsung/smc.h> 56 57 #include <arm/cortex/pl310_var.h> 58 #include <arm/cortex/pl310_reg.h> 59 60 /* XXXNH */ 61 #include <evbarm/odroid/platform.h> 62 63 bus_space_handle_t exynos_core_bsh; 64 bus_space_handle_t exynos_audiocore_bsh; 65 66 /* these variables are retrieved in start.S and stored in .data */ 67 uint32_t exynos_soc_id = 0; 68 uint32_t exynos_pop_id = 0; 69 70 71 /* 72 * the early serial console 73 */ 74 #ifdef EXYNOS_CONSOLE_EARLY 75 76 #include "opt_sscom.h" 77 #include <arm/samsung/sscom_reg.h> 78 #include <arm/samsung/sscom_var.h> 79 #include <dev/cons.h> 80 81 static volatile uint8_t *uart_base; 82 83 #define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a)))) 84 85 static int 86 exynos_cngetc(dev_t dv) 87 { 88 if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0) 89 return -1; 90 91 return CON_REG(SSCOM_URXH); 92 } 93 94 static void 95 exynos_cnputc(dev_t dv, int c) 96 { 97 int timo = 150000; 98 99 while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0); 100 101 CON_REG(SSCOM_UTXH) = c & 0xff; 102 } 103 104 static struct consdev exynos_earlycons = { 105 .cn_putc = exynos_cnputc, 106 .cn_getc = exynos_cngetc, 107 .cn_pollc = nullcnpollc, 108 }; 109 #endif /* EXYNOS_CONSOLE_EARLY */ 110 111 112 #ifdef ARM_TRUSTZONE_FIRMWARE 113 int 114 exynos_do_idle(void) 115 { 116 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 117 118 return 0; 119 } 120 121 122 int 123 exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr) 124 { 125 /* XXX we need to map in iRAM space for this XXX */ 126 return 0; 127 } 128 129 130 int 131 exynos_cpu_boot(int cpu) 132 { 133 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 134 135 return 0; 136 } 137 138 139 /* 140 * The latency values used below are `magic' and probably chosen empiricaly. 141 * For the 4210 variant the data latency is lower, a 0x110. This is currently 142 * not enforced. 143 * 144 * The prefetch values are also different for the revision 0 of the 145 * Exynos4412, but why? 146 */ 147 148 int 149 exynos_l2cc_init(void) 150 { 151 const uint32_t tag_latency = 0x110; 152 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120; 153 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */ 154 PREFETCHCTL_DBLLINEF_EN | 155 PREFETCHCTL_INSTRPREF_EN | 156 PREFETCHCTL_DATAPREF_EN | 157 PREFETCHCTL_PREF_DROP_EN | 158 PREFETCHCTL_PREFETCH_OFFSET_7; 159 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */ 160 PREFETCHCTL_INSTRPREF_EN | 161 PREFETCHCTL_DATAPREF_EN | 162 PREFETCHCTL_PREFETCH_OFFSET_7; 163 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */ 164 AUXCTL_EARLY_BRESP_EN | 165 AUXCTL_I_PREFETCH | 166 AUXCTL_D_PREFETCH | 167 AUXCTL_NS_INT_ACC_CTL | 168 AUXCTL_NS_INT_LOCK_EN | 169 AUXCTL_SHARED_ATT_OVR | 170 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */ 171 AUXCTL_FULL_LINE_WR0; 172 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */ 173 AUXCTL_RSVD31 | 174 AUXCTL_EARLY_BRESP_EN | 175 AUXCTL_CACHE_REPL_RR | 176 177 AUXCTL_SH_ATTR_INV_ENA| 178 AUXCTL_EXCL_CACHE_CFG | 179 AUXCTL_ST_BUF_DEV_LIM_EN | 180 AUXCTL_HIPRO_SO_DEV_EN | 181 AUXCTL_FULL_LINE_WR0 | 182 0xffff; 183 uint32_t prefetch; 184 185 /* check the bitmaps are the same as the linux implementation uses */ 186 KASSERT(prefetch4412 == 0x71000007); 187 KASSERT(prefetch4412_r0 == 0x30000007); 188 KASSERT(aux_val == 0x7C470001); 189 KASSERT(aux_keepmask == 0xC200FFFF); 190 191 if (IS_EXYNOS4412_R0_P()) 192 prefetch = prefetch4412_r0; 193 else 194 prefetch = prefetch4412; /* newer than >= r1_0 */ 195 ; 196 197 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch); 198 exynos_smc(SMC_CMD_L2X0SETUP2, 199 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY, 200 aux_val, aux_keepmask); 201 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 202 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); 203 204 return 0; 205 } 206 #endif /* ARM_TRUSTZONE_FIRMWARE */ 207 208 209 void 210 exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) 211 { 212 int error; 213 size_t core_size, audiocore_size; 214 size_t audiocore_pbase, audiocore_vbase; 215 216 #ifdef EXYNOS4 217 if (IS_EXYNOS4_P()) { 218 core_size = EXYNOS4_CORE_SIZE; 219 audiocore_size = EXYNOS4_AUDIOCORE_SIZE; 220 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; 221 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; 222 } 223 #endif 224 225 #ifdef EXYNOS5 226 if (IS_EXYNOS5_P()) { 227 core_size = EXYNOS5_CORE_SIZE; 228 audiocore_size = EXYNOS5_AUDIOCORE_SIZE; 229 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; 230 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; 231 } 232 #endif 233 234 /* set up early console so we can use printf() and friends */ 235 #ifdef EXYNOS_CONSOLE_EARLY 236 uart_base = (volatile uint8_t *) uartbase; 237 cn_tab = &exynos_earlycons; 238 printf("Exynos early console operational\n\n"); 239 #endif 240 /* map in the exynos io registers */ 241 error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE, 242 core_size, 0, &exynos_core_bsh); 243 if (error) 244 panic("%s: failed to map in Exynos SFR registers: %d", 245 __func__, error); 246 KASSERT(exynos_core_bsh == iobase); 247 248 error = bus_space_map(&exynos_bs_tag, audiocore_pbase, 249 audiocore_size, 0, &exynos_audiocore_bsh); 250 if (error) 251 panic("%s: failed to map in Exynos audio SFR registers: %d", 252 __func__, error); 253 KASSERT(exynos_audiocore_bsh == audiocore_vbase); 254 255 /* init bus dma tags */ 256 exynos_dma_bootstrap(physmem * PAGE_SIZE); 257 258 /* gpio bootstrapping delayed */ 259 } 260 261 262 void 263 exynos_device_register(device_t self, void *aux) 264 { 265 if (device_is_a(self, "armperiph") 266 && device_is_a(device_parent(self), "mainbus")) { 267 /* 268 * XXX KLUDGE ALERT XXX 269 * The iot mainbus supplies is completely wrong since it scales 270 * addresses by 2. The simpliest remedy is to replace with our 271 * bus space used for the armcore regisers (which armperiph uses). 272 */ 273 struct mainbus_attach_args * const mb = aux; 274 mb->mb_iot = &exynos_bs_tag; 275 return; 276 } 277 if (device_is_a(self, "armgic") 278 && device_is_a(device_parent(self), "armperiph")) { 279 /* 280 * The Exynos4420 armgic is located at a different location! 281 */ 282 283 extern uint32_t exynos_soc_id; 284 285 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { 286 #if defined(EXYNOS5) 287 case 0xe5410: 288 /* offsets not changed on matt's request */ 289 #if 0 290 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 291 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 292 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 293 #endif 294 break; 295 #endif 296 #if defined(EXYNOS4) 297 case 0xe4410: 298 case 0xe4412: { 299 struct mpcore_attach_args * const mpcaa = aux; 300 301 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 302 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; 303 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; 304 break; 305 } 306 #endif 307 default: 308 panic("%s: unknown SoC product id %#x", __func__, 309 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); 310 } 311 return; 312 } 313 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { 314 #ifdef EXONYS5 315 /* 316 * The global timer is dependent on the MCT running. 317 */ 318 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; 319 uint32_t v = bus_space_read_4(&exynos_bs_tag, exynos_core_bsh, 320 p); 321 v |= G_TCON_START; 322 bus_space_write_4(&exynos_bs_tag, exynos_core_bsh, o, v); 323 #endif 324 /* 325 * The frequencies of the timers are the reference 326 * frequency. 327 */ 328 prop_dictionary_set_uint32(device_properties(self), 329 "frequency", EXYNOS_F_IN_FREQ); 330 return; 331 } 332 333 exyo_device_register(self, aux); 334 } 335 336 337 void 338 exynos_device_register_post_config(device_t self, void *aux) 339 { 340 exyo_device_register_post_config(self, aux); 341 } 342 343
Indexes created Tue Sep 30 11:09:46 GMT 2025