exynos_soc.c revision 1.14.6.3
1 /* $NetBSD: exynos_soc.c,v 1.14.6.3 2017/12/03 11:35:56 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_exynos.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.14.6.3 2017/12/03 11:35:56 jdolecek Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 42 #include <prop/proplib.h> 43 44 #include <net/if.h> 45 #include <net/if_ether.h> 46 47 #include <arm/locore.h> 48 49 #include <arm/mainbus/mainbus.h> 50 #include <arm/cortex/mpcore_var.h> 51 52 #include <arm/samsung/exynos_reg.h> 53 #include <arm/samsung/exynos_var.h> 54 #include <arm/samsung/mct_reg.h> 55 #include <arm/samsung/smc.h> 56 57 #include <arm/cortex/pl310_var.h> 58 #include <arm/cortex/pl310_reg.h> 59 60 /* XXXNH */ 61 #include <evbarm/exynos/platform.h> 62 63 64 /* these variables are retrieved in start.S and stored in .data */ 65 uint32_t exynos_soc_id = 0; 66 uint32_t exynos_pop_id = 0; 67 68 /* cpu frequencies */ 69 struct cpu_freq { 70 uint64_t freq; 71 int P; 72 int M; 73 int S; 74 }; 75 76 77 #ifdef SOC_EXYNOS4 78 const struct cpu_freq cpu_freq_settings_exynos4[] = { 79 { 200, 3, 100, 2}, 80 { 300, 4, 200, 2}, 81 { 400, 3, 100, 1}, 82 { 500, 3, 125, 1}, 83 { 600, 4, 200, 1}, 84 { 700, 3, 175, 1}, 85 { 800, 3, 100, 0}, 86 { 900, 4, 150, 0}, 87 {1000, 3, 125, 0}, 88 {1100, 6, 275, 0}, 89 {1200, 4, 200, 0}, 90 {1300, 6, 325, 0}, 91 {1400, 3, 175, 0}, 92 {1600, 3, 200, 0}, 93 // {1704, 3, 213, 0}, 94 // {1800, 4, 300, 0}, 95 // {1920, 3, 240, 0}, 96 // {2000, 3, 250, 0}, 97 }; 98 #endif 99 100 101 #ifdef SOC_EXYNOS5 102 #define EXYNOS5_DEFAULT_ENTRY 7 103 const struct cpu_freq cpu_freq_settings_exynos5[] = { 104 { 200, 3, 100, 2}, 105 { 333, 4, 222, 2}, 106 { 400, 3, 100, 1}, 107 { 533, 12, 533, 1}, 108 { 600, 4, 200, 1}, 109 { 667, 7, 389, 1}, 110 { 800, 3, 100, 0}, 111 { 900, 4, 150, 0}, 112 {1000, 3, 125, 0}, 113 {1066, 12, 533, 0}, 114 {1200, 3, 150, 0}, 115 {1400, 3, 175, 0}, 116 {1600, 3, 200, 0}, 117 }; 118 #endif 119 120 static struct cpu_freq const *cpu_freq_settings = NULL; 121 static int ncpu_freq_settings = 0; 122 123 static int cpu_freq_target = 0; 124 #define NFRQS 18 125 static char sysctl_cpu_freqs_txt[NFRQS*5]; 126 127 bus_space_handle_t exynos_core_bsh; 128 bus_space_handle_t exynos_audiocore_bsh; 129 130 bus_space_handle_t exynos_wdt_bsh; 131 bus_space_handle_t exynos_pmu_bsh; 132 bus_space_handle_t exynos_cmu_bsh; 133 bus_space_handle_t exynos_cmu_apll_bsh; 134 bus_space_handle_t exynos_sysreg_bsh; 135 136 137 static int sysctl_cpufreq_target(SYSCTLFN_ARGS); 138 static int sysctl_cpufreq_current(SYSCTLFN_ARGS); 139 140 /* 141 * the early serial console 142 */ 143 #ifdef EXYNOS_CONSOLE_EARLY 144 145 #include "opt_sscom.h" 146 #include <arm/samsung/sscom_reg.h> 147 #include <arm/samsung/sscom_var.h> 148 #include <dev/cons.h> 149 150 static volatile uint8_t *uart_base; 151 152 #define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a)))) 153 154 static int 155 exynos_cngetc(dev_t dv) 156 { 157 if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0) 158 return -1; 159 160 return CON_REG(SSCOM_URXH); 161 } 162 163 static void 164 exynos_cnputc(dev_t dv, int c) 165 { 166 int timo = 150000; 167 168 while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0); 169 170 CON_REG(SSCOM_UTXH) = c & 0xff; 171 } 172 173 static struct consdev exynos_earlycons = { 174 .cn_putc = exynos_cnputc, 175 .cn_getc = exynos_cngetc, 176 .cn_pollc = nullcnpollc, 177 }; 178 #endif /* EXYNOS_CONSOLE_EARLY */ 179 180 181 #ifdef ARM_TRUSTZONE_FIRMWARE 182 int 183 exynos_do_idle(void) 184 { 185 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 186 187 return 0; 188 } 189 190 191 int 192 exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr) 193 { 194 /* XXX we need to map in iRAM space for this XXX */ 195 return 0; 196 } 197 198 199 int 200 exynos_cpu_boot(int cpu) 201 { 202 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 203 204 return 0; 205 } 206 207 208 #ifdef SOC_EXYNOS4 209 /* 210 * The latency values used below are `magic' and probably chosen empirically. 211 * For the 4210 variant the data latency is lower, a 0x110. This is currently 212 * not enforced. 213 * 214 * The prefetch values are also different for the revision 0 of the 215 * Exynos4412, but why? 216 */ 217 218 int 219 exynos4_l2cc_init(void) 220 { 221 const uint32_t tag_latency = 0x110; 222 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120; 223 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */ 224 PREFETCHCTL_DBLLINEF_EN | 225 PREFETCHCTL_INSTRPREF_EN | 226 PREFETCHCTL_DATAPREF_EN | 227 PREFETCHCTL_PREF_DROP_EN | 228 PREFETCHCTL_PREFETCH_OFFSET_7; 229 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */ 230 PREFETCHCTL_INSTRPREF_EN | 231 PREFETCHCTL_DATAPREF_EN | 232 PREFETCHCTL_PREFETCH_OFFSET_7; 233 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */ 234 AUXCTL_EARLY_BRESP_EN | 235 AUXCTL_I_PREFETCH | 236 AUXCTL_D_PREFETCH | 237 AUXCTL_NS_INT_ACC_CTL | 238 AUXCTL_NS_INT_LOCK_EN | 239 AUXCTL_SHARED_ATT_OVR | 240 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */ 241 AUXCTL_FULL_LINE_WR0; 242 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */ 243 AUXCTL_RSVD31 | 244 AUXCTL_EARLY_BRESP_EN | 245 AUXCTL_CACHE_REPL_RR | 246 247 AUXCTL_SH_ATTR_INV_ENA| 248 AUXCTL_EXCL_CACHE_CFG | 249 AUXCTL_ST_BUF_DEV_LIM_EN | 250 AUXCTL_HIPRO_SO_DEV_EN | 251 AUXCTL_FULL_LINE_WR0 | 252 0xffff; 253 uint32_t prefetch; 254 255 /* check the bitmaps are the same as the linux implementation uses */ 256 KASSERT(prefetch4412 == 0x71000007); 257 KASSERT(prefetch4412_r0 == 0x30000007); 258 KASSERT(aux_val == 0x7C470001); 259 KASSERT(aux_keepmask == 0xC200FFFF); 260 261 if (IS_EXYNOS4412_R0_P()) 262 prefetch = prefetch4412_r0; 263 else 264 prefetch = prefetch4412; /* newer than >= r1_0 */ 265 ; 266 267 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch); 268 exynos_smc(SMC_CMD_L2X0SETUP2, 269 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY, 270 aux_val, aux_keepmask); 271 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 272 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); 273 274 return 0; 275 } 276 #endif 277 #endif /* ARM_TRUSTZONE_FIRMWARE */ 278 279 280 void 281 exynos_sysctl_cpufreq_init(void) 282 { 283 const struct sysctlnode *node, *cpunode, *freqnode; 284 char *cpos; 285 int i, val; 286 int error; 287 288 memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt)); 289 cpos = sysctl_cpu_freqs_txt; 290 for (i = 0; i < ncpu_freq_settings; i++) { 291 val = cpu_freq_settings[i].freq; 292 snprintf(cpos, 6, "%d ", val); 293 cpos += (val < 1000) ? 4 : 5; 294 } 295 *cpos = 0; 296 297 error = sysctl_createv(NULL, 0, NULL, &node, 298 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 299 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 300 if (error) 301 printf("couldn't create `machdep' node\n"); 302 303 error = sysctl_createv(NULL, 0, &node, &cpunode, 304 0, CTLTYPE_NODE, "cpu", NULL, 305 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 306 if (error) 307 printf("couldn't create `cpu' node\n"); 308 309 error = sysctl_createv(NULL, 0, &cpunode, &freqnode, 310 0, CTLTYPE_NODE, "frequency", NULL, 311 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 312 if (error) 313 printf("couldn't create `frequency' node\n"); 314 315 error = sysctl_createv(NULL, 0, &freqnode, &node, 316 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 317 sysctl_cpufreq_target, 0, &cpu_freq_target, 0, 318 CTL_CREATE, CTL_EOL); 319 if (error) 320 printf("couldn't create `target' node\n"); 321 322 error = sysctl_createv(NULL, 0, &freqnode, &node, 323 0, CTLTYPE_INT, "current", NULL, 324 sysctl_cpufreq_current, 0, NULL, 0, 325 CTL_CREATE, CTL_EOL); 326 if (error) 327 printf("couldn't create `current' node\n"); 328 329 error = sysctl_createv(NULL, 0, &freqnode, &node, 330 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 331 NULL, 0, sysctl_cpu_freqs_txt, 0, 332 CTL_CREATE, CTL_EOL); 333 if (error) 334 printf("couldn't create `available' node\b"); 335 } 336 337 338 uint64_t 339 exynos_get_cpufreq(void) 340 { 341 uint32_t regval; 342 uint32_t freq; 343 344 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, 345 PLL_CON0_OFFSET); 346 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); 347 348 return freq; 349 } 350 351 352 static void 353 exynos_set_cpufreq(const struct cpu_freq *freqreq) 354 { 355 struct cpu_info *ci; 356 uint32_t regval; 357 int M, P, S; 358 int cii; 359 360 M = freqreq->M; 361 P = freqreq->P; 362 S = freqreq->S; 363 364 regval = __SHIFTIN(M, PLL_CON0_M) | 365 __SHIFTIN(P, PLL_CON0_P) | 366 __SHIFTIN(S, PLL_CON0_S); 367 368 /* enable PPL and write config */ 369 regval |= PLL_CON0_ENABLE; 370 bus_space_write_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET, 371 regval); 372 373 /* update our cycle counter i.e. our CPU frequency for all CPUs */ 374 for (CPU_INFO_FOREACH(cii, ci)) { 375 ci->ci_data.cpu_cc_freq = exynos_get_cpufreq(); 376 } 377 } 378 379 380 static int 381 sysctl_cpufreq_target(SYSCTLFN_ARGS) 382 { 383 struct sysctlnode node; 384 uint32_t t, curfreq, minfreq, maxfreq; 385 int i, best_i, diff; 386 int error; 387 388 curfreq = exynos_get_cpufreq() / (1000*1000); 389 t = *(int *)rnode->sysctl_data; 390 if (t == 0) 391 t = curfreq; 392 393 node = *rnode; 394 node.sysctl_data = &t; 395 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 396 if (error || newp == NULL) 397 return error; 398 399 minfreq = cpu_freq_settings[0].freq; 400 maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq; 401 402 if ((t < minfreq) || (t > maxfreq)) 403 return EINVAL; 404 405 if (t == curfreq) { 406 *(int *)rnode->sysctl_data = t; 407 return 0; 408 } 409 410 diff = maxfreq; 411 best_i = -1; 412 for (i = 0; i < ncpu_freq_settings; i++) { 413 if (abs(t - cpu_freq_settings[i].freq) <= diff) { 414 diff = labs(t - cpu_freq_settings[i].freq); 415 best_i = i; 416 } 417 } 418 if (best_i < 0) 419 return EINVAL; 420 421 exynos_set_cpufreq(&cpu_freq_settings[best_i]); 422 423 *(int *)rnode->sysctl_data = t; 424 return 0; 425 } 426 427 428 static int 429 sysctl_cpufreq_current(SYSCTLFN_ARGS) 430 { 431 struct sysctlnode node = *rnode; 432 uint32_t freq; 433 434 freq = exynos_get_cpufreq() / (1000*1000); 435 node.sysctl_data = &freq; 436 437 return sysctl_lookup(SYSCTLFN_CALL(&node)); 438 } 439 440 441 #ifdef VERBOSE_INIT_ARM 442 #define DUMP_PLL(v, var) \ 443 reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\ 444 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \ 445 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \ 446 printf("%8s at %d Mhz\n", #var, freq/(1000*1000)); 447 448 449 static void 450 exynos_dump_clocks(void) 451 { 452 uint32_t reg = 0; 453 uint32_t regval; 454 uint32_t freq; 455 456 printf("Initial PLL settings\n"); 457 #ifdef SOC_EXYNOS4 458 DUMP_PLL(4, APLL); 459 DUMP_PLL(4, MPLL); 460 DUMP_PLL(4, EPLL); 461 DUMP_PLL(4, VPLL); 462 #endif 463 #ifdef SOC_EXYNOS5 464 DUMP_PLL(5, APLL); 465 DUMP_PLL(5, MPLL); 466 DUMP_PLL(5, KPLL); 467 DUMP_PLL(5, DPLL); 468 DUMP_PLL(5, VPLL); 469 DUMP_PLL(5, CPLL); 470 DUMP_PLL(5, GPLL); 471 DUMP_PLL(5, BPLL); 472 #endif 473 } 474 #undef DUMP_PLL 475 #endif 476 477 478 /* XXX clock stuff needs major work XXX */ 479 480 void 481 exynos_init_clkout_for_usb(void) 482 { 483 /* Select XUSBXTI as source for CLKOUT */ 484 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 485 EXYNOS_PMU_DEBUG_CLKOUT, 0x1000); 486 } 487 488 489 void 490 exynos_clocks_bootstrap(void) 491 { 492 KASSERT(ncpu_freq_settings != 0); 493 KASSERT(ncpu_freq_settings < NFRQS); 494 int fsel; 495 496 #ifdef VERBOSE_INIT_ARM 497 exynos_dump_clocks(); 498 #endif 499 500 /* set (max) cpufreq */ 501 fsel = ncpu_freq_settings-1; 502 503 #ifdef SOC_EXYNOS5 504 /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */ 505 fsel = EXYNOS5_DEFAULT_ENTRY; 506 #endif 507 508 exynos_set_cpufreq(&cpu_freq_settings[fsel]); 509 510 /* set external USB frequency to XCLKOUT */ 511 exynos_init_clkout_for_usb(); 512 } 513 514 515 void 516 exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) 517 { 518 int error; 519 size_t core_size, audiocore_size; 520 bus_addr_t audiocore_pbase; 521 bus_addr_t audiocore_vbase __diagused; 522 bus_addr_t exynos_wdt_offset; 523 bus_addr_t exynos_pmu_offset; 524 bus_addr_t exynos_sysreg_offset; 525 bus_addr_t exynos_cmu_apll_offset; 526 527 /* set up early console so we can use printf() and friends */ 528 #ifdef EXYNOS_CONSOLE_EARLY 529 uart_base = (volatile uint8_t *) uartbase; 530 cn_tab = &exynos_earlycons; 531 printf("Exynos early console operational\n\n"); 532 #endif 533 534 #ifdef SOC_EXYNOS4 535 core_size = EXYNOS4_CORE_SIZE; 536 audiocore_size = EXYNOS4_AUDIOCORE_SIZE; 537 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; 538 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; 539 exynos_wdt_offset = EXYNOS4_WDT_OFFSET; 540 exynos_pmu_offset = EXYNOS4_PMU_OFFSET; 541 exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET; 542 exynos_cmu_apll_offset = EXYNOS4_CMU_APLL; 543 544 cpu_freq_settings = cpu_freq_settings_exynos4; 545 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); 546 #endif 547 548 #ifdef SOC_EXYNOS5 549 core_size = EXYNOS5_CORE_SIZE; 550 audiocore_size = EXYNOS5_AUDIOCORE_SIZE; 551 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; 552 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; 553 exynos_wdt_offset = EXYNOS5_WDT_OFFSET; 554 exynos_pmu_offset = EXYNOS5_PMU_OFFSET; 555 exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET; 556 exynos_cmu_apll_offset = EXYNOS5_CMU_APLL; 557 558 cpu_freq_settings = cpu_freq_settings_exynos5; 559 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); 560 #endif 561 562 /* map in the exynos io registers */ 563 error = bus_space_map(&armv7_generic_bs_tag, EXYNOS_CORE_PBASE, 564 core_size, 0, &exynos_core_bsh); 565 if (error) 566 panic("%s: failed to map in Exynos SFR registers: %d", 567 __func__, error); 568 KASSERT(exynos_core_bsh == iobase); 569 570 error = bus_space_map(&armv7_generic_bs_tag, audiocore_pbase, 571 audiocore_size, 0, &exynos_audiocore_bsh); 572 if (error) 573 panic("%s: failed to map in Exynos audio SFR registers: %d", 574 __func__, error); 575 KASSERT(exynos_audiocore_bsh == audiocore_vbase); 576 577 /* map in commonly used subregions and common used register banks */ 578 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 579 exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh); 580 if (error) 581 panic("%s: failed to subregion wdt registers: %d", 582 __func__, error); 583 584 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 585 exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh); 586 if (error) 587 panic("%s: failed to subregion pmu registers: %d", 588 __func__, error); 589 590 exynos_cmu_bsh = exynos_core_bsh; 591 bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 592 exynos_sysreg_offset, EXYNOS_BLOCK_SIZE, 593 &exynos_sysreg_bsh); 594 if (error) 595 panic("%s: failed to subregion sysreg registers: %d", 596 __func__, error); 597 598 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_cmu_bsh, 599 exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh); 600 if (error) 601 panic("%s: failed to subregion cmu apll registers: %d", 602 __func__, error); 603 604 /* gpio bootstrapping delayed */ 605 } 606 607 608 void 609 exynos_device_register(device_t self, void *aux) 610 { 611 if (device_is_a(self, "armperiph") 612 && device_is_a(device_parent(self), "mainbus")) { 613 /* 614 * XXX KLUDGE ALERT XXX 615 * The iot mainbus supplies is completely wrong since it scales 616 * addresses by 2. The simplest remedy is to replace with our 617 * bus space used for the armcore registers (which armperiph uses). 618 */ 619 struct mainbus_attach_args * const mb = aux; 620 mb->mb_iot = &armv7_generic_bs_tag; 621 return; 622 } 623 if (device_is_a(self, "armgic") 624 && device_is_a(device_parent(self), "armperiph")) { 625 /* 626 * The Exynos4420 armgic is located at a different location! 627 */ 628 629 extern uint32_t exynos_soc_id; 630 631 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { 632 #ifdef SOC_EXYNOS5 633 case 0xe5410: 634 /* offsets not changed on matt's request */ 635 #if 0 636 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 637 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 638 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 639 #endif 640 break; 641 case 0xe5422: { 642 struct mpcore_attach_args * const mpcaa = aux; 643 644 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 645 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 646 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 647 break; 648 } 649 #endif 650 #ifdef SOC_EXYNOS4 651 case 0xe4410: 652 case 0xe4412: { 653 struct mpcore_attach_args * const mpcaa = aux; 654 655 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 656 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; 657 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; 658 break; 659 } 660 #endif 661 default: 662 panic("%s: unknown SoC product id %#x", __func__, 663 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); 664 } 665 return; 666 } 667 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { 668 #ifdef SOC_EXYNOS5 669 /* 670 * The global timer is dependent on the MCT running. 671 */ 672 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; 673 uint32_t v = bus_space_read_4(&armv7_generic_bs_tag, exynos_core_bsh, 674 o); 675 v |= G_TCON_START; 676 bus_space_write_4(&armv7_generic_bs_tag, exynos_core_bsh, o, v); 677 #endif 678 /* 679 * The frequencies of the timers are the reference 680 * frequency. 681 */ 682 prop_dictionary_set_uint32(device_properties(self), 683 "frequency", EXYNOS_F_IN_FREQ); 684 return; 685 } 686 } 687 688 689 void 690 exynos_device_register_post_config(device_t self, void *aux) 691 { 692 } 693 694 void 695 exynos_usb_soc_powerup(void) 696 { 697 /* XXX 5422 XXX */ 698 } 699 700 701 /* 702 * USB Phy SoC dependent handling 703 */ 704 705 /* XXX 5422 not handled since its unknown how it handles this XXX*/ 706 static void 707 exynos_usb2_set_isolation(bool on) 708 { 709 uint32_t en_mask, regval; 710 bus_addr_t reg; 711 712 /* enable PHY */ 713 reg = EXYNOS_PMU_USB_PHY_CTRL; 714 715 if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) { 716 /* set usbhost mode */ 717 regval = on ? 0 : USB20_PHY_HOST_LINK_EN; 718 bus_space_write_4(&armv7_generic_bs_tag, exynos_sysreg_bsh, 719 EXYNOS5_SYSREG_USB20_PHY_TYPE, regval); 720 reg = EXYNOS_PMU_USBHOST_PHY_CTRL; 721 } 722 723 /* do enable PHY */ 724 en_mask = PMU_PHY_ENABLE; 725 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_pmu_bsh, reg); 726 regval = on ? regval & ~en_mask : regval | en_mask; 727 728 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 729 reg, regval); 730 731 if (IS_EXYNOS4X12_P()) { 732 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 733 EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval); 734 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 735 EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval); 736 } 737 } 738 739 740 #ifdef SOC_EXYNOS4 741 static void 742 exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 743 { 744 uint32_t phypwr, rstcon, clkreg; 745 746 /* write clock value */ 747 clkreg = FSEL_CLKSEL_24M; 748 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 749 USB_PHYCLK, clkreg); 750 751 /* set device and host to normal */ 752 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 753 USB_PHYPWR); 754 755 /* enable analog, enable otg, unsleep phy0 (host) */ 756 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0; 757 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 758 USB_PHYPWR, phypwr); 759 760 if (IS_EXYNOS4X12_P()) { 761 /* enable hsic0 (host), enable hsic1 and phy1 (otg) */ 762 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 763 USB_PHYPWR); 764 phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 | 765 PHYPWR_NORMAL_MASK_HSIC1 | 766 PHYPWR_NORMAL_MASK_PHY1); 767 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 768 USB_PHYPWR, phypwr); 769 } 770 771 /* reset both phy and link of device */ 772 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 773 USB_RSTCON); 774 rstcon |= RSTCON_DEVPHY_SWRST; 775 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 776 USB_RSTCON, rstcon); 777 DELAY(10000); 778 rstcon &= ~RSTCON_DEVPHY_SWRST; 779 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 780 USB_RSTCON, rstcon); 781 782 if (IS_EXYNOS4X12_P()) { 783 /* reset both phy and link of host */ 784 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 785 USB_RSTCON); 786 rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST; 787 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 788 USB_RSTCON, rstcon); 789 DELAY(10000); 790 rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST); 791 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 792 USB_RSTCON, rstcon); 793 } 794 795 /* wait for everything to be initialized */ 796 DELAY(80000); 797 } 798 #endif 799 800 801 #ifdef SOC_EXYNOS5 802 static void 803 exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 804 { 805 uint32_t phyhost; //, phyotg; 806 uint32_t phyhsic; 807 uint32_t ehcictrl, ohcictrl; 808 809 /* host configuration: */ 810 phyhost = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 811 USB_PHY_HOST_CTRL0); 812 813 /* host phy reference clock; assumption its 24 MHz now */ 814 phyhost &= ~HOST_CTRL0_FSEL_MASK; 815 phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK); 816 817 /* enable normal mode of operation */ 818 phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); 819 820 /* host phy reset */ 821 phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL | 822 HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | 823 HOST_CTRL0_FORCESLEEP); 824 825 /* host link reset */ 826 phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST | 827 HOST_CTRL0_COMMONON_N; 828 /* do the reset */ 829 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 830 phyhost); 831 DELAY(10000); 832 833 phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST); 834 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 835 phyhost); 836 837 /* HSIC control */ 838 phyhsic = 839 __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) | 840 __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) | 841 HSIC_CTRL_PHY_SWRST; 842 843 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 844 phyhsic); 845 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 846 phyhsic); 847 DELAY(10); 848 849 phyhsic &= ~HSIC_CTRL_PHY_SWRST; 850 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 851 phyhsic); 852 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 853 phyhsic); 854 DELAY(80); 855 856 #if 0 857 /* otg configuration: */ 858 phyotg = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 859 USB_PHY_OTG_SYS); 860 861 /* otg phy refrence clock: assumption its 24 Mhz now */ 862 phyotg &= ~OTG_SYS_FSEL_MASK; 863 phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M); 864 865 /* enable normal mode of operation */ 866 phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP | 867 OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK | 868 OTG_SYS_COMMON_ON); 869 870 /* OTG phy and link reset */ 871 phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST | 872 OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK; 873 874 /* do the reset */ 875 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 876 USB_PHY_OTG_SYS, phyotg); 877 DELAY(10000); 878 phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG | 879 OTG_SYS_PHYLINK_SWRST); 880 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 881 USB_PHY_OTG_SYS, phyotg); 882 #endif 883 884 /* enable EHCI DMA burst: */ 885 ehcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 886 USB_PHY_HOST_EHCICTRL); 887 ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN | 888 HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 | 889 HOST_EHCICTRL_ENA_INCR16; 890 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 891 USB_PHY_HOST_EHCICTRL, ehcictrl); 892 893 /* Set OHCI suspend */ 894 ohcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 895 USB_PHY_HOST_OHCICTRL); 896 ohcictrl |= HOST_OHCICTRL_SUSPLGCY; 897 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 898 USB_PHY_HOST_OHCICTRL, ohcictrl); 899 } 900 901 902 static void 903 exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 904 { 905 aprint_error("%s not implemented\n", __func__); 906 } 907 #endif 908 909 910 void 911 exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh) 912 { 913 /* disable phy isolation */ 914 exynos_usb2_set_isolation(false); 915 916 #ifdef SOC_EXYNOS4 917 exynos4_usb2phy_enable(usb2phy_bsh); 918 #endif 919 #ifdef SOC_EXYNOS5 920 if (IS_EXYNOS5410_P()) { 921 exynos5410_usb2phy_enable(usb2phy_bsh); 922 /* TBD: USB3 phy init */ 923 } else if (IS_EXYNOS5422_P()) { 924 exynos5422_usb2phy_enable(usb2phy_bsh); 925 /* TBD: USB3 phy init */ 926 } 927 #endif 928 } 929 930 931
Indexes created Tue Oct 21 08:09:48 GMT 2025