exynos_soc.c revision 1.17
1 /* $NetBSD: exynos_soc.c,v 1.17 2014/08/28 20:29:05 snj Exp $ */ 2 /*- 3 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Reinoud Zandijk. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_exynos.h" 32 33 #define _ARM32_BUS_DMA_PRIVATE 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.17 2014/08/28 20:29:05 snj Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 43 #include <prop/proplib.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 48 #include <arm/locore.h> 49 50 #include <arm/mainbus/mainbus.h> 51 #include <arm/cortex/mpcore_var.h> 52 53 #include <arm/samsung/exynos_reg.h> 54 #include <arm/samsung/exynos_var.h> 55 #include <arm/samsung/mct_reg.h> 56 #include <arm/samsung/smc.h> 57 58 #include <arm/cortex/pl310_var.h> 59 #include <arm/cortex/pl310_reg.h> 60 61 /* XXXNH */ 62 #include <evbarm/odroid/platform.h> 63 64 bus_space_handle_t exynos_core_bsh; 65 bus_space_handle_t exynos_audiocore_bsh; 66 67 /* these variables are retrieved in start.S and stored in .data */ 68 uint32_t exynos_soc_id = 0; 69 uint32_t exynos_pop_id = 0; 70 71 72 /* cpu frequencies */ 73 struct cpu_freq { 74 uint64_t freq; 75 int P; 76 int M; 77 int S; 78 }; 79 80 81 #ifdef EXYNOS4 82 const struct cpu_freq cpu_freq_settings_exynos4[] = { 83 { 200, 3, 100, 2}, 84 { 300, 4, 200, 2}, 85 { 400, 3, 100, 1}, 86 { 500, 3, 125, 1}, 87 { 600, 4, 200, 1}, 88 { 700, 3, 175, 1}, 89 { 800, 3, 100, 0}, 90 { 900, 4, 150, 0}, 91 {1000, 3, 125, 0}, 92 {1100, 6, 275, 0}, 93 {1200, 4, 200, 0}, 94 {1300, 6, 325, 0}, 95 {1400, 3, 175, 0}, 96 {1600, 3, 200, 0}, 97 }; 98 #endif 99 100 101 #ifdef EXYNOS5 102 const struct cpu_freq cpu_freq_settings_exynos5[] = { 103 { 200, 3, 100, 2}, 104 { 333, 4, 222, 2}, 105 { 400, 3, 100, 1}, 106 { 533, 12, 533, 1}, 107 { 600, 4, 200, 1}, 108 { 667, 7, 389, 1}, 109 { 800, 3, 100, 0}, 110 {1000, 3, 125, 0}, 111 {1066, 12, 533, 0}, 112 {1200, 3, 150, 0}, 113 {1400, 3, 175, 0}, 114 {1600, 3, 200, 0}, 115 }; 116 #endif 117 118 static struct cpu_freq const *cpu_freq_settings = NULL; 119 static int ncpu_freq_settings = 0; 120 121 static int cpu_freq_target = 0; 122 #define NFRQS 15 123 static char sysctl_cpu_freqs_txt[NFRQS*5]; 124 125 static int sysctl_cpufreq_target(SYSCTLFN_ARGS); 126 static int sysctl_cpufreq_current(SYSCTLFN_ARGS); 127 128 129 /* 130 * the early serial console 131 */ 132 #ifdef EXYNOS_CONSOLE_EARLY 133 134 #include "opt_sscom.h" 135 #include <arm/samsung/sscom_reg.h> 136 #include <arm/samsung/sscom_var.h> 137 #include <dev/cons.h> 138 139 static volatile uint8_t *uart_base; 140 141 #define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a)))) 142 143 static int 144 exynos_cngetc(dev_t dv) 145 { 146 if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0) 147 return -1; 148 149 return CON_REG(SSCOM_URXH); 150 } 151 152 static void 153 exynos_cnputc(dev_t dv, int c) 154 { 155 int timo = 150000; 156 157 while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0); 158 159 CON_REG(SSCOM_UTXH) = c & 0xff; 160 } 161 162 static struct consdev exynos_earlycons = { 163 .cn_putc = exynos_cnputc, 164 .cn_getc = exynos_cngetc, 165 .cn_pollc = nullcnpollc, 166 }; 167 #endif /* EXYNOS_CONSOLE_EARLY */ 168 169 170 #ifdef ARM_TRUSTZONE_FIRMWARE 171 int 172 exynos_do_idle(void) 173 { 174 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 175 176 return 0; 177 } 178 179 180 int 181 exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr) 182 { 183 /* XXX we need to map in iRAM space for this XXX */ 184 return 0; 185 } 186 187 188 int 189 exynos_cpu_boot(int cpu) 190 { 191 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 192 193 return 0; 194 } 195 196 197 /* 198 * The latency values used below are `magic' and probably chosen empirically. 199 * For the 4210 variant the data latency is lower, a 0x110. This is currently 200 * not enforced. 201 * 202 * The prefetch values are also different for the revision 0 of the 203 * Exynos4412, but why? 204 */ 205 206 int 207 exynos_l2cc_init(void) 208 { 209 const uint32_t tag_latency = 0x110; 210 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120; 211 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */ 212 PREFETCHCTL_DBLLINEF_EN | 213 PREFETCHCTL_INSTRPREF_EN | 214 PREFETCHCTL_DATAPREF_EN | 215 PREFETCHCTL_PREF_DROP_EN | 216 PREFETCHCTL_PREFETCH_OFFSET_7; 217 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */ 218 PREFETCHCTL_INSTRPREF_EN | 219 PREFETCHCTL_DATAPREF_EN | 220 PREFETCHCTL_PREFETCH_OFFSET_7; 221 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */ 222 AUXCTL_EARLY_BRESP_EN | 223 AUXCTL_I_PREFETCH | 224 AUXCTL_D_PREFETCH | 225 AUXCTL_NS_INT_ACC_CTL | 226 AUXCTL_NS_INT_LOCK_EN | 227 AUXCTL_SHARED_ATT_OVR | 228 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */ 229 AUXCTL_FULL_LINE_WR0; 230 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */ 231 AUXCTL_RSVD31 | 232 AUXCTL_EARLY_BRESP_EN | 233 AUXCTL_CACHE_REPL_RR | 234 235 AUXCTL_SH_ATTR_INV_ENA| 236 AUXCTL_EXCL_CACHE_CFG | 237 AUXCTL_ST_BUF_DEV_LIM_EN | 238 AUXCTL_HIPRO_SO_DEV_EN | 239 AUXCTL_FULL_LINE_WR0 | 240 0xffff; 241 uint32_t prefetch; 242 243 /* check the bitmaps are the same as the linux implementation uses */ 244 KASSERT(prefetch4412 == 0x71000007); 245 KASSERT(prefetch4412_r0 == 0x30000007); 246 KASSERT(aux_val == 0x7C470001); 247 KASSERT(aux_keepmask == 0xC200FFFF); 248 249 if (IS_EXYNOS4412_R0_P()) 250 prefetch = prefetch4412_r0; 251 else 252 prefetch = prefetch4412; /* newer than >= r1_0 */ 253 ; 254 255 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch); 256 exynos_smc(SMC_CMD_L2X0SETUP2, 257 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY, 258 aux_val, aux_keepmask); 259 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 260 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); 261 262 return 0; 263 } 264 #endif /* ARM_TRUSTZONE_FIRMWARE */ 265 266 267 void 268 exynos_sysctl_cpufreq_init(void) 269 { 270 const struct sysctlnode *node, *cpunode, *freqnode; 271 char *cpos; 272 int i, val; 273 int error; 274 275 memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt)); 276 cpos = sysctl_cpu_freqs_txt; 277 for (i = 0; i < ncpu_freq_settings; i++) { 278 val = cpu_freq_settings[i].freq; 279 snprintf(cpos, 6, "%d ", val); 280 cpos += (val < 1000) ? 4 : 5; 281 } 282 *cpos = 0; 283 284 error = sysctl_createv(NULL, 0, NULL, &node, 285 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 286 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 287 if (error) 288 printf("couldn't create `machdep' node\n"); 289 290 error = sysctl_createv(NULL, 0, &node, &cpunode, 291 0, CTLTYPE_NODE, "cpu", NULL, 292 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 293 if (error) 294 printf("couldn't create `cpu' node\n"); 295 296 error = sysctl_createv(NULL, 0, &cpunode, &freqnode, 297 0, CTLTYPE_NODE, "frequency", NULL, 298 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 299 if (error) 300 printf("couldn't create `frequency' node\n"); 301 302 error = sysctl_createv(NULL, 0, &freqnode, &node, 303 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 304 sysctl_cpufreq_target, 0, &cpu_freq_target, 0, 305 CTL_CREATE, CTL_EOL); 306 if (error) 307 printf("couldn't create `target' node\n"); 308 309 error = sysctl_createv(NULL, 0, &freqnode, &node, 310 0, CTLTYPE_INT, "current", NULL, 311 sysctl_cpufreq_current, 0, NULL, 0, 312 CTL_CREATE, CTL_EOL); 313 if (error) 314 printf("couldn't create `current' node\n"); 315 316 error = sysctl_createv(NULL, 0, &freqnode, &node, 317 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 318 NULL, 0, sysctl_cpu_freqs_txt, 0, 319 CTL_CREATE, CTL_EOL); 320 if (error) 321 printf("couldn't create `available' node\b"); 322 } 323 324 325 uint64_t 326 exynos_get_cpufreq(void) 327 { 328 uint32_t reg = 0; 329 uint32_t regval; 330 uint32_t freq; 331 332 #ifdef EXYNOS4 333 if (IS_EXYNOS4_P()) 334 reg = EXYNOS4_CMU_APLL + PLL_CON0_OFFSET; 335 #endif 336 #ifdef EXYNOS5 337 if (IS_EXYNOS5_P()) 338 reg = EXYNOS5_CMU_APLL + PLL_CON0_OFFSET; 339 #endif 340 KASSERT(reg); 341 342 regval = bus_space_read_4(&exynos_bs_tag, exynos_core_bsh, reg); 343 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); 344 345 return freq; 346 } 347 348 349 static void 350 exynos_set_cpufreq(const struct cpu_freq *freqreq) 351 { 352 uint32_t reg = 0; 353 uint32_t regval; 354 int M, P, S; 355 356 M = freqreq->M; 357 P = freqreq->P; 358 S = freqreq->S; 359 360 regval = __SHIFTIN(M, PLL_CON0_M) | 361 __SHIFTIN(P, PLL_CON0_P) | 362 __SHIFTIN(S, PLL_CON0_S); 363 364 #ifdef EXYNOS4 365 if (IS_EXYNOS4_P()) 366 reg = EXYNOS4_CMU_APLL + PLL_CON0_OFFSET; 367 #endif 368 #ifdef EXYNOS5 369 if (IS_EXYNOS5_P()) 370 reg = EXYNOS5_CMU_APLL + PLL_CON0_OFFSET; 371 #endif 372 KASSERT(reg); 373 374 /* enable PPL and write config */ 375 regval |= PLL_CON0_ENABLE; 376 bus_space_write_4(&exynos_bs_tag, exynos_core_bsh, reg, regval); 377 } 378 379 380 static int 381 sysctl_cpufreq_target(SYSCTLFN_ARGS) 382 { 383 struct sysctlnode node; 384 uint32_t t, curfreq, minfreq, maxfreq; 385 int i, best_i, diff; 386 int error; 387 388 curfreq = exynos_get_cpufreq() / (1000*1000); 389 t = *(int *)rnode->sysctl_data; 390 if (t == 0) 391 t = curfreq; 392 393 node = *rnode; 394 node.sysctl_data = &t; 395 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 396 if (error || newp == NULL) 397 return error; 398 399 minfreq = cpu_freq_settings[0].freq; 400 maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq; 401 402 if ((t < minfreq) || (t > maxfreq)) 403 return EINVAL; 404 405 if (t == curfreq) { 406 *(int *)rnode->sysctl_data = t; 407 return 0; 408 } 409 410 diff = maxfreq; 411 best_i = -1; 412 for (i = 0; i < ncpu_freq_settings; i++) { 413 if (abs(t - cpu_freq_settings[i].freq) <= diff) { 414 diff = labs(t - cpu_freq_settings[i].freq); 415 best_i = i; 416 } 417 } 418 if (best_i < 0) 419 return EINVAL; 420 421 exynos_set_cpufreq(&cpu_freq_settings[best_i]); 422 423 *(int *)rnode->sysctl_data = t; 424 return 0; 425 } 426 427 428 static int 429 sysctl_cpufreq_current(SYSCTLFN_ARGS) 430 { 431 struct sysctlnode node = *rnode; 432 uint32_t freq; 433 434 freq = exynos_get_cpufreq() / (1000*1000); 435 node.sysctl_data = &freq; 436 437 return sysctl_lookup(SYSCTLFN_CALL(&node)); 438 } 439 440 441 void 442 exynos_clocks_bootstrap(void) 443 { 444 #ifdef EXYNOS4 445 if (IS_EXYNOS4_P()) { 446 cpu_freq_settings = cpu_freq_settings_exynos4; 447 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); 448 } 449 #endif 450 #ifdef EXYNOS5 451 if (IS_EXYNOS5_P()) { 452 cpu_freq_settings = cpu_freq_settings_exynos5; 453 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); 454 } 455 #endif 456 KASSERT(ncpu_freq_settings != 0); 457 KASSERT(ncpu_freq_settings < NFRQS); 458 459 /* set max cpufreq */ 460 exynos_set_cpufreq(&cpu_freq_settings[ncpu_freq_settings-1]); 461 curcpu()->ci_data.cpu_cc_freq = exynos_get_cpufreq(); 462 } 463 464 465 void 466 exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) 467 { 468 int error; 469 size_t core_size, audiocore_size; 470 size_t audiocore_pbase, audiocore_vbase __diagused; 471 472 #ifdef EXYNOS4 473 if (IS_EXYNOS4_P()) { 474 core_size = EXYNOS4_CORE_SIZE; 475 audiocore_size = EXYNOS4_AUDIOCORE_SIZE; 476 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; 477 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; 478 } 479 #endif 480 481 #ifdef EXYNOS5 482 if (IS_EXYNOS5_P()) { 483 core_size = EXYNOS5_CORE_SIZE; 484 audiocore_size = EXYNOS5_AUDIOCORE_SIZE; 485 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; 486 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; 487 } 488 #endif 489 490 /* set up early console so we can use printf() and friends */ 491 #ifdef EXYNOS_CONSOLE_EARLY 492 uart_base = (volatile uint8_t *) uartbase; 493 cn_tab = &exynos_earlycons; 494 printf("Exynos early console operational\n\n"); 495 #endif 496 /* map in the exynos io registers */ 497 error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE, 498 core_size, 0, &exynos_core_bsh); 499 if (error) 500 panic("%s: failed to map in Exynos SFR registers: %d", 501 __func__, error); 502 KASSERT(exynos_core_bsh == iobase); 503 504 error = bus_space_map(&exynos_bs_tag, audiocore_pbase, 505 audiocore_size, 0, &exynos_audiocore_bsh); 506 if (error) 507 panic("%s: failed to map in Exynos audio SFR registers: %d", 508 __func__, error); 509 KASSERT(exynos_audiocore_bsh == audiocore_vbase); 510 511 /* init bus dma tags */ 512 exynos_dma_bootstrap(physmem * PAGE_SIZE); 513 514 /* gpio bootstrapping delayed */ 515 } 516 517 518 void 519 exynos_device_register(device_t self, void *aux) 520 { 521 if (device_is_a(self, "armperiph") 522 && device_is_a(device_parent(self), "mainbus")) { 523 /* 524 * XXX KLUDGE ALERT XXX 525 * The iot mainbus supplies is completely wrong since it scales 526 * addresses by 2. The simplest remedy is to replace with our 527 * bus space used for the armcore regisers (which armperiph uses). 528 */ 529 struct mainbus_attach_args * const mb = aux; 530 mb->mb_iot = &exynos_bs_tag; 531 return; 532 } 533 if (device_is_a(self, "armgic") 534 && device_is_a(device_parent(self), "armperiph")) { 535 /* 536 * The Exynos4420 armgic is located at a different location! 537 */ 538 539 extern uint32_t exynos_soc_id; 540 541 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { 542 #if defined(EXYNOS5) 543 case 0xe5410: 544 /* offsets not changed on matt's request */ 545 #if 0 546 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 547 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 548 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 549 #endif 550 break; 551 #endif 552 #if defined(EXYNOS4) 553 case 0xe4410: 554 case 0xe4412: { 555 struct mpcore_attach_args * const mpcaa = aux; 556 557 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 558 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; 559 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; 560 break; 561 } 562 #endif 563 default: 564 panic("%s: unknown SoC product id %#x", __func__, 565 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); 566 } 567 return; 568 } 569 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { 570 #ifdef EXYNOS5 571 /* 572 * The global timer is dependent on the MCT running. 573 */ 574 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; 575 uint32_t v = bus_space_read_4(&exynos_bs_tag, exynos_core_bsh, 576 o); 577 v |= G_TCON_START; 578 bus_space_write_4(&exynos_bs_tag, exynos_core_bsh, o, v); 579 #endif 580 /* 581 * The frequencies of the timers are the reference 582 * frequency. 583 */ 584 prop_dictionary_set_uint32(device_properties(self), 585 "frequency", EXYNOS_F_IN_FREQ); 586 return; 587 } 588 589 exyo_device_register(self, aux); 590 } 591 592 593 void 594 exynos_device_register_post_config(device_t self, void *aux) 595 { 596 exyo_device_register_post_config(self, aux); 597 } 598 599
Indexes created Tue Sep 30 20:09:53 GMT 2025