exynos_soc.c revision 1.24
1 /* $NetBSD: exynos_soc.c,v 1.24 2014/10/02 11:17:50 reinoud Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_exynos.h" 33 34 #define _ARM32_BUS_DMA_PRIVATE 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.24 2014/10/02 11:17:50 reinoud Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 44 #include <prop/proplib.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #include <arm/locore.h> 50 51 #include <arm/mainbus/mainbus.h> 52 #include <arm/cortex/mpcore_var.h> 53 54 #include <arm/samsung/exynos_reg.h> 55 #include <arm/samsung/exynos_var.h> 56 #include <arm/samsung/mct_reg.h> 57 #include <arm/samsung/smc.h> 58 59 #include <arm/cortex/pl310_var.h> 60 #include <arm/cortex/pl310_reg.h> 61 62 /* XXXNH */ 63 #include <evbarm/odroid/platform.h> 64 65 66 /* these variables are retrieved in start.S and stored in .data */ 67 uint32_t exynos_soc_id = 0; 68 uint32_t exynos_pop_id = 0; 69 70 /* cpu frequencies */ 71 struct cpu_freq { 72 uint64_t freq; 73 int P; 74 int M; 75 int S; 76 }; 77 78 79 #ifdef EXYNOS4 80 const struct cpu_freq cpu_freq_settings_exynos4[] = { 81 { 200, 3, 100, 2}, 82 { 300, 4, 200, 2}, 83 { 400, 3, 100, 1}, 84 { 500, 3, 125, 1}, 85 { 600, 4, 200, 1}, 86 { 700, 3, 175, 1}, 87 { 800, 3, 100, 0}, 88 { 900, 4, 150, 0}, 89 {1000, 3, 125, 0}, 90 {1100, 6, 275, 0}, 91 {1200, 4, 200, 0}, 92 {1300, 6, 325, 0}, 93 {1400, 3, 175, 0}, 94 {1600, 3, 200, 0}, 95 // {1704, 3, 213, 0}, 96 // {1800, 4, 300, 0}, 97 // {1920, 3, 240, 0}, 98 // {2000, 3, 250, 0}, 99 }; 100 #endif 101 102 103 #ifdef EXYNOS5 104 #define EXYNOS5_DEFAULT_ENTRY 7 105 const struct cpu_freq cpu_freq_settings_exynos5[] = { 106 { 200, 3, 100, 2}, 107 { 333, 4, 222, 2}, 108 { 400, 3, 100, 1}, 109 { 533, 12, 533, 1}, 110 { 600, 4, 200, 1}, 111 { 667, 7, 389, 1}, 112 { 800, 3, 100, 0}, 113 { 900, 4, 150, 0}, 114 {1000, 3, 125, 0}, 115 {1066, 12, 533, 0}, 116 {1200, 3, 150, 0}, 117 {1400, 3, 175, 0}, 118 {1600, 3, 200, 0}, 119 }; 120 #endif 121 122 static struct cpu_freq const *cpu_freq_settings = NULL; 123 static int ncpu_freq_settings = 0; 124 125 static int cpu_freq_target = 0; 126 #define NFRQS 18 127 static char sysctl_cpu_freqs_txt[NFRQS*5]; 128 129 bus_space_handle_t exynos_core_bsh; 130 bus_space_handle_t exynos_audiocore_bsh; 131 132 bus_space_handle_t exynos_wdt_bsh; 133 bus_space_handle_t exynos_pmu_bsh; 134 bus_space_handle_t exynos_cmu_bsh; 135 bus_space_handle_t exynos_cmu_apll_bsh; 136 bus_space_handle_t exynos_sysreg_bsh; 137 138 139 static int sysctl_cpufreq_target(SYSCTLFN_ARGS); 140 static int sysctl_cpufreq_current(SYSCTLFN_ARGS); 141 142 /* 143 * the early serial console 144 */ 145 #ifdef EXYNOS_CONSOLE_EARLY 146 147 #include "opt_sscom.h" 148 #include <arm/samsung/sscom_reg.h> 149 #include <arm/samsung/sscom_var.h> 150 #include <dev/cons.h> 151 152 static volatile uint8_t *uart_base; 153 154 #define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a)))) 155 156 static int 157 exynos_cngetc(dev_t dv) 158 { 159 if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0) 160 return -1; 161 162 return CON_REG(SSCOM_URXH); 163 } 164 165 static void 166 exynos_cnputc(dev_t dv, int c) 167 { 168 int timo = 150000; 169 170 while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0); 171 172 CON_REG(SSCOM_UTXH) = c & 0xff; 173 } 174 175 static struct consdev exynos_earlycons = { 176 .cn_putc = exynos_cnputc, 177 .cn_getc = exynos_cngetc, 178 .cn_pollc = nullcnpollc, 179 }; 180 #endif /* EXYNOS_CONSOLE_EARLY */ 181 182 183 #ifdef ARM_TRUSTZONE_FIRMWARE 184 int 185 exynos_do_idle(void) 186 { 187 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 188 189 return 0; 190 } 191 192 193 int 194 exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr) 195 { 196 /* XXX we need to map in iRAM space for this XXX */ 197 return 0; 198 } 199 200 201 int 202 exynos_cpu_boot(int cpu) 203 { 204 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 205 206 return 0; 207 } 208 209 210 #ifdef EXYNOS4 211 /* 212 * The latency values used below are `magic' and probably chosen empirically. 213 * For the 4210 variant the data latency is lower, a 0x110. This is currently 214 * not enforced. 215 * 216 * The prefetch values are also different for the revision 0 of the 217 * Exynos4412, but why? 218 */ 219 220 int 221 exynos4_l2cc_init(void) 222 { 223 const uint32_t tag_latency = 0x110; 224 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120; 225 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */ 226 PREFETCHCTL_DBLLINEF_EN | 227 PREFETCHCTL_INSTRPREF_EN | 228 PREFETCHCTL_DATAPREF_EN | 229 PREFETCHCTL_PREF_DROP_EN | 230 PREFETCHCTL_PREFETCH_OFFSET_7; 231 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */ 232 PREFETCHCTL_INSTRPREF_EN | 233 PREFETCHCTL_DATAPREF_EN | 234 PREFETCHCTL_PREFETCH_OFFSET_7; 235 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */ 236 AUXCTL_EARLY_BRESP_EN | 237 AUXCTL_I_PREFETCH | 238 AUXCTL_D_PREFETCH | 239 AUXCTL_NS_INT_ACC_CTL | 240 AUXCTL_NS_INT_LOCK_EN | 241 AUXCTL_SHARED_ATT_OVR | 242 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */ 243 AUXCTL_FULL_LINE_WR0; 244 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */ 245 AUXCTL_RSVD31 | 246 AUXCTL_EARLY_BRESP_EN | 247 AUXCTL_CACHE_REPL_RR | 248 249 AUXCTL_SH_ATTR_INV_ENA| 250 AUXCTL_EXCL_CACHE_CFG | 251 AUXCTL_ST_BUF_DEV_LIM_EN | 252 AUXCTL_HIPRO_SO_DEV_EN | 253 AUXCTL_FULL_LINE_WR0 | 254 0xffff; 255 uint32_t prefetch; 256 257 /* check the bitmaps are the same as the linux implementation uses */ 258 KASSERT(prefetch4412 == 0x71000007); 259 KASSERT(prefetch4412_r0 == 0x30000007); 260 KASSERT(aux_val == 0x7C470001); 261 KASSERT(aux_keepmask == 0xC200FFFF); 262 263 if (IS_EXYNOS4412_R0_P()) 264 prefetch = prefetch4412_r0; 265 else 266 prefetch = prefetch4412; /* newer than >= r1_0 */ 267 ; 268 269 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch); 270 exynos_smc(SMC_CMD_L2X0SETUP2, 271 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY, 272 aux_val, aux_keepmask); 273 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 274 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); 275 276 return 0; 277 } 278 #endif 279 #endif /* ARM_TRUSTZONE_FIRMWARE */ 280 281 282 void 283 exynos_sysctl_cpufreq_init(void) 284 { 285 const struct sysctlnode *node, *cpunode, *freqnode; 286 char *cpos; 287 int i, val; 288 int error; 289 290 memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt)); 291 cpos = sysctl_cpu_freqs_txt; 292 for (i = 0; i < ncpu_freq_settings; i++) { 293 val = cpu_freq_settings[i].freq; 294 snprintf(cpos, 6, "%d ", val); 295 cpos += (val < 1000) ? 4 : 5; 296 } 297 *cpos = 0; 298 299 error = sysctl_createv(NULL, 0, NULL, &node, 300 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 301 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 302 if (error) 303 printf("couldn't create `machdep' node\n"); 304 305 error = sysctl_createv(NULL, 0, &node, &cpunode, 306 0, CTLTYPE_NODE, "cpu", NULL, 307 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 308 if (error) 309 printf("couldn't create `cpu' node\n"); 310 311 error = sysctl_createv(NULL, 0, &cpunode, &freqnode, 312 0, CTLTYPE_NODE, "frequency", NULL, 313 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 314 if (error) 315 printf("couldn't create `frequency' node\n"); 316 317 error = sysctl_createv(NULL, 0, &freqnode, &node, 318 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 319 sysctl_cpufreq_target, 0, &cpu_freq_target, 0, 320 CTL_CREATE, CTL_EOL); 321 if (error) 322 printf("couldn't create `target' node\n"); 323 324 error = sysctl_createv(NULL, 0, &freqnode, &node, 325 0, CTLTYPE_INT, "current", NULL, 326 sysctl_cpufreq_current, 0, NULL, 0, 327 CTL_CREATE, CTL_EOL); 328 if (error) 329 printf("couldn't create `current' node\n"); 330 331 error = sysctl_createv(NULL, 0, &freqnode, &node, 332 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 333 NULL, 0, sysctl_cpu_freqs_txt, 0, 334 CTL_CREATE, CTL_EOL); 335 if (error) 336 printf("couldn't create `available' node\b"); 337 } 338 339 340 uint64_t 341 exynos_get_cpufreq(void) 342 { 343 uint32_t regval; 344 uint32_t freq; 345 346 regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_apll_bsh, 347 PLL_CON0_OFFSET); 348 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); 349 350 return freq; 351 } 352 353 354 static void 355 exynos_set_cpufreq(const struct cpu_freq *freqreq) 356 { 357 struct cpu_info *ci; 358 uint32_t regval; 359 int M, P, S; 360 int cii; 361 362 M = freqreq->M; 363 P = freqreq->P; 364 S = freqreq->S; 365 366 regval = __SHIFTIN(M, PLL_CON0_M) | 367 __SHIFTIN(P, PLL_CON0_P) | 368 __SHIFTIN(S, PLL_CON0_S); 369 370 /* enable PPL and write config */ 371 regval |= PLL_CON0_ENABLE; 372 bus_space_write_4(&exynos_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET, 373 regval); 374 375 /* update our cycle counter i.e. our CPU frequency for all CPUs */ 376 for (CPU_INFO_FOREACH(cii, ci)) { 377 ci->ci_data.cpu_cc_freq = exynos_get_cpufreq(); 378 } 379 } 380 381 382 static int 383 sysctl_cpufreq_target(SYSCTLFN_ARGS) 384 { 385 struct sysctlnode node; 386 uint32_t t, curfreq, minfreq, maxfreq; 387 int i, best_i, diff; 388 int error; 389 390 curfreq = exynos_get_cpufreq() / (1000*1000); 391 t = *(int *)rnode->sysctl_data; 392 if (t == 0) 393 t = curfreq; 394 395 node = *rnode; 396 node.sysctl_data = &t; 397 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 398 if (error || newp == NULL) 399 return error; 400 401 minfreq = cpu_freq_settings[0].freq; 402 maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq; 403 404 if ((t < minfreq) || (t > maxfreq)) 405 return EINVAL; 406 407 if (t == curfreq) { 408 *(int *)rnode->sysctl_data = t; 409 return 0; 410 } 411 412 diff = maxfreq; 413 best_i = -1; 414 for (i = 0; i < ncpu_freq_settings; i++) { 415 if (abs(t - cpu_freq_settings[i].freq) <= diff) { 416 diff = labs(t - cpu_freq_settings[i].freq); 417 best_i = i; 418 } 419 } 420 if (best_i < 0) 421 return EINVAL; 422 423 exynos_set_cpufreq(&cpu_freq_settings[best_i]); 424 425 *(int *)rnode->sysctl_data = t; 426 return 0; 427 } 428 429 430 static int 431 sysctl_cpufreq_current(SYSCTLFN_ARGS) 432 { 433 struct sysctlnode node = *rnode; 434 uint32_t freq; 435 436 freq = exynos_get_cpufreq() / (1000*1000); 437 node.sysctl_data = &freq; 438 439 return sysctl_lookup(SYSCTLFN_CALL(&node)); 440 } 441 442 443 #ifdef VERBOSE_INIT_ARM 444 #define DUMP_PLL(v, var) \ 445 reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\ 446 regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_bsh, reg); \ 447 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \ 448 printf("%8s at %d Mhz\n", #var, freq/(1000*1000)); 449 450 451 static void 452 exynos_dump_clocks(void) 453 { 454 uint32_t reg = 0; 455 uint32_t regval; 456 uint32_t freq; 457 458 printf("Initial PLL settings\n"); 459 #ifdef EXYNOS4 460 DUMP_PLL(4, APLL); 461 DUMP_PLL(4, MPLL); 462 DUMP_PLL(4, EPLL); 463 DUMP_PLL(4, VPLL); 464 #endif 465 #ifdef EXYNOS5 466 DUMP_PLL(5, APLL); 467 DUMP_PLL(5, MPLL); 468 DUMP_PLL(5, EPLL); 469 DUMP_PLL(5, VPLL); 470 DUMP_PLL(5, CPLL); 471 DUMP_PLL(5, GPLL); 472 DUMP_PLL(5, BPLL); 473 #endif 474 } 475 #undef DUMP_PLL 476 #endif 477 478 479 /* XXX clock stuff needs major work XXX */ 480 481 void 482 exynos_clocks_bootstrap(void) 483 { 484 KASSERT(ncpu_freq_settings != 0); 485 KASSERT(ncpu_freq_settings < NFRQS); 486 int fsel; 487 488 #ifdef VERBOSE_INIT_ARM 489 exynos_dump_clocks(); 490 #endif 491 492 /* set (max) cpufreq */ 493 fsel = ncpu_freq_settings-1; 494 495 #ifdef EXYNOS5 496 /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */ 497 fsel = EXYNOS5_DEFAULT_ENTRY; 498 #endif 499 500 exynos_set_cpufreq(&cpu_freq_settings[fsel]); 501 502 /* set external USB frequency to XCLKOUT */ 503 exynos_init_clkout_for_usb(); 504 } 505 506 507 void 508 exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) 509 { 510 int error; 511 size_t core_size, audiocore_size; 512 bus_addr_t audiocore_pbase; 513 bus_addr_t audiocore_vbase __diagused; 514 bus_addr_t exynos_wdt_offset; 515 bus_addr_t exynos_pmu_offset; 516 bus_addr_t exynos_sysreg_offset; 517 bus_addr_t exynos_cmu_apll_offset; 518 519 /* set up early console so we can use printf() and friends */ 520 #ifdef EXYNOS_CONSOLE_EARLY 521 uart_base = (volatile uint8_t *) uartbase; 522 cn_tab = &exynos_earlycons; 523 printf("Exynos early console operational\n\n"); 524 #endif 525 526 #ifdef EXYNOS4 527 core_size = EXYNOS4_CORE_SIZE; 528 audiocore_size = EXYNOS4_AUDIOCORE_SIZE; 529 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; 530 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; 531 exynos_wdt_offset = EXYNOS4_WDT_OFFSET; 532 exynos_pmu_offset = EXYNOS4_PMU_OFFSET; 533 exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET; 534 exynos_cmu_apll_offset = EXYNOS4_CMU_APLL; 535 536 cpu_freq_settings = cpu_freq_settings_exynos4; 537 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); 538 #endif 539 540 #ifdef EXYNOS5 541 core_size = EXYNOS5_CORE_SIZE; 542 audiocore_size = EXYNOS5_AUDIOCORE_SIZE; 543 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; 544 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; 545 exynos_wdt_offset = EXYNOS5_WDT_OFFSET; 546 exynos_pmu_offset = EXYNOS5_PMU_OFFSET; 547 exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET; 548 exynos_cmu_apll_offset = EXYNOS5_CMU_APLL; 549 550 cpu_freq_settings = cpu_freq_settings_exynos5; 551 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); 552 #endif 553 554 /* map in the exynos io registers */ 555 error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE, 556 core_size, 0, &exynos_core_bsh); 557 if (error) 558 panic("%s: failed to map in Exynos SFR registers: %d", 559 __func__, error); 560 KASSERT(exynos_core_bsh == iobase); 561 562 error = bus_space_map(&exynos_bs_tag, audiocore_pbase, 563 audiocore_size, 0, &exynos_audiocore_bsh); 564 if (error) 565 panic("%s: failed to map in Exynos audio SFR registers: %d", 566 __func__, error); 567 KASSERT(exynos_audiocore_bsh == audiocore_vbase); 568 569 /* map in commonly used subregions and common used register banks */ 570 error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 571 exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh); 572 if (error) 573 panic("%s: failed to subregion wdt registers: %d", 574 __func__, error); 575 576 error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 577 exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh); 578 if (error) 579 panic("%s: failed to subregion pmu registers: %d", 580 __func__, error); 581 582 exynos_cmu_bsh = exynos_core_bsh; 583 bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 584 exynos_sysreg_offset, EXYNOS_BLOCK_SIZE, 585 &exynos_sysreg_bsh); 586 if (error) 587 panic("%s: failed to subregion sysreg registers: %d", 588 __func__, error); 589 590 error = bus_space_subregion(&exynos_bs_tag, exynos_cmu_bsh, 591 exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh); 592 if (error) 593 panic("%s: failed to subregion cmu apll registers: %d", 594 __func__, error); 595 596 /* init bus dma tags */ 597 exynos_dma_bootstrap(physmem * PAGE_SIZE); 598 599 /* gpio bootstrapping delayed */ 600 } 601 602 603 void 604 exynos_device_register(device_t self, void *aux) 605 { 606 if (device_is_a(self, "armperiph") 607 && device_is_a(device_parent(self), "mainbus")) { 608 /* 609 * XXX KLUDGE ALERT XXX 610 * The iot mainbus supplies is completely wrong since it scales 611 * addresses by 2. The simplest remedy is to replace with our 612 * bus space used for the armcore registers (which armperiph uses). 613 */ 614 struct mainbus_attach_args * const mb = aux; 615 mb->mb_iot = &exynos_bs_tag; 616 return; 617 } 618 if (device_is_a(self, "armgic") 619 && device_is_a(device_parent(self), "armperiph")) { 620 /* 621 * The Exynos4420 armgic is located at a different location! 622 */ 623 624 extern uint32_t exynos_soc_id; 625 626 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { 627 #ifdef EXYNOS5 628 case 0xe5410: 629 /* offsets not changed on matt's request */ 630 #if 0 631 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 632 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 633 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 634 #endif 635 break; 636 #endif 637 #ifdef EXYNOS4 638 case 0xe4410: 639 case 0xe4412: { 640 struct mpcore_attach_args * const mpcaa = aux; 641 642 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 643 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; 644 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; 645 break; 646 } 647 #endif 648 default: 649 panic("%s: unknown SoC product id %#x", __func__, 650 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); 651 } 652 return; 653 } 654 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { 655 #ifdef EXYNOS5 656 /* 657 * The global timer is dependent on the MCT running. 658 */ 659 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; 660 uint32_t v = bus_space_read_4(&exynos_bs_tag, exynos_core_bsh, 661 o); 662 v |= G_TCON_START; 663 bus_space_write_4(&exynos_bs_tag, exynos_core_bsh, o, v); 664 #endif 665 /* 666 * The frequencies of the timers are the reference 667 * frequency. 668 */ 669 prop_dictionary_set_uint32(device_properties(self), 670 "frequency", EXYNOS_F_IN_FREQ); 671 return; 672 } 673 674 exyo_device_register(self, aux); 675 } 676 677 678 void 679 exynos_device_register_post_config(device_t self, void *aux) 680 { 681 exyo_device_register_post_config(self, aux); 682 } 683 684 685 /* 686 * USB power SoC dependent handling 687 */ 688 689 #ifdef EXYNOS4 690 static struct exynos_gpio_pinset e4_uhost_pwr_pinset = { 691 .pinset_group = "ETC6", 692 .pinset_func = 0, 693 .pinset_mask = __BIT(6) | __BIT(7), 694 }; 695 #endif 696 697 698 #ifdef EXYNOS5 699 static struct exynos_gpio_pinset e5_uhost_pwr_pinset = { 700 .pinset_group = "ETC6", 701 .pinset_func = 0, 702 .pinset_mask = __BIT(5) | __BIT(6), 703 }; 704 static struct exynos_gpio_pinset e5_usb3_bus0_pinset = { 705 .pinset_group = "GPK3", 706 .pinset_func = 2, 707 .pinset_mask = __BIT(0) | __BIT(1) | __BIT(3), 708 }; 709 static struct exynos_gpio_pinset e5_usb3_bus1_pinset = { 710 .pinset_group = "GPK2", 711 .pinset_func = 2, 712 .pinset_mask = __BIT(4) | __BIT(5) | __BIT(7), 713 }; 714 #endif 715 716 717 void 718 exynos_usb_soc_powerup(void) 719 { 720 struct exynos_gpio_pindata XuhostOVERCUR; 721 struct exynos_gpio_pindata XuhostPWREN; 722 723 #ifdef EXYNOS4 724 exynos_gpio_pinset_acquire(&e4_uhost_pwr_pinset); 725 exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 6, &XuhostPWREN); 726 exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 7, &XuhostOVERCUR); 727 728 /* enable power and set Xuhost OVERCUR to inactive by pulling it up */ 729 exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP); 730 exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP); 731 DELAY(80000); 732 #endif 733 #ifdef EXYNOS5 734 if (IS_EXYNOS5410_P()) { 735 struct exynos_gpio_pindata Xovercur2, Xovercur3; 736 struct exynos_gpio_pindata Xvbus; 737 738 /* BUS 0 */ 739 exynos_gpio_pinset_acquire(&e5_usb3_bus0_pinset); 740 exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 0, &Xovercur2); 741 exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 1, &Xovercur3); 742 exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 3, &Xvbus); 743 744 /* enable power and set overcur inactive by pulling them up */ 745 exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP); 746 exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP); 747 exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP); 748 749 /* BUS 1 */ 750 exynos_gpio_pinset_acquire(&e5_usb3_bus1_pinset); 751 exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 4, &Xovercur2); 752 exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 5, &Xovercur3); 753 exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 7, &Xvbus); 754 755 /* enable power and set overcur inactive by pulling them up */ 756 exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP); 757 exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP); 758 exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP); 759 760 /* enable power to the hub */ 761 exynos_gpio_pinset_acquire(&e5_uhost_pwr_pinset); 762 exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 5, &XuhostPWREN); 763 exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 6, &XuhostOVERCUR); 764 765 /* enable power and set Xuhost OVERCUR to inactive by pulling it up */ 766 exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP); 767 exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP); 768 DELAY(80000); 769 } 770 /* XXX 5422 XXX */ 771 #endif 772 } 773 774 775 /* 776 * USB Phy SoC dependent handling 777 */ 778 779 /* XXX 5422 not handled since its unknown how it handles this XXX*/ 780 static void 781 exynos_usb2_set_isolation(bool on) 782 { 783 uint32_t en_mask, regval; 784 bus_addr_t reg; 785 786 /* enable PHY */ 787 reg = EXYNOS_PMU_USB_PHY_CTRL; 788 789 if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) { 790 /* set usbhost mode */ 791 regval = on ? 0 : USB20_PHY_HOST_LINK_EN; 792 bus_space_write_4(&exynos_bs_tag, exynos_sysreg_bsh, 793 EXYNOS5_SYSREG_USB20_PHY_TYPE, regval); 794 reg = EXYNOS_PMU_USBHOST_PHY_CTRL; 795 } 796 797 /* do enable PHY */ 798 en_mask = PMU_PHY_ENABLE; 799 regval = bus_space_read_4(&exynos_bs_tag, exynos_pmu_bsh, reg); 800 regval = on ? regval & ~en_mask : regval | en_mask; 801 802 bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh, 803 reg, regval); 804 805 if (IS_EXYNOS4X12_P()) { 806 bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh, 807 EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval); 808 bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh, 809 EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval); 810 } 811 } 812 813 814 #ifdef EXYNOS4 815 static void 816 exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 817 { 818 uint32_t phypwr, rstcon, clkreg; 819 820 /* write clock value */ 821 clkreg = FSEL_CLKSEL_24M; 822 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 823 USB_PHYCLK, clkreg); 824 825 /* set device and host to normal */ 826 phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 827 USB_PHYPWR); 828 829 /* enable analog, enable otg, unsleep phy0 (host) */ 830 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0; 831 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 832 USB_PHYPWR, phypwr); 833 834 if (IS_EXYNOS4X12_P()) { 835 /* enable hsic0 (host), enable hsic1 and phy1 (otg) */ 836 phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 837 USB_PHYPWR); 838 phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 | 839 PHYPWR_NORMAL_MASK_HSIC1 | 840 PHYPWR_NORMAL_MASK_PHY1); 841 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 842 USB_PHYPWR, phypwr); 843 } 844 845 /* reset both phy and link of device */ 846 rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 847 USB_RSTCON); 848 rstcon |= RSTCON_DEVPHY_SWRST; 849 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 850 USB_RSTCON, rstcon); 851 DELAY(10000); 852 rstcon &= ~RSTCON_DEVPHY_SWRST; 853 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 854 USB_RSTCON, rstcon); 855 856 if (IS_EXYNOS4X12_P()) { 857 /* reset both phy and link of host */ 858 rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 859 USB_RSTCON); 860 rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST; 861 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 862 USB_RSTCON, rstcon); 863 DELAY(10000); 864 rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST); 865 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 866 USB_RSTCON, rstcon); 867 } 868 869 /* wait for everything to be initialized */ 870 DELAY(80000); 871 } 872 #endif 873 874 875 #ifdef EXYNOS5 876 static void 877 exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 878 { 879 uint32_t phyhost; //, phyotg; 880 uint32_t phyhsic1, phyhsic2, hsic_ctrl; 881 uint32_t ehcictrl; //, ohcictrl; 882 883 /* host configuration: */ 884 phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 885 USB_PHY_HOST_CTRL0); 886 887 /* host phy reference clock; assumption its 24 MHz now */ 888 phyhost &= ~HOST_CTRL0_FSEL_MASK; 889 phyhost |= __SHIFTIN(HOST_CTRL0_FSEL_MASK, FSEL_CLKSEL_24M); 890 891 /* enable normal mode of operation */ 892 phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); 893 894 /* host phy reset */ 895 phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL | 896 HOST_CTRL0_SIDDQ | HOST_CTRL0_COMMONON_N); 897 898 /* host link reset */ 899 phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST; 900 901 /* do the reset */ 902 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 903 USB_PHY_HOST_CTRL0, phyhost); 904 DELAY(10000); 905 phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST); 906 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 907 USB_PHY_HOST_CTRL0, phyhost); 908 909 #if 0 910 /* otg configuration: */ 911 phyotg = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 912 USB_PHY_OTG_SYS); 913 914 /* otg phy refrence clock: assumption its 24 Mhz now */ 915 phyotg &= ~OTG_SYS_FSEL_MASK; 916 phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M); 917 918 /* enable normal mode of operation */ 919 phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP | 920 OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK | 921 OTG_SYS_COMMON_ON); 922 923 /* OTG phy and link reset */ 924 phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST | 925 OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK; 926 927 /* do the reset */ 928 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 929 USB_PHY_OTG_SYS, phyotg); 930 DELAY(10000); 931 phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG | 932 OTG_SYS_PHYLINK_SWRST); 933 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 934 USB_PHY_OTG_SYS, phyotg); 935 #endif 936 937 /* HSIC phy configuration: */ 938 hsic_ctrl = HSIC_CTRL_FORCESUSPEND | HSIC_CTRL_FORCESLEEP | 939 HSIC_CTRL_SIDDQ; 940 941 phyhsic1 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 942 USB_PHY_HSIC_CTRL1); 943 phyhsic2 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 944 USB_PHY_HSIC_CTRL1); 945 946 phyhsic1 &= ~hsic_ctrl; 947 phyhsic2 &= ~hsic_ctrl; 948 949 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 950 USB_PHY_HSIC_CTRL1, phyhsic1); 951 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 952 USB_PHY_HSIC_CTRL2, phyhsic2); 953 DELAY(10000); 954 955 hsic_ctrl = REFCLKDIV_12 | REFCLKSEL_HSIC_DEFAULT | 956 HSIC_CTRL_UTMI_SWRST; 957 958 phyhsic1 |= hsic_ctrl; 959 phyhsic2 |= hsic_ctrl; 960 961 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 962 USB_PHY_HSIC_CTRL1, phyhsic1); 963 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 964 USB_PHY_HSIC_CTRL2, phyhsic2); 965 966 DELAY(10000); 967 968 hsic_ctrl = HSIC_CTRL_PHY_SWRST | HSIC_CTRL_UTMI_SWRST; 969 970 phyhsic1 &= ~hsic_ctrl; 971 phyhsic2 &= ~hsic_ctrl; 972 973 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 974 USB_PHY_HSIC_CTRL1, phyhsic1); 975 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 976 USB_PHY_HSIC_CTRL2, phyhsic2); 977 DELAY(20000); 978 979 /* enable EHCI DMA burst: */ 980 ehcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 981 USB_PHY_HOST_EHCICTRL); 982 ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN | 983 HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 | 984 HOST_EHCICTRL_ENA_INCR16; 985 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 986 USB_PHY_HOST_EHCICTRL, ehcictrl); 987 DELAY(10000); 988 } 989 990 991 static void 992 exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 993 { 994 aprint_error("%s not implemented\n", __func__); 995 } 996 #endif 997 998 999 void 1000 exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh) 1001 { 1002 /* disable phy isolation */ 1003 exynos_usb2_set_isolation(false); 1004 1005 #ifdef EXYNOS4 1006 exynos4_usb2phy_enable(usb2phy_bsh); 1007 #endif 1008 #ifdef EXYNOS5 1009 if (IS_EXYNOS5410_P()) { 1010 exynos5410_usb2phy_enable(usb2phy_bsh); 1011 /* TBD: USB3 phy init */ 1012 } else if (IS_EXYNOS5422_P()) { 1013 exynos5422_usb2phy_enable(usb2phy_bsh); 1014 /* TBD: USB3 phy init */ 1015 } 1016 #endif 1017 } 1018 1019 1020
Indexes created Wed Oct 01 07:09:59 GMT 2025