exynos_soc.c revision 1.30
1 /* $NetBSD: exynos_soc.c,v 1.30 2015/12/12 21:57:40 marty Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_exynos.h" 33 34 #define _ARM32_BUS_DMA_PRIVATE 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.30 2015/12/12 21:57:40 marty Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 44 #include <prop/proplib.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #include <arm/locore.h> 50 51 #include <arm/mainbus/mainbus.h> 52 #include <arm/cortex/mpcore_var.h> 53 54 #include <arm/samsung/exynos_reg.h> 55 #include <arm/samsung/exynos_var.h> 56 #include <arm/samsung/mct_reg.h> 57 #include <arm/samsung/smc.h> 58 59 #include <arm/cortex/pl310_var.h> 60 #include <arm/cortex/pl310_reg.h> 61 62 /* XXXNH */ 63 #include <evbarm/exynos/platform.h> 64 65 66 /* these variables are retrieved in start.S and stored in .data */ 67 uint32_t exynos_soc_id = 0; 68 uint32_t exynos_pop_id = 0; 69 70 /* cpu frequencies */ 71 struct cpu_freq { 72 uint64_t freq; 73 int P; 74 int M; 75 int S; 76 }; 77 78 79 #ifdef EXYNOS4 80 const struct cpu_freq cpu_freq_settings_exynos4[] = { 81 { 200, 3, 100, 2}, 82 { 300, 4, 200, 2}, 83 { 400, 3, 100, 1}, 84 { 500, 3, 125, 1}, 85 { 600, 4, 200, 1}, 86 { 700, 3, 175, 1}, 87 { 800, 3, 100, 0}, 88 { 900, 4, 150, 0}, 89 {1000, 3, 125, 0}, 90 {1100, 6, 275, 0}, 91 {1200, 4, 200, 0}, 92 {1300, 6, 325, 0}, 93 {1400, 3, 175, 0}, 94 {1600, 3, 200, 0}, 95 // {1704, 3, 213, 0}, 96 // {1800, 4, 300, 0}, 97 // {1920, 3, 240, 0}, 98 // {2000, 3, 250, 0}, 99 }; 100 #endif 101 102 103 #ifdef EXYNOS5 104 #define EXYNOS5_DEFAULT_ENTRY 7 105 const struct cpu_freq cpu_freq_settings_exynos5[] = { 106 { 200, 3, 100, 2}, 107 { 333, 4, 222, 2}, 108 { 400, 3, 100, 1}, 109 { 533, 12, 533, 1}, 110 { 600, 4, 200, 1}, 111 { 667, 7, 389, 1}, 112 { 800, 3, 100, 0}, 113 { 900, 4, 150, 0}, 114 {1000, 3, 125, 0}, 115 {1066, 12, 533, 0}, 116 {1200, 3, 150, 0}, 117 {1400, 3, 175, 0}, 118 {1600, 3, 200, 0}, 119 }; 120 #endif 121 122 static struct cpu_freq const *cpu_freq_settings = NULL; 123 static int ncpu_freq_settings = 0; 124 125 static int cpu_freq_target = 0; 126 #define NFRQS 18 127 static char sysctl_cpu_freqs_txt[NFRQS*5]; 128 129 bus_space_handle_t exynos_core_bsh; 130 bus_space_handle_t exynos_audiocore_bsh; 131 132 bus_space_handle_t exynos_wdt_bsh; 133 bus_space_handle_t exynos_pmu_bsh; 134 bus_space_handle_t exynos_cmu_bsh; 135 bus_space_handle_t exynos_cmu_apll_bsh; 136 bus_space_handle_t exynos_sysreg_bsh; 137 138 139 static int sysctl_cpufreq_target(SYSCTLFN_ARGS); 140 static int sysctl_cpufreq_current(SYSCTLFN_ARGS); 141 142 /* 143 * the early serial console 144 */ 145 #ifdef EXYNOS_CONSOLE_EARLY 146 147 #include "opt_sscom.h" 148 #include <arm/samsung/sscom_reg.h> 149 #include <arm/samsung/sscom_var.h> 150 #include <dev/cons.h> 151 152 static volatile uint8_t *uart_base; 153 154 #define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a)))) 155 156 static int 157 exynos_cngetc(dev_t dv) 158 { 159 if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0) 160 return -1; 161 162 return CON_REG(SSCOM_URXH); 163 } 164 165 static void 166 exynos_cnputc(dev_t dv, int c) 167 { 168 int timo = 150000; 169 170 while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0); 171 172 CON_REG(SSCOM_UTXH) = c & 0xff; 173 } 174 175 static struct consdev exynos_earlycons = { 176 .cn_putc = exynos_cnputc, 177 .cn_getc = exynos_cngetc, 178 .cn_pollc = nullcnpollc, 179 }; 180 #endif /* EXYNOS_CONSOLE_EARLY */ 181 182 183 #ifdef ARM_TRUSTZONE_FIRMWARE 184 int 185 exynos_do_idle(void) 186 { 187 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 188 189 return 0; 190 } 191 192 193 int 194 exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr) 195 { 196 /* XXX we need to map in iRAM space for this XXX */ 197 return 0; 198 } 199 200 201 int 202 exynos_cpu_boot(int cpu) 203 { 204 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 205 206 return 0; 207 } 208 209 210 #ifdef EXYNOS4 211 /* 212 * The latency values used below are `magic' and probably chosen empirically. 213 * For the 4210 variant the data latency is lower, a 0x110. This is currently 214 * not enforced. 215 * 216 * The prefetch values are also different for the revision 0 of the 217 * Exynos4412, but why? 218 */ 219 220 int 221 exynos4_l2cc_init(void) 222 { 223 const uint32_t tag_latency = 0x110; 224 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120; 225 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */ 226 PREFETCHCTL_DBLLINEF_EN | 227 PREFETCHCTL_INSTRPREF_EN | 228 PREFETCHCTL_DATAPREF_EN | 229 PREFETCHCTL_PREF_DROP_EN | 230 PREFETCHCTL_PREFETCH_OFFSET_7; 231 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */ 232 PREFETCHCTL_INSTRPREF_EN | 233 PREFETCHCTL_DATAPREF_EN | 234 PREFETCHCTL_PREFETCH_OFFSET_7; 235 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */ 236 AUXCTL_EARLY_BRESP_EN | 237 AUXCTL_I_PREFETCH | 238 AUXCTL_D_PREFETCH | 239 AUXCTL_NS_INT_ACC_CTL | 240 AUXCTL_NS_INT_LOCK_EN | 241 AUXCTL_SHARED_ATT_OVR | 242 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */ 243 AUXCTL_FULL_LINE_WR0; 244 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */ 245 AUXCTL_RSVD31 | 246 AUXCTL_EARLY_BRESP_EN | 247 AUXCTL_CACHE_REPL_RR | 248 249 AUXCTL_SH_ATTR_INV_ENA| 250 AUXCTL_EXCL_CACHE_CFG | 251 AUXCTL_ST_BUF_DEV_LIM_EN | 252 AUXCTL_HIPRO_SO_DEV_EN | 253 AUXCTL_FULL_LINE_WR0 | 254 0xffff; 255 uint32_t prefetch; 256 257 /* check the bitmaps are the same as the linux implementation uses */ 258 KASSERT(prefetch4412 == 0x71000007); 259 KASSERT(prefetch4412_r0 == 0x30000007); 260 KASSERT(aux_val == 0x7C470001); 261 KASSERT(aux_keepmask == 0xC200FFFF); 262 263 if (IS_EXYNOS4412_R0_P()) 264 prefetch = prefetch4412_r0; 265 else 266 prefetch = prefetch4412; /* newer than >= r1_0 */ 267 ; 268 269 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch); 270 exynos_smc(SMC_CMD_L2X0SETUP2, 271 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY, 272 aux_val, aux_keepmask); 273 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 274 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); 275 276 return 0; 277 } 278 #endif 279 #endif /* ARM_TRUSTZONE_FIRMWARE */ 280 281 282 void 283 exynos_sysctl_cpufreq_init(void) 284 { 285 const struct sysctlnode *node, *cpunode, *freqnode; 286 char *cpos; 287 int i, val; 288 int error; 289 290 memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt)); 291 cpos = sysctl_cpu_freqs_txt; 292 for (i = 0; i < ncpu_freq_settings; i++) { 293 val = cpu_freq_settings[i].freq; 294 snprintf(cpos, 6, "%d ", val); 295 cpos += (val < 1000) ? 4 : 5; 296 } 297 *cpos = 0; 298 299 error = sysctl_createv(NULL, 0, NULL, &node, 300 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 301 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 302 if (error) 303 printf("couldn't create `machdep' node\n"); 304 305 error = sysctl_createv(NULL, 0, &node, &cpunode, 306 0, CTLTYPE_NODE, "cpu", NULL, 307 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 308 if (error) 309 printf("couldn't create `cpu' node\n"); 310 311 error = sysctl_createv(NULL, 0, &cpunode, &freqnode, 312 0, CTLTYPE_NODE, "frequency", NULL, 313 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 314 if (error) 315 printf("couldn't create `frequency' node\n"); 316 317 error = sysctl_createv(NULL, 0, &freqnode, &node, 318 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 319 sysctl_cpufreq_target, 0, &cpu_freq_target, 0, 320 CTL_CREATE, CTL_EOL); 321 if (error) 322 printf("couldn't create `target' node\n"); 323 324 error = sysctl_createv(NULL, 0, &freqnode, &node, 325 0, CTLTYPE_INT, "current", NULL, 326 sysctl_cpufreq_current, 0, NULL, 0, 327 CTL_CREATE, CTL_EOL); 328 if (error) 329 printf("couldn't create `current' node\n"); 330 331 error = sysctl_createv(NULL, 0, &freqnode, &node, 332 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 333 NULL, 0, sysctl_cpu_freqs_txt, 0, 334 CTL_CREATE, CTL_EOL); 335 if (error) 336 printf("couldn't create `available' node\b"); 337 } 338 339 340 uint64_t 341 exynos_get_cpufreq(void) 342 { 343 uint32_t regval; 344 uint32_t freq; 345 346 regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_apll_bsh, 347 PLL_CON0_OFFSET); 348 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); 349 350 return freq; 351 } 352 353 354 static void 355 exynos_set_cpufreq(const struct cpu_freq *freqreq) 356 { 357 struct cpu_info *ci; 358 uint32_t regval; 359 int M, P, S; 360 int cii; 361 362 M = freqreq->M; 363 P = freqreq->P; 364 S = freqreq->S; 365 366 regval = __SHIFTIN(M, PLL_CON0_M) | 367 __SHIFTIN(P, PLL_CON0_P) | 368 __SHIFTIN(S, PLL_CON0_S); 369 370 /* enable PPL and write config */ 371 regval |= PLL_CON0_ENABLE; 372 bus_space_write_4(&exynos_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET, 373 regval); 374 375 /* update our cycle counter i.e. our CPU frequency for all CPUs */ 376 for (CPU_INFO_FOREACH(cii, ci)) { 377 ci->ci_data.cpu_cc_freq = exynos_get_cpufreq(); 378 } 379 } 380 381 382 static int 383 sysctl_cpufreq_target(SYSCTLFN_ARGS) 384 { 385 struct sysctlnode node; 386 uint32_t t, curfreq, minfreq, maxfreq; 387 int i, best_i, diff; 388 int error; 389 390 curfreq = exynos_get_cpufreq() / (1000*1000); 391 t = *(int *)rnode->sysctl_data; 392 if (t == 0) 393 t = curfreq; 394 395 node = *rnode; 396 node.sysctl_data = &t; 397 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 398 if (error || newp == NULL) 399 return error; 400 401 minfreq = cpu_freq_settings[0].freq; 402 maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq; 403 404 if ((t < minfreq) || (t > maxfreq)) 405 return EINVAL; 406 407 if (t == curfreq) { 408 *(int *)rnode->sysctl_data = t; 409 return 0; 410 } 411 412 diff = maxfreq; 413 best_i = -1; 414 for (i = 0; i < ncpu_freq_settings; i++) { 415 if (abs(t - cpu_freq_settings[i].freq) <= diff) { 416 diff = labs(t - cpu_freq_settings[i].freq); 417 best_i = i; 418 } 419 } 420 if (best_i < 0) 421 return EINVAL; 422 423 exynos_set_cpufreq(&cpu_freq_settings[best_i]); 424 425 *(int *)rnode->sysctl_data = t; 426 return 0; 427 } 428 429 430 static int 431 sysctl_cpufreq_current(SYSCTLFN_ARGS) 432 { 433 struct sysctlnode node = *rnode; 434 uint32_t freq; 435 436 freq = exynos_get_cpufreq() / (1000*1000); 437 node.sysctl_data = &freq; 438 439 return sysctl_lookup(SYSCTLFN_CALL(&node)); 440 } 441 442 443 #ifdef VERBOSE_INIT_ARM 444 #define DUMP_PLL(v, var) \ 445 reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\ 446 regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_bsh, reg); \ 447 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \ 448 printf("%8s at %d Mhz\n", #var, freq/(1000*1000)); 449 450 451 static void 452 exynos_dump_clocks(void) 453 { 454 uint32_t reg = 0; 455 uint32_t regval; 456 uint32_t freq; 457 458 printf("Initial PLL settings\n"); 459 #ifdef EXYNOS4 460 DUMP_PLL(4, APLL); 461 DUMP_PLL(4, MPLL); 462 DUMP_PLL(4, EPLL); 463 DUMP_PLL(4, VPLL); 464 #endif 465 #ifdef EXYNOS5 466 DUMP_PLL(5, APLL); 467 DUMP_PLL(5, MPLL); 468 DUMP_PLL(5, KPLL); 469 DUMP_PLL(5, DPLL); 470 DUMP_PLL(5, VPLL); 471 DUMP_PLL(5, CPLL); 472 DUMP_PLL(5, GPLL); 473 DUMP_PLL(5, BPLL); 474 #endif 475 } 476 #undef DUMP_PLL 477 #endif 478 479 480 /* XXX clock stuff needs major work XXX */ 481 482 void 483 exynos_clocks_bootstrap(void) 484 { 485 KASSERT(ncpu_freq_settings != 0); 486 KASSERT(ncpu_freq_settings < NFRQS); 487 int fsel; 488 489 #ifdef VERBOSE_INIT_ARM 490 exynos_dump_clocks(); 491 #endif 492 493 /* set (max) cpufreq */ 494 fsel = ncpu_freq_settings-1; 495 496 #ifdef EXYNOS5 497 /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */ 498 fsel = EXYNOS5_DEFAULT_ENTRY; 499 #endif 500 501 exynos_set_cpufreq(&cpu_freq_settings[fsel]); 502 503 /* set external USB frequency to XCLKOUT */ 504 exynos_init_clkout_for_usb(); 505 } 506 507 508 void 509 exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) 510 { 511 int error; 512 size_t core_size, audiocore_size; 513 bus_addr_t audiocore_pbase; 514 bus_addr_t audiocore_vbase __diagused; 515 bus_addr_t exynos_wdt_offset; 516 bus_addr_t exynos_pmu_offset; 517 bus_addr_t exynos_sysreg_offset; 518 bus_addr_t exynos_cmu_apll_offset; 519 520 /* set up early console so we can use printf() and friends */ 521 #ifdef EXYNOS_CONSOLE_EARLY 522 uart_base = (volatile uint8_t *) uartbase; 523 cn_tab = &exynos_earlycons; 524 printf("Exynos early console operational\n\n"); 525 #endif 526 527 #ifdef EXYNOS4 528 core_size = EXYNOS4_CORE_SIZE; 529 audiocore_size = EXYNOS4_AUDIOCORE_SIZE; 530 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; 531 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; 532 exynos_wdt_offset = EXYNOS4_WDT_OFFSET; 533 exynos_pmu_offset = EXYNOS4_PMU_OFFSET; 534 exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET; 535 exynos_cmu_apll_offset = EXYNOS4_CMU_APLL; 536 537 cpu_freq_settings = cpu_freq_settings_exynos4; 538 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); 539 #endif 540 541 #ifdef EXYNOS5 542 core_size = EXYNOS5_CORE_SIZE; 543 audiocore_size = EXYNOS5_AUDIOCORE_SIZE; 544 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; 545 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; 546 exynos_wdt_offset = EXYNOS5_WDT_OFFSET; 547 exynos_pmu_offset = EXYNOS5_PMU_OFFSET; 548 exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET; 549 exynos_cmu_apll_offset = EXYNOS5_CMU_APLL; 550 551 cpu_freq_settings = cpu_freq_settings_exynos5; 552 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); 553 #endif 554 555 /* map in the exynos io registers */ 556 error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE, 557 core_size, 0, &exynos_core_bsh); 558 if (error) 559 panic("%s: failed to map in Exynos SFR registers: %d", 560 __func__, error); 561 KASSERT(exynos_core_bsh == iobase); 562 563 error = bus_space_map(&exynos_bs_tag, audiocore_pbase, 564 audiocore_size, 0, &exynos_audiocore_bsh); 565 if (error) 566 panic("%s: failed to map in Exynos audio SFR registers: %d", 567 __func__, error); 568 KASSERT(exynos_audiocore_bsh == audiocore_vbase); 569 570 /* map in commonly used subregions and common used register banks */ 571 error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 572 exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh); 573 if (error) 574 panic("%s: failed to subregion wdt registers: %d", 575 __func__, error); 576 577 error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 578 exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh); 579 if (error) 580 panic("%s: failed to subregion pmu registers: %d", 581 __func__, error); 582 583 exynos_cmu_bsh = exynos_core_bsh; 584 bus_space_subregion(&exynos_bs_tag, exynos_core_bsh, 585 exynos_sysreg_offset, EXYNOS_BLOCK_SIZE, 586 &exynos_sysreg_bsh); 587 if (error) 588 panic("%s: failed to subregion sysreg registers: %d", 589 __func__, error); 590 591 error = bus_space_subregion(&exynos_bs_tag, exynos_cmu_bsh, 592 exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh); 593 if (error) 594 panic("%s: failed to subregion cmu apll registers: %d", 595 __func__, error); 596 597 /* init bus dma tags */ 598 exynos_dma_bootstrap(physmem * PAGE_SIZE); 599 600 /* gpio bootstrapping delayed */ 601 } 602 603 604 void 605 exynos_device_register(device_t self, void *aux) 606 { 607 if (device_is_a(self, "armperiph") 608 && device_is_a(device_parent(self), "mainbus")) { 609 /* 610 * XXX KLUDGE ALERT XXX 611 * The iot mainbus supplies is completely wrong since it scales 612 * addresses by 2. The simplest remedy is to replace with our 613 * bus space used for the armcore registers (which armperiph uses). 614 */ 615 struct mainbus_attach_args * const mb = aux; 616 mb->mb_iot = &exynos_bs_tag; 617 return; 618 } 619 if (device_is_a(self, "armgic") 620 && device_is_a(device_parent(self), "armperiph")) { 621 /* 622 * The Exynos4420 armgic is located at a different location! 623 */ 624 625 extern uint32_t exynos_soc_id; 626 627 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { 628 #ifdef EXYNOS5 629 case 0xe5410: 630 /* offsets not changed on matt's request */ 631 #if 0 632 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 633 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 634 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 635 #endif 636 break; 637 case 0xe5422: { 638 struct mpcore_attach_args * const mpcaa = aux; 639 640 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 641 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 642 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 643 break; 644 } 645 #endif 646 #ifdef EXYNOS4 647 case 0xe4410: 648 case 0xe4412: { 649 struct mpcore_attach_args * const mpcaa = aux; 650 651 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 652 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; 653 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; 654 break; 655 } 656 #endif 657 default: 658 panic("%s: unknown SoC product id %#x", __func__, 659 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); 660 } 661 return; 662 } 663 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { 664 #ifdef EXYNOS5 665 /* 666 * The global timer is dependent on the MCT running. 667 */ 668 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; 669 uint32_t v = bus_space_read_4(&exynos_bs_tag, exynos_core_bsh, 670 o); 671 v |= G_TCON_START; 672 bus_space_write_4(&exynos_bs_tag, exynos_core_bsh, o, v); 673 #endif 674 /* 675 * The frequencies of the timers are the reference 676 * frequency. 677 */ 678 prop_dictionary_set_uint32(device_properties(self), 679 "frequency", EXYNOS_F_IN_FREQ); 680 return; 681 } 682 683 exyo_device_register(self, aux); 684 } 685 686 687 void 688 exynos_device_register_post_config(device_t self, void *aux) 689 { 690 exyo_device_register_post_config(self, aux); 691 } 692 693 void 694 exynos_usb_soc_powerup(void) 695 { 696 /* XXX 5422 XXX */ 697 } 698 699 700 /* 701 * USB Phy SoC dependent handling 702 */ 703 704 /* XXX 5422 not handled since its unknown how it handles this XXX*/ 705 static void 706 exynos_usb2_set_isolation(bool on) 707 { 708 uint32_t en_mask, regval; 709 bus_addr_t reg; 710 711 /* enable PHY */ 712 reg = EXYNOS_PMU_USB_PHY_CTRL; 713 714 if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) { 715 /* set usbhost mode */ 716 regval = on ? 0 : USB20_PHY_HOST_LINK_EN; 717 bus_space_write_4(&exynos_bs_tag, exynos_sysreg_bsh, 718 EXYNOS5_SYSREG_USB20_PHY_TYPE, regval); 719 reg = EXYNOS_PMU_USBHOST_PHY_CTRL; 720 } 721 722 /* do enable PHY */ 723 en_mask = PMU_PHY_ENABLE; 724 regval = bus_space_read_4(&exynos_bs_tag, exynos_pmu_bsh, reg); 725 regval = on ? regval & ~en_mask : regval | en_mask; 726 727 bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh, 728 reg, regval); 729 730 if (IS_EXYNOS4X12_P()) { 731 bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh, 732 EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval); 733 bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh, 734 EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval); 735 } 736 } 737 738 739 #ifdef EXYNOS4 740 static void 741 exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 742 { 743 uint32_t phypwr, rstcon, clkreg; 744 745 /* write clock value */ 746 clkreg = FSEL_CLKSEL_24M; 747 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 748 USB_PHYCLK, clkreg); 749 750 /* set device and host to normal */ 751 phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 752 USB_PHYPWR); 753 754 /* enable analog, enable otg, unsleep phy0 (host) */ 755 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0; 756 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 757 USB_PHYPWR, phypwr); 758 759 if (IS_EXYNOS4X12_P()) { 760 /* enable hsic0 (host), enable hsic1 and phy1 (otg) */ 761 phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 762 USB_PHYPWR); 763 phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 | 764 PHYPWR_NORMAL_MASK_HSIC1 | 765 PHYPWR_NORMAL_MASK_PHY1); 766 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 767 USB_PHYPWR, phypwr); 768 } 769 770 /* reset both phy and link of device */ 771 rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 772 USB_RSTCON); 773 rstcon |= RSTCON_DEVPHY_SWRST; 774 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 775 USB_RSTCON, rstcon); 776 DELAY(10000); 777 rstcon &= ~RSTCON_DEVPHY_SWRST; 778 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 779 USB_RSTCON, rstcon); 780 781 if (IS_EXYNOS4X12_P()) { 782 /* reset both phy and link of host */ 783 rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 784 USB_RSTCON); 785 rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST; 786 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 787 USB_RSTCON, rstcon); 788 DELAY(10000); 789 rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST); 790 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 791 USB_RSTCON, rstcon); 792 } 793 794 /* wait for everything to be initialized */ 795 DELAY(80000); 796 } 797 #endif 798 799 800 #ifdef EXYNOS5 801 static void 802 exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 803 { 804 uint32_t phyhost; //, phyotg; 805 uint32_t phyhsic; 806 uint32_t ehcictrl, ohcictrl; 807 808 /* host configuration: */ 809 phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 810 USB_PHY_HOST_CTRL0); 811 812 /* host phy reference clock; assumption its 24 MHz now */ 813 phyhost &= ~HOST_CTRL0_FSEL_MASK; 814 phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK); 815 816 /* enable normal mode of operation */ 817 phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); 818 819 /* host phy reset */ 820 phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL | 821 HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | 822 HOST_CTRL0_FORCESLEEP); 823 824 /* host link reset */ 825 phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST | 826 HOST_CTRL0_COMMONON_N; 827 /* do the reset */ 828 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 829 phyhost); 830 DELAY(10000); 831 832 phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST); 833 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 834 phyhost); 835 836 /* HSIC control */ 837 phyhsic = 838 __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) | 839 __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) | 840 HSIC_CTRL_PHY_SWRST; 841 842 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 843 phyhsic); 844 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 845 phyhsic); 846 DELAY(10); 847 848 phyhsic &= ~HSIC_CTRL_PHY_SWRST; 849 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 850 phyhsic); 851 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 852 phyhsic); 853 DELAY(80); 854 855 #if 0 856 /* otg configuration: */ 857 phyotg = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 858 USB_PHY_OTG_SYS); 859 860 /* otg phy refrence clock: assumption its 24 Mhz now */ 861 phyotg &= ~OTG_SYS_FSEL_MASK; 862 phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M); 863 864 /* enable normal mode of operation */ 865 phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP | 866 OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK | 867 OTG_SYS_COMMON_ON); 868 869 /* OTG phy and link reset */ 870 phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST | 871 OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK; 872 873 /* do the reset */ 874 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 875 USB_PHY_OTG_SYS, phyotg); 876 DELAY(10000); 877 phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG | 878 OTG_SYS_PHYLINK_SWRST); 879 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 880 USB_PHY_OTG_SYS, phyotg); 881 #endif 882 883 /* enable EHCI DMA burst: */ 884 ehcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 885 USB_PHY_HOST_EHCICTRL); 886 ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN | 887 HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 | 888 HOST_EHCICTRL_ENA_INCR16; 889 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 890 USB_PHY_HOST_EHCICTRL, ehcictrl); 891 892 /* Set OHCI suspend */ 893 ohcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh, 894 USB_PHY_HOST_OHCICTRL); 895 ohcictrl |= HOST_OHCICTRL_SUSPLGCY; 896 bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, 897 USB_PHY_HOST_OHCICTRL, ohcictrl); 898 } 899 900 901 static void 902 exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 903 { 904 aprint_error("%s not implemented\n", __func__); 905 } 906 #endif 907 908 909 void 910 exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh) 911 { 912 /* disable phy isolation */ 913 exynos_usb2_set_isolation(false); 914 915 #ifdef EXYNOS4 916 exynos4_usb2phy_enable(usb2phy_bsh); 917 #endif 918 #ifdef EXYNOS5 919 if (IS_EXYNOS5410_P()) { 920 exynos5410_usb2phy_enable(usb2phy_bsh); 921 /* TBD: USB3 phy init */ 922 } else if (IS_EXYNOS5422_P()) { 923 exynos5422_usb2phy_enable(usb2phy_bsh); 924 /* TBD: USB3 phy init */ 925 } 926 #endif 927 } 928 929 930
Indexes created Wed Oct 01 15:09:59 GMT 2025