exynos_soc.c revision 1.33
1 /* $NetBSD: exynos_soc.c,v 1.33 2018/07/05 13:11:58 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_exynos.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.33 2018/07/05 13:11:58 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 42 #include <prop/proplib.h> 43 44 #include <net/if.h> 45 #include <net/if_ether.h> 46 47 #include <arm/locore.h> 48 49 #include <arm/mainbus/mainbus.h> 50 #include <arm/cortex/mpcore_var.h> 51 52 #include <arm/samsung/exynos_reg.h> 53 #include <arm/samsung/exynos_var.h> 54 #include <arm/samsung/mct_reg.h> 55 #include <arm/samsung/smc.h> 56 57 #include <arm/cortex/pl310_var.h> 58 #include <arm/cortex/pl310_reg.h> 59 60 /* XXXNH */ 61 #include <evbarm/exynos/platform.h> 62 63 64 /* these variables are retrieved in start.S and stored in .data */ 65 uint32_t exynos_soc_id = 0; 66 uint32_t exynos_pop_id = 0; 67 68 /* cpu frequencies */ 69 struct cpu_freq { 70 uint64_t freq; 71 int P; 72 int M; 73 int S; 74 }; 75 76 77 #ifdef SOC_EXYNOS4 78 const struct cpu_freq cpu_freq_settings_exynos4[] = { 79 { 200, 3, 100, 2}, 80 { 300, 4, 200, 2}, 81 { 400, 3, 100, 1}, 82 { 500, 3, 125, 1}, 83 { 600, 4, 200, 1}, 84 { 700, 3, 175, 1}, 85 { 800, 3, 100, 0}, 86 { 900, 4, 150, 0}, 87 {1000, 3, 125, 0}, 88 {1100, 6, 275, 0}, 89 {1200, 4, 200, 0}, 90 {1300, 6, 325, 0}, 91 {1400, 3, 175, 0}, 92 {1600, 3, 200, 0}, 93 // {1704, 3, 213, 0}, 94 // {1800, 4, 300, 0}, 95 // {1920, 3, 240, 0}, 96 // {2000, 3, 250, 0}, 97 }; 98 #endif 99 100 101 #ifdef SOC_EXYNOS5 102 #define EXYNOS5_DEFAULT_ENTRY 7 103 const struct cpu_freq cpu_freq_settings_exynos5[] = { 104 { 200, 3, 100, 2}, 105 { 333, 4, 222, 2}, 106 { 400, 3, 100, 1}, 107 { 533, 12, 533, 1}, 108 { 600, 4, 200, 1}, 109 { 667, 7, 389, 1}, 110 { 800, 3, 100, 0}, 111 { 900, 4, 150, 0}, 112 {1000, 3, 125, 0}, 113 {1066, 12, 533, 0}, 114 {1200, 3, 150, 0}, 115 {1400, 3, 175, 0}, 116 {1600, 3, 200, 0}, 117 }; 118 #endif 119 120 static struct cpu_freq const *cpu_freq_settings = NULL; 121 static int ncpu_freq_settings = 0; 122 123 static int cpu_freq_target = 0; 124 #define NFRQS 18 125 static char sysctl_cpu_freqs_txt[NFRQS*5]; 126 127 bus_space_handle_t exynos_core_bsh; 128 bus_space_handle_t exynos_audiocore_bsh; 129 130 bus_space_handle_t exynos_wdt_bsh; 131 bus_space_handle_t exynos_pmu_bsh; 132 bus_space_handle_t exynos_cmu_bsh; 133 bus_space_handle_t exynos_cmu_apll_bsh; 134 bus_space_handle_t exynos_sysreg_bsh; 135 136 137 static int sysctl_cpufreq_target(SYSCTLFN_ARGS); 138 static int sysctl_cpufreq_current(SYSCTLFN_ARGS); 139 140 #ifdef ARM_TRUSTZONE_FIRMWARE 141 int 142 exynos_do_idle(void) 143 { 144 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 145 146 return 0; 147 } 148 149 150 int 151 exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr) 152 { 153 /* XXX we need to map in iRAM space for this XXX */ 154 return 0; 155 } 156 157 158 int 159 exynos_cpu_boot(int cpu) 160 { 161 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 162 163 return 0; 164 } 165 166 167 #ifdef SOC_EXYNOS4 168 /* 169 * The latency values used below are `magic' and probably chosen empirically. 170 * For the 4210 variant the data latency is lower, a 0x110. This is currently 171 * not enforced. 172 * 173 * The prefetch values are also different for the revision 0 of the 174 * Exynos4412, but why? 175 */ 176 177 int 178 exynos4_l2cc_init(void) 179 { 180 const uint32_t tag_latency = 0x110; 181 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120; 182 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */ 183 PREFETCHCTL_DBLLINEF_EN | 184 PREFETCHCTL_INSTRPREF_EN | 185 PREFETCHCTL_DATAPREF_EN | 186 PREFETCHCTL_PREF_DROP_EN | 187 PREFETCHCTL_PREFETCH_OFFSET_7; 188 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */ 189 PREFETCHCTL_INSTRPREF_EN | 190 PREFETCHCTL_DATAPREF_EN | 191 PREFETCHCTL_PREFETCH_OFFSET_7; 192 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */ 193 AUXCTL_EARLY_BRESP_EN | 194 AUXCTL_I_PREFETCH | 195 AUXCTL_D_PREFETCH | 196 AUXCTL_NS_INT_ACC_CTL | 197 AUXCTL_NS_INT_LOCK_EN | 198 AUXCTL_SHARED_ATT_OVR | 199 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */ 200 AUXCTL_FULL_LINE_WR0; 201 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */ 202 AUXCTL_RSVD31 | 203 AUXCTL_EARLY_BRESP_EN | 204 AUXCTL_CACHE_REPL_RR | 205 206 AUXCTL_SH_ATTR_INV_ENA| 207 AUXCTL_EXCL_CACHE_CFG | 208 AUXCTL_ST_BUF_DEV_LIM_EN | 209 AUXCTL_HIPRO_SO_DEV_EN | 210 AUXCTL_FULL_LINE_WR0 | 211 0xffff; 212 uint32_t prefetch; 213 214 /* check the bitmaps are the same as the linux implementation uses */ 215 KASSERT(prefetch4412 == 0x71000007); 216 KASSERT(prefetch4412_r0 == 0x30000007); 217 KASSERT(aux_val == 0x7C470001); 218 KASSERT(aux_keepmask == 0xC200FFFF); 219 220 if (IS_EXYNOS4412_R0_P()) 221 prefetch = prefetch4412_r0; 222 else 223 prefetch = prefetch4412; /* newer than >= r1_0 */ 224 ; 225 226 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch); 227 exynos_smc(SMC_CMD_L2X0SETUP2, 228 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY, 229 aux_val, aux_keepmask); 230 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 231 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); 232 233 return 0; 234 } 235 #endif 236 #endif /* ARM_TRUSTZONE_FIRMWARE */ 237 238 239 void 240 exynos_sysctl_cpufreq_init(void) 241 { 242 const struct sysctlnode *node, *cpunode, *freqnode; 243 char *cpos; 244 int i, val; 245 int error; 246 247 memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt)); 248 cpos = sysctl_cpu_freqs_txt; 249 for (i = 0; i < ncpu_freq_settings; i++) { 250 val = cpu_freq_settings[i].freq; 251 snprintf(cpos, 6, "%d ", val); 252 cpos += (val < 1000) ? 4 : 5; 253 } 254 *cpos = 0; 255 256 error = sysctl_createv(NULL, 0, NULL, &node, 257 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 258 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 259 if (error) 260 printf("couldn't create `machdep' node\n"); 261 262 error = sysctl_createv(NULL, 0, &node, &cpunode, 263 0, CTLTYPE_NODE, "cpu", NULL, 264 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 265 if (error) 266 printf("couldn't create `cpu' node\n"); 267 268 error = sysctl_createv(NULL, 0, &cpunode, &freqnode, 269 0, CTLTYPE_NODE, "frequency", NULL, 270 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 271 if (error) 272 printf("couldn't create `frequency' node\n"); 273 274 error = sysctl_createv(NULL, 0, &freqnode, &node, 275 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 276 sysctl_cpufreq_target, 0, &cpu_freq_target, 0, 277 CTL_CREATE, CTL_EOL); 278 if (error) 279 printf("couldn't create `target' node\n"); 280 281 error = sysctl_createv(NULL, 0, &freqnode, &node, 282 0, CTLTYPE_INT, "current", NULL, 283 sysctl_cpufreq_current, 0, NULL, 0, 284 CTL_CREATE, CTL_EOL); 285 if (error) 286 printf("couldn't create `current' node\n"); 287 288 error = sysctl_createv(NULL, 0, &freqnode, &node, 289 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 290 NULL, 0, sysctl_cpu_freqs_txt, 0, 291 CTL_CREATE, CTL_EOL); 292 if (error) 293 printf("couldn't create `available' node\b"); 294 } 295 296 297 uint64_t 298 exynos_get_cpufreq(void) 299 { 300 uint32_t regval; 301 uint32_t freq; 302 303 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, 304 PLL_CON0_OFFSET); 305 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); 306 307 return freq; 308 } 309 310 311 static void 312 exynos_set_cpufreq(const struct cpu_freq *freqreq) 313 { 314 struct cpu_info *ci; 315 uint32_t regval; 316 int M, P, S; 317 int cii; 318 319 M = freqreq->M; 320 P = freqreq->P; 321 S = freqreq->S; 322 323 regval = __SHIFTIN(M, PLL_CON0_M) | 324 __SHIFTIN(P, PLL_CON0_P) | 325 __SHIFTIN(S, PLL_CON0_S); 326 327 /* enable PPL and write config */ 328 regval |= PLL_CON0_ENABLE; 329 bus_space_write_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET, 330 regval); 331 332 /* update our cycle counter i.e. our CPU frequency for all CPUs */ 333 for (CPU_INFO_FOREACH(cii, ci)) { 334 ci->ci_data.cpu_cc_freq = exynos_get_cpufreq(); 335 } 336 } 337 338 339 static int 340 sysctl_cpufreq_target(SYSCTLFN_ARGS) 341 { 342 struct sysctlnode node; 343 uint32_t t, curfreq, minfreq, maxfreq; 344 int i, best_i, diff; 345 int error; 346 347 curfreq = exynos_get_cpufreq() / (1000*1000); 348 t = *(int *)rnode->sysctl_data; 349 if (t == 0) 350 t = curfreq; 351 352 node = *rnode; 353 node.sysctl_data = &t; 354 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 355 if (error || newp == NULL) 356 return error; 357 358 minfreq = cpu_freq_settings[0].freq; 359 maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq; 360 361 if ((t < minfreq) || (t > maxfreq)) 362 return EINVAL; 363 364 if (t == curfreq) { 365 *(int *)rnode->sysctl_data = t; 366 return 0; 367 } 368 369 diff = maxfreq; 370 best_i = -1; 371 for (i = 0; i < ncpu_freq_settings; i++) { 372 if (abs(t - cpu_freq_settings[i].freq) <= diff) { 373 diff = labs(t - cpu_freq_settings[i].freq); 374 best_i = i; 375 } 376 } 377 if (best_i < 0) 378 return EINVAL; 379 380 exynos_set_cpufreq(&cpu_freq_settings[best_i]); 381 382 *(int *)rnode->sysctl_data = t; 383 return 0; 384 } 385 386 387 static int 388 sysctl_cpufreq_current(SYSCTLFN_ARGS) 389 { 390 struct sysctlnode node = *rnode; 391 uint32_t freq; 392 393 freq = exynos_get_cpufreq() / (1000*1000); 394 node.sysctl_data = &freq; 395 396 return sysctl_lookup(SYSCTLFN_CALL(&node)); 397 } 398 399 400 #ifdef VERBOSE_INIT_ARM 401 #define DUMP_PLL(v, var) \ 402 reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\ 403 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \ 404 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \ 405 printf("%8s at %d Mhz\n", #var, freq/(1000*1000)); 406 407 408 static void 409 exynos_dump_clocks(void) 410 { 411 uint32_t reg = 0; 412 uint32_t regval; 413 uint32_t freq; 414 415 printf("Initial PLL settings\n"); 416 #ifdef SOC_EXYNOS4 417 DUMP_PLL(4, APLL); 418 DUMP_PLL(4, MPLL); 419 DUMP_PLL(4, EPLL); 420 DUMP_PLL(4, VPLL); 421 #endif 422 #ifdef SOC_EXYNOS5 423 DUMP_PLL(5, APLL); 424 DUMP_PLL(5, MPLL); 425 DUMP_PLL(5, KPLL); 426 DUMP_PLL(5, DPLL); 427 DUMP_PLL(5, VPLL); 428 DUMP_PLL(5, CPLL); 429 DUMP_PLL(5, GPLL); 430 DUMP_PLL(5, BPLL); 431 #endif 432 } 433 #undef DUMP_PLL 434 #endif 435 436 437 /* XXX clock stuff needs major work XXX */ 438 439 void 440 exynos_init_clkout_for_usb(void) 441 { 442 /* Select XUSBXTI as source for CLKOUT */ 443 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 444 EXYNOS_PMU_DEBUG_CLKOUT, 0x1000); 445 } 446 447 448 void 449 exynos_clocks_bootstrap(void) 450 { 451 KASSERT(ncpu_freq_settings != 0); 452 KASSERT(ncpu_freq_settings < NFRQS); 453 int fsel; 454 455 #ifdef VERBOSE_INIT_ARM 456 exynos_dump_clocks(); 457 #endif 458 459 /* set (max) cpufreq */ 460 fsel = ncpu_freq_settings-1; 461 462 #ifdef SOC_EXYNOS5 463 /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */ 464 fsel = EXYNOS5_DEFAULT_ENTRY; 465 #endif 466 467 exynos_set_cpufreq(&cpu_freq_settings[fsel]); 468 469 /* set external USB frequency to XCLKOUT */ 470 exynos_init_clkout_for_usb(); 471 } 472 473 474 void 475 exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) 476 { 477 int error; 478 size_t core_size, audiocore_size; 479 bus_addr_t audiocore_pbase; 480 bus_addr_t audiocore_vbase __diagused; 481 bus_addr_t exynos_wdt_offset; 482 bus_addr_t exynos_pmu_offset; 483 bus_addr_t exynos_sysreg_offset; 484 bus_addr_t exynos_cmu_apll_offset; 485 486 /* set up early console so we can use printf() and friends */ 487 #ifdef EXYNOS_CONSOLE_EARLY 488 uart_base = (volatile uint8_t *) uartbase; 489 cn_tab = &exynos_earlycons; 490 printf("Exynos early console operational\n\n"); 491 #endif 492 493 #ifdef SOC_EXYNOS4 494 core_size = EXYNOS4_CORE_SIZE; 495 audiocore_size = EXYNOS4_AUDIOCORE_SIZE; 496 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; 497 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; 498 exynos_wdt_offset = EXYNOS4_WDT_OFFSET; 499 exynos_pmu_offset = EXYNOS4_PMU_OFFSET; 500 exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET; 501 exynos_cmu_apll_offset = EXYNOS4_CMU_APLL; 502 503 cpu_freq_settings = cpu_freq_settings_exynos4; 504 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); 505 #endif 506 507 #ifdef SOC_EXYNOS5 508 core_size = EXYNOS5_CORE_SIZE; 509 audiocore_size = EXYNOS5_AUDIOCORE_SIZE; 510 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; 511 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; 512 exynos_wdt_offset = EXYNOS5_WDT_OFFSET; 513 exynos_pmu_offset = EXYNOS5_PMU_OFFSET; 514 exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET; 515 exynos_cmu_apll_offset = EXYNOS5_CMU_APLL; 516 517 cpu_freq_settings = cpu_freq_settings_exynos5; 518 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); 519 #endif 520 521 /* map in the exynos io registers */ 522 error = bus_space_map(&armv7_generic_bs_tag, EXYNOS_CORE_PBASE, 523 core_size, 0, &exynos_core_bsh); 524 if (error) 525 panic("%s: failed to map in Exynos SFR registers: %d", 526 __func__, error); 527 KASSERT(exynos_core_bsh == iobase); 528 529 error = bus_space_map(&armv7_generic_bs_tag, audiocore_pbase, 530 audiocore_size, 0, &exynos_audiocore_bsh); 531 if (error) 532 panic("%s: failed to map in Exynos audio SFR registers: %d", 533 __func__, error); 534 KASSERT(exynos_audiocore_bsh == audiocore_vbase); 535 536 /* map in commonly used subregions and common used register banks */ 537 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 538 exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh); 539 if (error) 540 panic("%s: failed to subregion wdt registers: %d", 541 __func__, error); 542 543 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 544 exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh); 545 if (error) 546 panic("%s: failed to subregion pmu registers: %d", 547 __func__, error); 548 549 exynos_cmu_bsh = exynos_core_bsh; 550 bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 551 exynos_sysreg_offset, EXYNOS_BLOCK_SIZE, 552 &exynos_sysreg_bsh); 553 if (error) 554 panic("%s: failed to subregion sysreg registers: %d", 555 __func__, error); 556 557 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_cmu_bsh, 558 exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh); 559 if (error) 560 panic("%s: failed to subregion cmu apll registers: %d", 561 __func__, error); 562 563 /* gpio bootstrapping delayed */ 564 } 565 566 567 void 568 exynos_device_register(device_t self, void *aux) 569 { 570 if (device_is_a(self, "armperiph") 571 && device_is_a(device_parent(self), "mainbus")) { 572 /* 573 * XXX KLUDGE ALERT XXX 574 * The iot mainbus supplies is completely wrong since it scales 575 * addresses by 2. The simplest remedy is to replace with our 576 * bus space used for the armcore registers (which armperiph uses). 577 */ 578 struct mainbus_attach_args * const mb = aux; 579 mb->mb_iot = &armv7_generic_bs_tag; 580 return; 581 } 582 if (device_is_a(self, "armgic") 583 && device_is_a(device_parent(self), "armperiph")) { 584 /* 585 * The Exynos4420 armgic is located at a different location! 586 */ 587 588 extern uint32_t exynos_soc_id; 589 590 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { 591 #ifdef SOC_EXYNOS5 592 case 0xe5410: 593 /* offsets not changed on matt's request */ 594 #if 0 595 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 596 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 597 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 598 #endif 599 break; 600 case 0xe5422: { 601 struct mpcore_attach_args * const mpcaa = aux; 602 603 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 604 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 605 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 606 break; 607 } 608 #endif 609 #ifdef SOC_EXYNOS4 610 case 0xe4410: 611 case 0xe4412: { 612 struct mpcore_attach_args * const mpcaa = aux; 613 614 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 615 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; 616 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; 617 break; 618 } 619 #endif 620 default: 621 panic("%s: unknown SoC product id %#x", __func__, 622 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); 623 } 624 return; 625 } 626 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { 627 #ifdef SOC_EXYNOS5 628 /* 629 * The global timer is dependent on the MCT running. 630 */ 631 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; 632 uint32_t v = bus_space_read_4(&armv7_generic_bs_tag, exynos_core_bsh, 633 o); 634 v |= G_TCON_START; 635 bus_space_write_4(&armv7_generic_bs_tag, exynos_core_bsh, o, v); 636 #endif 637 /* 638 * The frequencies of the timers are the reference 639 * frequency. 640 */ 641 prop_dictionary_set_uint32(device_properties(self), 642 "frequency", EXYNOS_F_IN_FREQ); 643 return; 644 } 645 } 646 647 648 void 649 exynos_device_register_post_config(device_t self, void *aux) 650 { 651 } 652 653 void 654 exynos_usb_soc_powerup(void) 655 { 656 /* XXX 5422 XXX */ 657 } 658 659 660 /* 661 * USB Phy SoC dependent handling 662 */ 663 664 /* XXX 5422 not handled since its unknown how it handles this XXX*/ 665 static void 666 exynos_usb2_set_isolation(bool on) 667 { 668 uint32_t en_mask, regval; 669 bus_addr_t reg; 670 671 /* enable PHY */ 672 reg = EXYNOS_PMU_USB_PHY_CTRL; 673 674 if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) { 675 /* set usbhost mode */ 676 regval = on ? 0 : USB20_PHY_HOST_LINK_EN; 677 bus_space_write_4(&armv7_generic_bs_tag, exynos_sysreg_bsh, 678 EXYNOS5_SYSREG_USB20_PHY_TYPE, regval); 679 reg = EXYNOS_PMU_USBHOST_PHY_CTRL; 680 } 681 682 /* do enable PHY */ 683 en_mask = PMU_PHY_ENABLE; 684 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_pmu_bsh, reg); 685 regval = on ? regval & ~en_mask : regval | en_mask; 686 687 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 688 reg, regval); 689 690 if (IS_EXYNOS4X12_P()) { 691 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 692 EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval); 693 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 694 EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval); 695 } 696 } 697 698 699 #ifdef SOC_EXYNOS4 700 static void 701 exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 702 { 703 uint32_t phypwr, rstcon, clkreg; 704 705 /* write clock value */ 706 clkreg = FSEL_CLKSEL_24M; 707 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 708 USB_PHYCLK, clkreg); 709 710 /* set device and host to normal */ 711 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 712 USB_PHYPWR); 713 714 /* enable analog, enable otg, unsleep phy0 (host) */ 715 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0; 716 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 717 USB_PHYPWR, phypwr); 718 719 if (IS_EXYNOS4X12_P()) { 720 /* enable hsic0 (host), enable hsic1 and phy1 (otg) */ 721 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 722 USB_PHYPWR); 723 phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 | 724 PHYPWR_NORMAL_MASK_HSIC1 | 725 PHYPWR_NORMAL_MASK_PHY1); 726 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 727 USB_PHYPWR, phypwr); 728 } 729 730 /* reset both phy and link of device */ 731 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 732 USB_RSTCON); 733 rstcon |= RSTCON_DEVPHY_SWRST; 734 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 735 USB_RSTCON, rstcon); 736 DELAY(10000); 737 rstcon &= ~RSTCON_DEVPHY_SWRST; 738 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 739 USB_RSTCON, rstcon); 740 741 if (IS_EXYNOS4X12_P()) { 742 /* reset both phy and link of host */ 743 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 744 USB_RSTCON); 745 rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST; 746 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 747 USB_RSTCON, rstcon); 748 DELAY(10000); 749 rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST); 750 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 751 USB_RSTCON, rstcon); 752 } 753 754 /* wait for everything to be initialized */ 755 DELAY(80000); 756 } 757 #endif 758 759 760 #ifdef SOC_EXYNOS5 761 static void 762 exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 763 { 764 uint32_t phyhost; //, phyotg; 765 uint32_t phyhsic; 766 uint32_t ehcictrl, ohcictrl; 767 768 /* host configuration: */ 769 phyhost = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 770 USB_PHY_HOST_CTRL0); 771 772 /* host phy reference clock; assumption its 24 MHz now */ 773 phyhost &= ~HOST_CTRL0_FSEL_MASK; 774 phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK); 775 776 /* enable normal mode of operation */ 777 phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); 778 779 /* host phy reset */ 780 phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL | 781 HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | 782 HOST_CTRL0_FORCESLEEP); 783 784 /* host link reset */ 785 phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST | 786 HOST_CTRL0_COMMONON_N; 787 /* do the reset */ 788 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 789 phyhost); 790 DELAY(10000); 791 792 phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST); 793 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 794 phyhost); 795 796 /* HSIC control */ 797 phyhsic = 798 __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) | 799 __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) | 800 HSIC_CTRL_PHY_SWRST; 801 802 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 803 phyhsic); 804 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 805 phyhsic); 806 DELAY(10); 807 808 phyhsic &= ~HSIC_CTRL_PHY_SWRST; 809 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 810 phyhsic); 811 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 812 phyhsic); 813 DELAY(80); 814 815 #if 0 816 /* otg configuration: */ 817 phyotg = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 818 USB_PHY_OTG_SYS); 819 820 /* otg phy refrence clock: assumption its 24 Mhz now */ 821 phyotg &= ~OTG_SYS_FSEL_MASK; 822 phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M); 823 824 /* enable normal mode of operation */ 825 phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP | 826 OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK | 827 OTG_SYS_COMMON_ON); 828 829 /* OTG phy and link reset */ 830 phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST | 831 OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK; 832 833 /* do the reset */ 834 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 835 USB_PHY_OTG_SYS, phyotg); 836 DELAY(10000); 837 phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG | 838 OTG_SYS_PHYLINK_SWRST); 839 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 840 USB_PHY_OTG_SYS, phyotg); 841 #endif 842 843 /* enable EHCI DMA burst: */ 844 ehcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 845 USB_PHY_HOST_EHCICTRL); 846 ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN | 847 HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 | 848 HOST_EHCICTRL_ENA_INCR16; 849 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 850 USB_PHY_HOST_EHCICTRL, ehcictrl); 851 852 /* Set OHCI suspend */ 853 ohcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 854 USB_PHY_HOST_OHCICTRL); 855 ohcictrl |= HOST_OHCICTRL_SUSPLGCY; 856 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 857 USB_PHY_HOST_OHCICTRL, ohcictrl); 858 } 859 860 861 static void 862 exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 863 { 864 aprint_error("%s not implemented\n", __func__); 865 } 866 #endif 867 868 869 void 870 exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh) 871 { 872 /* disable phy isolation */ 873 exynos_usb2_set_isolation(false); 874 875 #ifdef SOC_EXYNOS4 876 exynos4_usb2phy_enable(usb2phy_bsh); 877 #endif 878 #ifdef SOC_EXYNOS5 879 if (IS_EXYNOS5410_P()) { 880 exynos5410_usb2phy_enable(usb2phy_bsh); 881 /* TBD: USB3 phy init */ 882 } else if (IS_EXYNOS5422_P()) { 883 exynos5422_usb2phy_enable(usb2phy_bsh); 884 /* TBD: USB3 phy init */ 885 } 886 #endif 887 } 888 889 890
Indexes created Tue Oct 21 12:09:54 GMT 2025