exynos_uart.c revision 1.6 1 1.6 jmcneill /* $NetBSD: exynos_uart.c,v 1.6 2021/09/13 23:31:23 jmcneill Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.6 jmcneill * Copyright (c) 2013-2021 The NetBSD Foundation, Inc.
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * This code is derived from software contributed to The NetBSD Foundation
8 1.1 jmcneill * by Matt Thomas of 3am Software Foundry and Jared McNeill.
9 1.1 jmcneill *
10 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
11 1.1 jmcneill * modification, are permitted provided that the following conditions
12 1.1 jmcneill * are met:
13 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
14 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
15 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
17 1.1 jmcneill * documentation and/or other materials provided with the distribution.
18 1.1 jmcneill *
19 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 jmcneill * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 jmcneill * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 jmcneill * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 jmcneill * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 jmcneill * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 jmcneill * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 jmcneill * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 jmcneill * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 jmcneill * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 jmcneill * POSSIBILITY OF SUCH DAMAGE.
30 1.1 jmcneill */
31 1.1 jmcneill
32 1.1 jmcneill #include "locators.h"
33 1.1 jmcneill
34 1.1 jmcneill #include <sys/cdefs.h>
35 1.1 jmcneill
36 1.6 jmcneill __KERNEL_RCSID(1, "$NetBSD: exynos_uart.c,v 1.6 2021/09/13 23:31:23 jmcneill Exp $");
37 1.1 jmcneill
38 1.1 jmcneill #define cn_trap() \
39 1.1 jmcneill do { \
40 1.1 jmcneill console_debugger(); \
41 1.1 jmcneill cn_trapped = 1; \
42 1.1 jmcneill } while (/* CONSTCOND */ 0)
43 1.1 jmcneill
44 1.1 jmcneill #include <sys/param.h>
45 1.1 jmcneill #include <sys/bus.h>
46 1.1 jmcneill #include <sys/device.h>
47 1.1 jmcneill #include <sys/conf.h>
48 1.1 jmcneill #include <sys/intr.h>
49 1.1 jmcneill #include <sys/systm.h>
50 1.1 jmcneill #include <sys/time.h>
51 1.1 jmcneill #include <sys/termios.h>
52 1.1 jmcneill #include <sys/kauth.h>
53 1.1 jmcneill #include <sys/lwp.h>
54 1.1 jmcneill #include <sys/tty.h>
55 1.1 jmcneill
56 1.1 jmcneill #include <dev/cons.h>
57 1.1 jmcneill
58 1.1 jmcneill #include <dev/fdt/fdtvar.h>
59 1.1 jmcneill
60 1.1 jmcneill #include <arm/samsung/sscom_reg.h>
61 1.1 jmcneill
62 1.1 jmcneill static int exynos_uart_match(device_t, cfdata_t, void *);
63 1.1 jmcneill static void exynos_uart_attach(device_t, device_t, void *);
64 1.1 jmcneill
65 1.1 jmcneill static int exynos_uart_intr(void *);
66 1.1 jmcneill
67 1.1 jmcneill static int exynos_uart_cngetc(dev_t);
68 1.1 jmcneill static void exynos_uart_cnputc(dev_t, int);
69 1.1 jmcneill static void exynos_uart_cnpollc(dev_t, int);
70 1.1 jmcneill
71 1.1 jmcneill static void exynos_uart_start(struct tty *);
72 1.1 jmcneill static int exynos_uart_param(struct tty *, struct termios *);
73 1.1 jmcneill
74 1.1 jmcneill extern struct cfdriver exuart_cd;
75 1.1 jmcneill
76 1.6 jmcneill enum exynos_uart_type {
77 1.6 jmcneill EXYNOS_UART_SAMSUNG,
78 1.6 jmcneill EXYNOS_UART_APPLE,
79 1.6 jmcneill };
80 1.6 jmcneill
81 1.6 jmcneill struct exynos_uart_config {
82 1.6 jmcneill enum exynos_uart_type type;
83 1.6 jmcneill uint32_t rxfull;
84 1.6 jmcneill uint32_t txfull;
85 1.6 jmcneill uint32_t rxcount;
86 1.6 jmcneill };
87 1.6 jmcneill
88 1.1 jmcneill struct exynos_uart_softc {
89 1.1 jmcneill device_t sc_dev;
90 1.1 jmcneill bus_space_tag_t sc_bst;
91 1.1 jmcneill bus_space_handle_t sc_bsh;
92 1.2 jmcneill kmutex_t sc_lock;
93 1.1 jmcneill u_int sc_freq;
94 1.1 jmcneill void *sc_ih;
95 1.1 jmcneill
96 1.1 jmcneill bool sc_console;
97 1.1 jmcneill struct tty *sc_tty;
98 1.1 jmcneill
99 1.1 jmcneill int sc_ospeed;
100 1.1 jmcneill tcflag_t sc_cflag;
101 1.1 jmcneill
102 1.6 jmcneill const struct exynos_uart_config *sc_conf;
103 1.6 jmcneill
104 1.1 jmcneill u_char sc_buf[1024];
105 1.1 jmcneill };
106 1.1 jmcneill
107 1.1 jmcneill #define RD4(sc, reg) \
108 1.1 jmcneill bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
109 1.1 jmcneill #define WR4(sc, reg, val) \
110 1.1 jmcneill bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
111 1.1 jmcneill
112 1.1 jmcneill static bus_addr_t exynos_uart_consaddr;
113 1.1 jmcneill
114 1.1 jmcneill static struct exynos_uart_softc exynos_uart_cnsc;
115 1.1 jmcneill
116 1.1 jmcneill static struct cnm_state exynos_uart_cnm_state;
117 1.1 jmcneill
118 1.1 jmcneill struct consdev exynos_uart_consdev = {
119 1.1 jmcneill .cn_getc = exynos_uart_cngetc,
120 1.1 jmcneill .cn_putc = exynos_uart_cnputc,
121 1.1 jmcneill .cn_pollc = exynos_uart_cnpollc,
122 1.1 jmcneill .cn_dev = NODEV,
123 1.1 jmcneill .cn_pri = CN_NORMAL,
124 1.1 jmcneill };
125 1.1 jmcneill
126 1.1 jmcneill static dev_type_open(exynos_uart_open);
127 1.1 jmcneill static dev_type_open(exynos_uart_close);
128 1.1 jmcneill static dev_type_read(exynos_uart_read);
129 1.1 jmcneill static dev_type_write(exynos_uart_write);
130 1.1 jmcneill static dev_type_ioctl(exynos_uart_ioctl);
131 1.1 jmcneill static dev_type_tty(exynos_uart_tty);
132 1.1 jmcneill static dev_type_poll(exynos_uart_poll);
133 1.1 jmcneill static dev_type_stop(exynos_uart_stop);
134 1.1 jmcneill
135 1.1 jmcneill const struct cdevsw exuart_cdevsw = {
136 1.1 jmcneill .d_open = exynos_uart_open,
137 1.1 jmcneill .d_close = exynos_uart_close,
138 1.1 jmcneill .d_read = exynos_uart_read,
139 1.1 jmcneill .d_write = exynos_uart_write,
140 1.1 jmcneill .d_ioctl = exynos_uart_ioctl,
141 1.1 jmcneill .d_stop = exynos_uart_stop,
142 1.1 jmcneill .d_tty = exynos_uart_tty,
143 1.1 jmcneill .d_poll = exynos_uart_poll,
144 1.1 jmcneill .d_mmap = nommap,
145 1.1 jmcneill .d_kqfilter = ttykqfilter,
146 1.1 jmcneill .d_discard = nodiscard,
147 1.1 jmcneill .d_flag = D_TTY
148 1.1 jmcneill };
149 1.1 jmcneill
150 1.1 jmcneill static int exynos_uart_cmajor = -1;
151 1.1 jmcneill
152 1.6 jmcneill static const struct exynos_uart_config exynos_uart_samsung = {
153 1.6 jmcneill .type = EXYNOS_UART_SAMSUNG,
154 1.6 jmcneill .rxfull = UFSTAT_RXFULL,
155 1.6 jmcneill .txfull = UFSTAT_TXFULL,
156 1.6 jmcneill .rxcount = UFSTAT_RXCOUNT,
157 1.6 jmcneill };
158 1.6 jmcneill
159 1.6 jmcneill static const struct exynos_uart_config exynos_uart_apple = {
160 1.6 jmcneill .type = EXYNOS_UART_APPLE,
161 1.6 jmcneill .rxfull = UFSTAT_S5L_RXFULL,
162 1.6 jmcneill .txfull = UFSTAT_S5L_TXFULL,
163 1.6 jmcneill .rxcount = UFSTAT_S5L_RXCOUNT,
164 1.6 jmcneill };
165 1.6 jmcneill
166 1.4 thorpej static const struct device_compatible_entry compat_data[] = {
167 1.6 jmcneill { .compat = "samsung,exynos4210-uart", .data = &exynos_uart_samsung },
168 1.6 jmcneill { .compat = "apple,s5l-uart", .data = &exynos_uart_apple },
169 1.4 thorpej DEVICE_COMPAT_EOL
170 1.1 jmcneill };
171 1.1 jmcneill
172 1.1 jmcneill CFATTACH_DECL_NEW(exynos_uart, sizeof(struct exynos_uart_softc),
173 1.1 jmcneill exynos_uart_match, exynos_uart_attach, NULL, NULL);
174 1.1 jmcneill
175 1.1 jmcneill static int
176 1.1 jmcneill exynos_uart_match(device_t parent, cfdata_t cf, void *aux)
177 1.1 jmcneill {
178 1.1 jmcneill struct fdt_attach_args * const faa = aux;
179 1.1 jmcneill
180 1.4 thorpej return of_compatible_match(faa->faa_phandle, compat_data);
181 1.1 jmcneill }
182 1.1 jmcneill
183 1.1 jmcneill static void
184 1.1 jmcneill exynos_uart_attach(device_t parent, device_t self, void *aux)
185 1.1 jmcneill {
186 1.1 jmcneill struct exynos_uart_softc * const sc = device_private(self);
187 1.1 jmcneill struct fdt_attach_args * const faa = aux;
188 1.1 jmcneill const int phandle = faa->faa_phandle;
189 1.1 jmcneill char intrstr[128];
190 1.1 jmcneill struct clk *clk_uart, *clk_uart_baud0;
191 1.1 jmcneill struct tty *tp;
192 1.1 jmcneill int major, minor;
193 1.1 jmcneill bus_addr_t addr;
194 1.1 jmcneill bus_size_t size;
195 1.6 jmcneill uint32_t ucon;
196 1.1 jmcneill
197 1.1 jmcneill if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
198 1.1 jmcneill aprint_error(": couldn't get registers\n");
199 1.1 jmcneill return;
200 1.1 jmcneill }
201 1.1 jmcneill if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
202 1.1 jmcneill aprint_error(": failed to decode interrupt\n");
203 1.1 jmcneill return;
204 1.1 jmcneill }
205 1.1 jmcneill clk_uart = fdtbus_clock_get(phandle, "uart");
206 1.1 jmcneill if (clk_uart == NULL || clk_enable(clk_uart) != 0) {
207 1.1 jmcneill aprint_error(": failed to enable uart clock\n");
208 1.1 jmcneill return;
209 1.1 jmcneill }
210 1.1 jmcneill clk_uart_baud0 = fdtbus_clock_get(phandle, "clk_uart_baud0");
211 1.1 jmcneill if (clk_uart_baud0 == NULL || clk_enable(clk_uart_baud0) != 0) {
212 1.1 jmcneill aprint_error(": failed to enable clk_uart_baud0 clock\n");
213 1.1 jmcneill return;
214 1.1 jmcneill }
215 1.1 jmcneill
216 1.1 jmcneill const bool is_console = exynos_uart_consaddr == addr;
217 1.1 jmcneill
218 1.1 jmcneill sc->sc_dev = self;
219 1.1 jmcneill sc->sc_bst = faa->faa_bst;
220 1.6 jmcneill sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data;
221 1.2 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
222 1.1 jmcneill sc->sc_console = is_console;
223 1.1 jmcneill if (is_console) {
224 1.1 jmcneill sc->sc_bsh = exynos_uart_cnsc.sc_bsh;
225 1.1 jmcneill } else {
226 1.1 jmcneill if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
227 1.1 jmcneill aprint_error(": failed to map registers\n");
228 1.1 jmcneill return;
229 1.1 jmcneill }
230 1.1 jmcneill }
231 1.1 jmcneill sc->sc_freq = clk_get_rate(clk_uart_baud0);
232 1.1 jmcneill
233 1.5 skrll sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL,
234 1.5 skrll 0, exynos_uart_intr, sc, device_xname(self));
235 1.1 jmcneill if (sc->sc_ih == NULL) {
236 1.1 jmcneill aprint_error(": failed to establish interrupt on %s\n",
237 1.1 jmcneill intrstr);
238 1.1 jmcneill return;
239 1.1 jmcneill }
240 1.1 jmcneill
241 1.1 jmcneill if (exynos_uart_cmajor == -1) {
242 1.1 jmcneill /* allocate a major number */
243 1.1 jmcneill int bmajor = -1, cmajor = -1;
244 1.1 jmcneill int error = devsw_attach("exuart", NULL, &bmajor,
245 1.1 jmcneill &exuart_cdevsw, &cmajor);
246 1.1 jmcneill if (error) {
247 1.1 jmcneill aprint_error(": couldn't allocate major number\n");
248 1.1 jmcneill return;
249 1.1 jmcneill }
250 1.1 jmcneill exynos_uart_cmajor = cmajor;
251 1.1 jmcneill }
252 1.1 jmcneill
253 1.1 jmcneill major = cdevsw_lookup_major(&exuart_cdevsw);
254 1.1 jmcneill minor = device_unit(self);
255 1.1 jmcneill
256 1.1 jmcneill tp = sc->sc_tty = tty_alloc();
257 1.1 jmcneill tp->t_oproc = exynos_uart_start;
258 1.1 jmcneill tp->t_param = exynos_uart_param;
259 1.1 jmcneill tp->t_dev = makedev(major, minor);
260 1.1 jmcneill tp->t_sc = sc;
261 1.1 jmcneill tty_attach(tp);
262 1.1 jmcneill
263 1.1 jmcneill aprint_naive("\n");
264 1.1 jmcneill if (is_console) {
265 1.1 jmcneill cn_tab->cn_dev = tp->t_dev;
266 1.1 jmcneill aprint_normal(": console");
267 1.1 jmcneill }
268 1.1 jmcneill aprint_normal("\n");
269 1.1 jmcneill
270 1.1 jmcneill if (is_console)
271 1.1 jmcneill delay(10000);
272 1.1 jmcneill
273 1.1 jmcneill /* Initialize device */
274 1.1 jmcneill WR4(sc, SSCOM_UFCON,
275 1.1 jmcneill __SHIFTIN(2, UFCON_TXTRIGGER) |
276 1.1 jmcneill __SHIFTIN(1, UFCON_RXTRIGGER) |
277 1.1 jmcneill UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET |
278 1.1 jmcneill UFCON_FIFO_ENABLE);
279 1.6 jmcneill
280 1.1 jmcneill /* Configure PIO mode with RX timeout interrupts */
281 1.6 jmcneill ucon = UCON_TOINT | UCON_ERRINT |
282 1.6 jmcneill UCON_TXMODE_INT | UCON_RXMODE_INT;
283 1.6 jmcneill WR4(sc, SSCOM_UCON, ucon);
284 1.6 jmcneill
285 1.6 jmcneill switch (sc->sc_conf->type) {
286 1.6 jmcneill case EXYNOS_UART_SAMSUNG:
287 1.6 jmcneill WR4(sc, SSCOM_UCON, ucon | __SHIFTIN(3, UCON_RXTO));
288 1.6 jmcneill /* Disable interrupts */
289 1.6 jmcneill WR4(sc, SSCOM_UINTM, ~0u);
290 1.6 jmcneill break;
291 1.6 jmcneill case EXYNOS_UART_APPLE:
292 1.6 jmcneill break;
293 1.6 jmcneill }
294 1.1 jmcneill
295 1.1 jmcneill aprint_normal_dev(self, "interrupting on %s\n", intrstr);
296 1.1 jmcneill }
297 1.1 jmcneill
298 1.1 jmcneill static int
299 1.1 jmcneill exynos_uart_cngetc(dev_t dev)
300 1.1 jmcneill {
301 1.1 jmcneill struct exynos_uart_softc * const sc = &exynos_uart_cnsc;
302 1.2 jmcneill uint32_t ufstat;
303 1.1 jmcneill int s, c;
304 1.1 jmcneill
305 1.1 jmcneill s = splserial();
306 1.1 jmcneill
307 1.2 jmcneill ufstat = RD4(sc, SSCOM_UFSTAT);
308 1.6 jmcneill if (__SHIFTOUT(ufstat, sc->sc_conf->rxcount) == 0) {
309 1.1 jmcneill splx(s);
310 1.1 jmcneill return -1;
311 1.1 jmcneill }
312 1.1 jmcneill
313 1.6 jmcneill c = RD4(sc, SSCOM_URXH);
314 1.1 jmcneill #if defined(DDB)
315 1.1 jmcneill extern int db_active;
316 1.1 jmcneill if (!db_active)
317 1.1 jmcneill #endif
318 1.1 jmcneill {
319 1.1 jmcneill int cn_trapped __unused = 0;
320 1.6 jmcneill cn_check_magic(dev, c & 0xff, exynos_uart_cnm_state);
321 1.1 jmcneill }
322 1.1 jmcneill
323 1.1 jmcneill splx(s);
324 1.1 jmcneill
325 1.1 jmcneill return c & 0xff;
326 1.1 jmcneill }
327 1.1 jmcneill
328 1.1 jmcneill static void
329 1.1 jmcneill exynos_uart_cnputc(dev_t dev, int c)
330 1.1 jmcneill {
331 1.1 jmcneill struct exynos_uart_softc * const sc = &exynos_uart_cnsc;
332 1.1 jmcneill int s;
333 1.1 jmcneill
334 1.1 jmcneill s = splserial();
335 1.6 jmcneill while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0)
336 1.1 jmcneill ;
337 1.1 jmcneill
338 1.6 jmcneill WR4(sc, SSCOM_UTXH, c & 0xff);
339 1.1 jmcneill
340 1.1 jmcneill splx(s);
341 1.1 jmcneill }
342 1.3 skrll
343 1.1 jmcneill
344 1.1 jmcneill static void
345 1.1 jmcneill exynos_uart_cnpollc(dev_t dev, int on)
346 1.1 jmcneill {
347 1.1 jmcneill }
348 1.1 jmcneill
349 1.1 jmcneill static void
350 1.1 jmcneill exynos_uart_cnattach(bus_space_tag_t bst, bus_space_handle_t bsh,
351 1.6 jmcneill int ospeed, tcflag_t cflag, const struct exynos_uart_config *conf)
352 1.1 jmcneill {
353 1.1 jmcneill struct exynos_uart_softc *sc = &exynos_uart_cnsc;
354 1.1 jmcneill
355 1.1 jmcneill cn_tab = &exynos_uart_consdev;
356 1.1 jmcneill cn_init_magic(&exynos_uart_cnm_state);
357 1.1 jmcneill cn_set_magic("\047\001");
358 1.1 jmcneill
359 1.1 jmcneill sc->sc_bst = bst;
360 1.1 jmcneill sc->sc_bsh = bsh;
361 1.1 jmcneill sc->sc_ospeed = ospeed;
362 1.1 jmcneill sc->sc_cflag = cflag;
363 1.6 jmcneill sc->sc_conf = conf;
364 1.1 jmcneill }
365 1.1 jmcneill
366 1.1 jmcneill static int
367 1.1 jmcneill exynos_uart_open(dev_t dev, int flag, int mode, lwp_t *l)
368 1.1 jmcneill {
369 1.1 jmcneill struct exynos_uart_softc *sc =
370 1.1 jmcneill device_lookup_private(&exuart_cd, minor(dev));
371 1.1 jmcneill struct tty *tp = sc->sc_tty;
372 1.6 jmcneill uint32_t ucon;
373 1.1 jmcneill
374 1.1 jmcneill if (kauth_authorize_device_tty(l->l_cred,
375 1.1 jmcneill KAUTH_DEVICE_TTY_OPEN, tp) != 0) {
376 1.1 jmcneill return EBUSY;
377 1.1 jmcneill }
378 1.1 jmcneill
379 1.2 jmcneill mutex_enter(&sc->sc_lock);
380 1.2 jmcneill
381 1.1 jmcneill if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) {
382 1.1 jmcneill tp->t_dev = dev;
383 1.1 jmcneill ttychars(tp);
384 1.1 jmcneill tp->t_iflag = TTYDEF_IFLAG;
385 1.1 jmcneill tp->t_oflag = TTYDEF_OFLAG;
386 1.1 jmcneill tp->t_lflag = TTYDEF_LFLAG;
387 1.1 jmcneill if (sc->sc_console) {
388 1.1 jmcneill tp->t_ispeed = tp->t_ospeed = exynos_uart_cnsc.sc_ospeed;
389 1.1 jmcneill tp->t_cflag = exynos_uart_cnsc.sc_cflag;
390 1.1 jmcneill } else {
391 1.1 jmcneill tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
392 1.1 jmcneill tp->t_cflag = TTYDEF_CFLAG;
393 1.1 jmcneill }
394 1.1 jmcneill ttsetwater(tp);
395 1.1 jmcneill }
396 1.1 jmcneill tp->t_state |= TS_CARR_ON;
397 1.1 jmcneill
398 1.1 jmcneill /* Enable RX and error interrupts */
399 1.6 jmcneill switch (sc->sc_conf->type) {
400 1.6 jmcneill case EXYNOS_UART_SAMSUNG:
401 1.6 jmcneill WR4(sc, SSCOM_UINTM, ~0u & ~(UINT_RXD|UINT_ERROR));
402 1.6 jmcneill break;
403 1.6 jmcneill case EXYNOS_UART_APPLE:
404 1.6 jmcneill ucon = RD4(sc, SSCOM_UCON);
405 1.6 jmcneill ucon |= UCON_S5L_RXTHRESH | UCON_S5L_RX_TIMEOUT;
406 1.6 jmcneill WR4(sc, SSCOM_UCON, ucon);
407 1.6 jmcneill break;
408 1.6 jmcneill }
409 1.1 jmcneill
410 1.2 jmcneill mutex_exit(&sc->sc_lock);
411 1.2 jmcneill
412 1.1 jmcneill return tp->t_linesw->l_open(dev, tp);
413 1.1 jmcneill }
414 1.1 jmcneill
415 1.1 jmcneill static int
416 1.1 jmcneill exynos_uart_close(dev_t dev, int flag, int mode, lwp_t *l)
417 1.1 jmcneill {
418 1.1 jmcneill struct exynos_uart_softc *sc =
419 1.1 jmcneill device_lookup_private(&exuart_cd, minor(dev));
420 1.1 jmcneill struct tty *tp = sc->sc_tty;
421 1.6 jmcneill uint32_t ucon;
422 1.1 jmcneill
423 1.2 jmcneill mutex_enter(&sc->sc_lock);
424 1.2 jmcneill
425 1.1 jmcneill tp->t_linesw->l_close(tp, flag);
426 1.1 jmcneill ttyclose(tp);
427 1.1 jmcneill
428 1.1 jmcneill /* Disable interrupts */
429 1.6 jmcneill switch (sc->sc_conf->type) {
430 1.6 jmcneill case EXYNOS_UART_SAMSUNG:
431 1.6 jmcneill WR4(sc, SSCOM_UINTM, ~0u);
432 1.6 jmcneill break;
433 1.6 jmcneill case EXYNOS_UART_APPLE:
434 1.6 jmcneill ucon = RD4(sc, SSCOM_UCON);
435 1.6 jmcneill ucon &= ~(UCON_S5L_RXTHRESH | UCON_S5L_RX_TIMEOUT);
436 1.6 jmcneill WR4(sc, SSCOM_UCON, ucon);
437 1.6 jmcneill break;
438 1.6 jmcneill }
439 1.1 jmcneill
440 1.2 jmcneill mutex_exit(&sc->sc_lock);
441 1.2 jmcneill
442 1.1 jmcneill return 0;
443 1.1 jmcneill }
444 1.1 jmcneill
445 1.1 jmcneill static int
446 1.1 jmcneill exynos_uart_read(dev_t dev, struct uio *uio, int flag)
447 1.1 jmcneill {
448 1.1 jmcneill struct exynos_uart_softc *sc =
449 1.1 jmcneill device_lookup_private(&exuart_cd, minor(dev));
450 1.1 jmcneill struct tty *tp = sc->sc_tty;
451 1.1 jmcneill
452 1.1 jmcneill return tp->t_linesw->l_read(tp, uio, flag);
453 1.1 jmcneill }
454 1.1 jmcneill
455 1.1 jmcneill static int
456 1.1 jmcneill exynos_uart_write(dev_t dev, struct uio *uio, int flag)
457 1.1 jmcneill {
458 1.1 jmcneill struct exynos_uart_softc *sc =
459 1.1 jmcneill device_lookup_private(&exuart_cd, minor(dev));
460 1.1 jmcneill struct tty *tp = sc->sc_tty;
461 1.1 jmcneill
462 1.1 jmcneill return tp->t_linesw->l_write(tp, uio, flag);
463 1.1 jmcneill }
464 1.1 jmcneill
465 1.1 jmcneill static int
466 1.1 jmcneill exynos_uart_poll(dev_t dev, int events, lwp_t *l)
467 1.1 jmcneill {
468 1.1 jmcneill struct exynos_uart_softc *sc =
469 1.1 jmcneill device_lookup_private(&exuart_cd, minor(dev));
470 1.1 jmcneill struct tty *tp = sc->sc_tty;
471 1.1 jmcneill
472 1.1 jmcneill return tp->t_linesw->l_poll(tp, events, l);
473 1.1 jmcneill }
474 1.1 jmcneill
475 1.1 jmcneill static int
476 1.1 jmcneill exynos_uart_ioctl(dev_t dev, u_long cmd, void *data, int flag, lwp_t *l)
477 1.1 jmcneill {
478 1.1 jmcneill struct exynos_uart_softc *sc =
479 1.1 jmcneill device_lookup_private(&exuart_cd, minor(dev));
480 1.1 jmcneill struct tty *tp = sc->sc_tty;
481 1.1 jmcneill int error;
482 1.1 jmcneill
483 1.1 jmcneill error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l);
484 1.1 jmcneill if (error != EPASSTHROUGH)
485 1.1 jmcneill return error;
486 1.1 jmcneill
487 1.1 jmcneill return ttioctl(tp, cmd, data, flag, l);
488 1.1 jmcneill }
489 1.1 jmcneill
490 1.1 jmcneill static struct tty *
491 1.1 jmcneill exynos_uart_tty(dev_t dev)
492 1.1 jmcneill {
493 1.1 jmcneill struct exynos_uart_softc *sc =
494 1.1 jmcneill device_lookup_private(&exuart_cd, minor(dev));
495 1.1 jmcneill
496 1.1 jmcneill return sc->sc_tty;
497 1.1 jmcneill }
498 1.1 jmcneill
499 1.1 jmcneill static void
500 1.1 jmcneill exynos_uart_stop(struct tty *tp, int flag)
501 1.1 jmcneill {
502 1.1 jmcneill }
503 1.1 jmcneill
504 1.1 jmcneill static void
505 1.1 jmcneill exynos_uart_start(struct tty *tp)
506 1.1 jmcneill {
507 1.1 jmcneill struct exynos_uart_softc *sc = tp->t_sc;
508 1.1 jmcneill u_char *p = sc->sc_buf;
509 1.1 jmcneill int s, brem;
510 1.1 jmcneill
511 1.1 jmcneill s = spltty();
512 1.1 jmcneill
513 1.1 jmcneill if (tp->t_state & (TS_TTSTOP | TS_BUSY | TS_TIMEOUT)) {
514 1.1 jmcneill splx(s);
515 1.1 jmcneill return;
516 1.1 jmcneill }
517 1.1 jmcneill tp->t_state |= TS_BUSY;
518 1.1 jmcneill
519 1.1 jmcneill for (brem = q_to_b(&tp->t_outq, sc->sc_buf, sizeof(sc->sc_buf));
520 1.1 jmcneill brem > 0;
521 1.1 jmcneill brem--, p++) {
522 1.6 jmcneill while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0)
523 1.1 jmcneill ;
524 1.1 jmcneill
525 1.6 jmcneill WR4(sc, SSCOM_UTXH, *p);
526 1.1 jmcneill }
527 1.1 jmcneill
528 1.1 jmcneill tp->t_state &= ~TS_BUSY;
529 1.1 jmcneill if (ttypull(tp)) {
530 1.1 jmcneill tp->t_state |= TS_TIMEOUT;
531 1.1 jmcneill callout_schedule(&tp->t_rstrt_ch, 1);
532 1.1 jmcneill }
533 1.1 jmcneill splx(s);
534 1.1 jmcneill }
535 1.1 jmcneill
536 1.1 jmcneill static int
537 1.1 jmcneill exynos_uart_param(struct tty *tp, struct termios *t)
538 1.1 jmcneill {
539 1.1 jmcneill struct exynos_uart_softc *sc = tp->t_sc;
540 1.1 jmcneill
541 1.2 jmcneill mutex_enter(&sc->sc_lock);
542 1.2 jmcneill
543 1.2 jmcneill if (tp->t_cflag != t->c_cflag) {
544 1.2 jmcneill uint32_t ulcon = 0;
545 1.2 jmcneill switch (ISSET(t->c_cflag, CSIZE)) {
546 1.2 jmcneill case CS5:
547 1.2 jmcneill ulcon |= ULCON_LENGTH_5;
548 1.2 jmcneill break;
549 1.2 jmcneill case CS6:
550 1.2 jmcneill ulcon |= ULCON_LENGTH_6;
551 1.2 jmcneill break;
552 1.2 jmcneill case CS7:
553 1.2 jmcneill ulcon |= ULCON_LENGTH_7;
554 1.2 jmcneill break;
555 1.2 jmcneill case CS8:
556 1.2 jmcneill ulcon |= ULCON_LENGTH_8;
557 1.2 jmcneill break;
558 1.2 jmcneill }
559 1.2 jmcneill switch (ISSET(t->c_cflag, PARENB|PARODD)) {
560 1.2 jmcneill case PARENB|PARODD:
561 1.2 jmcneill ulcon |= ULCON_PARITY_ODD;
562 1.2 jmcneill break;
563 1.2 jmcneill case PARENB:
564 1.2 jmcneill ulcon |= ULCON_PARITY_EVEN;
565 1.2 jmcneill break;
566 1.2 jmcneill default:
567 1.2 jmcneill ulcon |= ULCON_PARITY_NONE;
568 1.2 jmcneill break;
569 1.2 jmcneill }
570 1.2 jmcneill if (ISSET(t->c_cflag, CSTOPB))
571 1.2 jmcneill ulcon |= ULCON_STOP;
572 1.2 jmcneill WR4(sc, SSCOM_ULCON, ulcon);
573 1.2 jmcneill }
574 1.1 jmcneill
575 1.2 jmcneill if (tp->t_ospeed != t->c_ospeed) {
576 1.2 jmcneill const uint32_t ubrdiv = (sc->sc_freq / 16) / t->c_ospeed - 1;
577 1.2 jmcneill WR4(sc, SSCOM_UBRDIV, ubrdiv);
578 1.2 jmcneill }
579 1.1 jmcneill
580 1.1 jmcneill tp->t_ispeed = t->c_ispeed;
581 1.1 jmcneill tp->t_ospeed = t->c_ospeed;
582 1.1 jmcneill tp->t_cflag = t->c_cflag;
583 1.1 jmcneill
584 1.2 jmcneill mutex_exit(&sc->sc_lock);
585 1.2 jmcneill
586 1.1 jmcneill return 0;
587 1.1 jmcneill }
588 1.1 jmcneill
589 1.1 jmcneill static int
590 1.1 jmcneill exynos_uart_intr(void *priv)
591 1.1 jmcneill {
592 1.1 jmcneill struct exynos_uart_softc *sc = priv;
593 1.1 jmcneill struct tty *tp = sc->sc_tty;
594 1.6 jmcneill uint32_t ack, uerstat, ufstat, c;
595 1.1 jmcneill
596 1.2 jmcneill mutex_enter(&sc->sc_lock);
597 1.2 jmcneill
598 1.6 jmcneill if (sc->sc_conf->type == EXYNOS_UART_APPLE) {
599 1.6 jmcneill ack = RD4(sc, SSCOM_UTRSTAT);
600 1.6 jmcneill } else {
601 1.6 jmcneill ack = RD4(sc, SSCOM_UINTP);
602 1.6 jmcneill }
603 1.1 jmcneill
604 1.1 jmcneill for (;;) {
605 1.1 jmcneill int cn_trapped = 0;
606 1.1 jmcneill
607 1.1 jmcneill uerstat = RD4(sc, SSCOM_UERSTAT);
608 1.1 jmcneill if (uerstat & UERSTAT_BREAK) {
609 1.1 jmcneill cn_check_magic(tp->t_dev, CNC_BREAK,
610 1.1 jmcneill exynos_uart_cnm_state);
611 1.1 jmcneill if (cn_trapped)
612 1.1 jmcneill continue;
613 1.1 jmcneill }
614 1.1 jmcneill
615 1.1 jmcneill ufstat = RD4(sc, SSCOM_UFSTAT);
616 1.6 jmcneill if (__SHIFTOUT(ufstat, sc->sc_conf->rxcount) == 0) {
617 1.1 jmcneill break;
618 1.1 jmcneill }
619 1.1 jmcneill
620 1.6 jmcneill c = RD4(sc, SSCOM_URXH);
621 1.1 jmcneill cn_check_magic(tp->t_dev, c & 0xff, exynos_uart_cnm_state);
622 1.1 jmcneill if (cn_trapped)
623 1.1 jmcneill continue;
624 1.1 jmcneill tp->t_linesw->l_rint(c & 0xff, tp);
625 1.1 jmcneill }
626 1.1 jmcneill
627 1.6 jmcneill if (sc->sc_conf->type == EXYNOS_UART_APPLE) {
628 1.6 jmcneill WR4(sc, SSCOM_UTRSTAT, ack);
629 1.6 jmcneill } else {
630 1.6 jmcneill WR4(sc, SSCOM_UINTP, ack);
631 1.6 jmcneill }
632 1.1 jmcneill
633 1.2 jmcneill mutex_exit(&sc->sc_lock);
634 1.2 jmcneill
635 1.1 jmcneill return 1;
636 1.1 jmcneill }
637 1.1 jmcneill
638 1.1 jmcneill /*
639 1.1 jmcneill * Console support
640 1.1 jmcneill */
641 1.1 jmcneill
642 1.1 jmcneill static int
643 1.1 jmcneill exynos_uart_console_match(int phandle)
644 1.1 jmcneill {
645 1.4 thorpej return of_compatible_match(phandle, compat_data);
646 1.1 jmcneill }
647 1.1 jmcneill
648 1.1 jmcneill static void
649 1.1 jmcneill exynos_uart_console_consinit(struct fdt_attach_args *faa, u_int uart_freq)
650 1.1 jmcneill {
651 1.1 jmcneill const int phandle = faa->faa_phandle;
652 1.1 jmcneill bus_space_tag_t bst = faa->faa_bst;
653 1.1 jmcneill bus_space_handle_t bsh;
654 1.1 jmcneill bus_addr_t addr;
655 1.1 jmcneill bus_size_t size;
656 1.1 jmcneill tcflag_t flags;
657 1.1 jmcneill int speed;
658 1.6 jmcneill const struct exynos_uart_config *conf;
659 1.1 jmcneill
660 1.1 jmcneill speed = fdtbus_get_stdout_speed();
661 1.1 jmcneill if (speed < 0)
662 1.1 jmcneill speed = 115200; /* default */
663 1.1 jmcneill flags = fdtbus_get_stdout_flags();
664 1.6 jmcneill conf = of_compatible_lookup(phandle, compat_data)->data;
665 1.1 jmcneill
666 1.1 jmcneill if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0)
667 1.1 jmcneill panic("exynos_uart: couldn't get registers");
668 1.1 jmcneill if (bus_space_map(bst, addr, size, 0, &bsh) != 0)
669 1.1 jmcneill panic("exynos_uart: couldn't map registers");
670 1.1 jmcneill
671 1.1 jmcneill exynos_uart_consaddr = addr;
672 1.1 jmcneill
673 1.6 jmcneill exynos_uart_cnattach(bst, bsh, speed, flags, conf);
674 1.1 jmcneill }
675 1.1 jmcneill
676 1.1 jmcneill static const struct fdt_console exynos_uart_console = {
677 1.1 jmcneill .match = exynos_uart_console_match,
678 1.1 jmcneill .consinit = exynos_uart_console_consinit,
679 1.1 jmcneill };
680 1.1 jmcneill
681 1.1 jmcneill FDT_CONSOLE(exynos_uart, &exynos_uart_console);
682