exynos_uart.c revision 1.5
1 /* $NetBSD: exynos_uart.c,v 1.5 2021/03/14 08:16:57 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2013-2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry and Jared McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "locators.h" 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(1, "$NetBSD: exynos_uart.c,v 1.5 2021/03/14 08:16:57 skrll Exp $"); 37 38 #define cn_trap() \ 39 do { \ 40 console_debugger(); \ 41 cn_trapped = 1; \ 42 } while (/* CONSTCOND */ 0) 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/device.h> 47 #include <sys/conf.h> 48 #include <sys/intr.h> 49 #include <sys/systm.h> 50 #include <sys/time.h> 51 #include <sys/termios.h> 52 #include <sys/kauth.h> 53 #include <sys/lwp.h> 54 #include <sys/tty.h> 55 56 #include <dev/cons.h> 57 58 #include <dev/fdt/fdtvar.h> 59 60 #include <arm/samsung/sscom_reg.h> 61 62 static int exynos_uart_match(device_t, cfdata_t, void *); 63 static void exynos_uart_attach(device_t, device_t, void *); 64 65 static int exynos_uart_intr(void *); 66 67 static int exynos_uart_cngetc(dev_t); 68 static void exynos_uart_cnputc(dev_t, int); 69 static void exynos_uart_cnpollc(dev_t, int); 70 71 static void exynos_uart_start(struct tty *); 72 static int exynos_uart_param(struct tty *, struct termios *); 73 74 extern struct cfdriver exuart_cd; 75 76 struct exynos_uart_softc { 77 device_t sc_dev; 78 bus_space_tag_t sc_bst; 79 bus_space_handle_t sc_bsh; 80 kmutex_t sc_lock; 81 u_int sc_freq; 82 void *sc_ih; 83 84 bool sc_console; 85 struct tty *sc_tty; 86 87 int sc_ospeed; 88 tcflag_t sc_cflag; 89 90 u_char sc_buf[1024]; 91 }; 92 93 #define RD4(sc, reg) \ 94 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 95 #define WR4(sc, reg, val) \ 96 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 97 98 static bus_addr_t exynos_uart_consaddr; 99 100 static struct exynos_uart_softc exynos_uart_cnsc; 101 102 static struct cnm_state exynos_uart_cnm_state; 103 104 struct consdev exynos_uart_consdev = { 105 .cn_getc = exynos_uart_cngetc, 106 .cn_putc = exynos_uart_cnputc, 107 .cn_pollc = exynos_uart_cnpollc, 108 .cn_dev = NODEV, 109 .cn_pri = CN_NORMAL, 110 }; 111 112 static dev_type_open(exynos_uart_open); 113 static dev_type_open(exynos_uart_close); 114 static dev_type_read(exynos_uart_read); 115 static dev_type_write(exynos_uart_write); 116 static dev_type_ioctl(exynos_uart_ioctl); 117 static dev_type_tty(exynos_uart_tty); 118 static dev_type_poll(exynos_uart_poll); 119 static dev_type_stop(exynos_uart_stop); 120 121 const struct cdevsw exuart_cdevsw = { 122 .d_open = exynos_uart_open, 123 .d_close = exynos_uart_close, 124 .d_read = exynos_uart_read, 125 .d_write = exynos_uart_write, 126 .d_ioctl = exynos_uart_ioctl, 127 .d_stop = exynos_uart_stop, 128 .d_tty = exynos_uart_tty, 129 .d_poll = exynos_uart_poll, 130 .d_mmap = nommap, 131 .d_kqfilter = ttykqfilter, 132 .d_discard = nodiscard, 133 .d_flag = D_TTY 134 }; 135 136 static int exynos_uart_cmajor = -1; 137 138 static const struct device_compatible_entry compat_data[] = { 139 { .compat = "samsung,exynos4210-uart" }, 140 DEVICE_COMPAT_EOL 141 }; 142 143 CFATTACH_DECL_NEW(exynos_uart, sizeof(struct exynos_uart_softc), 144 exynos_uart_match, exynos_uart_attach, NULL, NULL); 145 146 static int 147 exynos_uart_match(device_t parent, cfdata_t cf, void *aux) 148 { 149 struct fdt_attach_args * const faa = aux; 150 151 return of_compatible_match(faa->faa_phandle, compat_data); 152 } 153 154 static void 155 exynos_uart_attach(device_t parent, device_t self, void *aux) 156 { 157 struct exynos_uart_softc * const sc = device_private(self); 158 struct fdt_attach_args * const faa = aux; 159 const int phandle = faa->faa_phandle; 160 char intrstr[128]; 161 struct clk *clk_uart, *clk_uart_baud0; 162 struct tty *tp; 163 int major, minor; 164 bus_addr_t addr; 165 bus_size_t size; 166 167 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 168 aprint_error(": couldn't get registers\n"); 169 return; 170 } 171 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 172 aprint_error(": failed to decode interrupt\n"); 173 return; 174 } 175 clk_uart = fdtbus_clock_get(phandle, "uart"); 176 if (clk_uart == NULL || clk_enable(clk_uart) != 0) { 177 aprint_error(": failed to enable uart clock\n"); 178 return; 179 } 180 clk_uart_baud0 = fdtbus_clock_get(phandle, "clk_uart_baud0"); 181 if (clk_uart_baud0 == NULL || clk_enable(clk_uart_baud0) != 0) { 182 aprint_error(": failed to enable clk_uart_baud0 clock\n"); 183 return; 184 } 185 186 const bool is_console = exynos_uart_consaddr == addr; 187 188 sc->sc_dev = self; 189 sc->sc_bst = faa->faa_bst; 190 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 191 sc->sc_console = is_console; 192 if (is_console) { 193 sc->sc_bsh = exynos_uart_cnsc.sc_bsh; 194 } else { 195 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 196 aprint_error(": failed to map registers\n"); 197 return; 198 } 199 } 200 sc->sc_freq = clk_get_rate(clk_uart_baud0); 201 202 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL, 203 0, exynos_uart_intr, sc, device_xname(self)); 204 if (sc->sc_ih == NULL) { 205 aprint_error(": failed to establish interrupt on %s\n", 206 intrstr); 207 return; 208 } 209 210 if (exynos_uart_cmajor == -1) { 211 /* allocate a major number */ 212 int bmajor = -1, cmajor = -1; 213 int error = devsw_attach("exuart", NULL, &bmajor, 214 &exuart_cdevsw, &cmajor); 215 if (error) { 216 aprint_error(": couldn't allocate major number\n"); 217 return; 218 } 219 exynos_uart_cmajor = cmajor; 220 } 221 222 major = cdevsw_lookup_major(&exuart_cdevsw); 223 minor = device_unit(self); 224 225 tp = sc->sc_tty = tty_alloc(); 226 tp->t_oproc = exynos_uart_start; 227 tp->t_param = exynos_uart_param; 228 tp->t_dev = makedev(major, minor); 229 tp->t_sc = sc; 230 tty_attach(tp); 231 232 aprint_naive("\n"); 233 if (is_console) { 234 cn_tab->cn_dev = tp->t_dev; 235 aprint_normal(": console"); 236 } 237 aprint_normal("\n"); 238 239 if (is_console) 240 delay(10000); 241 242 /* Initialize device */ 243 WR4(sc, SSCOM_UFCON, 244 __SHIFTIN(2, UFCON_TXTRIGGER) | 245 __SHIFTIN(1, UFCON_RXTRIGGER) | 246 UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET | 247 UFCON_FIFO_ENABLE); 248 /* Configure PIO mode with RX timeout interrupts */ 249 WR4(sc, SSCOM_UCON, 250 __SHIFTIN(3, UCON_RXTO) | 251 UCON_TOINT | UCON_ERRINT | 252 UCON_TXMODE_INT | UCON_RXMODE_INT); 253 254 /* Disable interrupts */ 255 WR4(sc, SSCOM_UINTM, ~0u); 256 257 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 258 } 259 260 static int 261 exynos_uart_cngetc(dev_t dev) 262 { 263 struct exynos_uart_softc * const sc = &exynos_uart_cnsc; 264 uint32_t ufstat; 265 int s, c; 266 267 s = splserial(); 268 269 ufstat = RD4(sc, SSCOM_UFSTAT); 270 if (__SHIFTOUT(ufstat, UFSTAT_RXCOUNT) == 0) { 271 splx(s); 272 return -1; 273 } 274 275 c = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SSCOM_URXH); 276 #if defined(DDB) 277 extern int db_active; 278 if (!db_active) 279 #endif 280 { 281 int cn_trapped __unused = 0; 282 cn_check_magic(dev, c, exynos_uart_cnm_state); 283 } 284 285 splx(s); 286 287 return c & 0xff; 288 } 289 290 static void 291 exynos_uart_cnputc(dev_t dev, int c) 292 { 293 struct exynos_uart_softc * const sc = &exynos_uart_cnsc; 294 int s; 295 296 s = splserial(); 297 while ((RD4(sc, SSCOM_UFSTAT) & UFSTAT_TXFULL) != 0) 298 ; 299 300 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SSCOM_UTXH, c); 301 302 splx(s); 303 } 304 305 306 static void 307 exynos_uart_cnpollc(dev_t dev, int on) 308 { 309 } 310 311 static void 312 exynos_uart_cnattach(bus_space_tag_t bst, bus_space_handle_t bsh, 313 int ospeed, tcflag_t cflag) 314 { 315 struct exynos_uart_softc *sc = &exynos_uart_cnsc; 316 317 cn_tab = &exynos_uart_consdev; 318 cn_init_magic(&exynos_uart_cnm_state); 319 cn_set_magic("\047\001"); 320 321 sc->sc_bst = bst; 322 sc->sc_bsh = bsh; 323 sc->sc_ospeed = ospeed; 324 sc->sc_cflag = cflag; 325 } 326 327 static int 328 exynos_uart_open(dev_t dev, int flag, int mode, lwp_t *l) 329 { 330 struct exynos_uart_softc *sc = 331 device_lookup_private(&exuart_cd, minor(dev)); 332 struct tty *tp = sc->sc_tty; 333 334 if (kauth_authorize_device_tty(l->l_cred, 335 KAUTH_DEVICE_TTY_OPEN, tp) != 0) { 336 return EBUSY; 337 } 338 339 mutex_enter(&sc->sc_lock); 340 341 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 342 tp->t_dev = dev; 343 ttychars(tp); 344 tp->t_iflag = TTYDEF_IFLAG; 345 tp->t_oflag = TTYDEF_OFLAG; 346 tp->t_lflag = TTYDEF_LFLAG; 347 if (sc->sc_console) { 348 tp->t_ispeed = tp->t_ospeed = exynos_uart_cnsc.sc_ospeed; 349 tp->t_cflag = exynos_uart_cnsc.sc_cflag; 350 } else { 351 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 352 tp->t_cflag = TTYDEF_CFLAG; 353 } 354 ttsetwater(tp); 355 } 356 tp->t_state |= TS_CARR_ON; 357 358 /* Enable RX and error interrupts */ 359 WR4(sc, SSCOM_UINTM, ~0u & ~(UINT_RXD|UINT_ERROR)); 360 361 mutex_exit(&sc->sc_lock); 362 363 return tp->t_linesw->l_open(dev, tp); 364 } 365 366 static int 367 exynos_uart_close(dev_t dev, int flag, int mode, lwp_t *l) 368 { 369 struct exynos_uart_softc *sc = 370 device_lookup_private(&exuart_cd, minor(dev)); 371 struct tty *tp = sc->sc_tty; 372 373 mutex_enter(&sc->sc_lock); 374 375 tp->t_linesw->l_close(tp, flag); 376 ttyclose(tp); 377 378 /* Disable interrupts */ 379 WR4(sc, SSCOM_UINTM, ~0u); 380 381 mutex_exit(&sc->sc_lock); 382 383 return 0; 384 } 385 386 static int 387 exynos_uart_read(dev_t dev, struct uio *uio, int flag) 388 { 389 struct exynos_uart_softc *sc = 390 device_lookup_private(&exuart_cd, minor(dev)); 391 struct tty *tp = sc->sc_tty; 392 393 return tp->t_linesw->l_read(tp, uio, flag); 394 } 395 396 static int 397 exynos_uart_write(dev_t dev, struct uio *uio, int flag) 398 { 399 struct exynos_uart_softc *sc = 400 device_lookup_private(&exuart_cd, minor(dev)); 401 struct tty *tp = sc->sc_tty; 402 403 return tp->t_linesw->l_write(tp, uio, flag); 404 } 405 406 static int 407 exynos_uart_poll(dev_t dev, int events, lwp_t *l) 408 { 409 struct exynos_uart_softc *sc = 410 device_lookup_private(&exuart_cd, minor(dev)); 411 struct tty *tp = sc->sc_tty; 412 413 return tp->t_linesw->l_poll(tp, events, l); 414 } 415 416 static int 417 exynos_uart_ioctl(dev_t dev, u_long cmd, void *data, int flag, lwp_t *l) 418 { 419 struct exynos_uart_softc *sc = 420 device_lookup_private(&exuart_cd, minor(dev)); 421 struct tty *tp = sc->sc_tty; 422 int error; 423 424 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l); 425 if (error != EPASSTHROUGH) 426 return error; 427 428 return ttioctl(tp, cmd, data, flag, l); 429 } 430 431 static struct tty * 432 exynos_uart_tty(dev_t dev) 433 { 434 struct exynos_uart_softc *sc = 435 device_lookup_private(&exuart_cd, minor(dev)); 436 437 return sc->sc_tty; 438 } 439 440 static void 441 exynos_uart_stop(struct tty *tp, int flag) 442 { 443 } 444 445 static void 446 exynos_uart_start(struct tty *tp) 447 { 448 struct exynos_uart_softc *sc = tp->t_sc; 449 u_char *p = sc->sc_buf; 450 int s, brem; 451 452 s = spltty(); 453 454 if (tp->t_state & (TS_TTSTOP | TS_BUSY | TS_TIMEOUT)) { 455 splx(s); 456 return; 457 } 458 tp->t_state |= TS_BUSY; 459 460 for (brem = q_to_b(&tp->t_outq, sc->sc_buf, sizeof(sc->sc_buf)); 461 brem > 0; 462 brem--, p++) { 463 while ((RD4(sc, SSCOM_UFSTAT) & UFSTAT_TXFULL) != 0) 464 ; 465 466 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 467 SSCOM_UTXH, *p); 468 } 469 470 tp->t_state &= ~TS_BUSY; 471 if (ttypull(tp)) { 472 tp->t_state |= TS_TIMEOUT; 473 callout_schedule(&tp->t_rstrt_ch, 1); 474 } 475 splx(s); 476 } 477 478 static int 479 exynos_uart_param(struct tty *tp, struct termios *t) 480 { 481 struct exynos_uart_softc *sc = tp->t_sc; 482 483 mutex_enter(&sc->sc_lock); 484 485 if (tp->t_cflag != t->c_cflag) { 486 uint32_t ulcon = 0; 487 switch (ISSET(t->c_cflag, CSIZE)) { 488 case CS5: 489 ulcon |= ULCON_LENGTH_5; 490 break; 491 case CS6: 492 ulcon |= ULCON_LENGTH_6; 493 break; 494 case CS7: 495 ulcon |= ULCON_LENGTH_7; 496 break; 497 case CS8: 498 ulcon |= ULCON_LENGTH_8; 499 break; 500 } 501 switch (ISSET(t->c_cflag, PARENB|PARODD)) { 502 case PARENB|PARODD: 503 ulcon |= ULCON_PARITY_ODD; 504 break; 505 case PARENB: 506 ulcon |= ULCON_PARITY_EVEN; 507 break; 508 default: 509 ulcon |= ULCON_PARITY_NONE; 510 break; 511 } 512 if (ISSET(t->c_cflag, CSTOPB)) 513 ulcon |= ULCON_STOP; 514 WR4(sc, SSCOM_ULCON, ulcon); 515 } 516 517 if (tp->t_ospeed != t->c_ospeed) { 518 const uint32_t ubrdiv = (sc->sc_freq / 16) / t->c_ospeed - 1; 519 WR4(sc, SSCOM_UBRDIV, ubrdiv); 520 } 521 522 tp->t_ispeed = t->c_ispeed; 523 tp->t_ospeed = t->c_ospeed; 524 tp->t_cflag = t->c_cflag; 525 526 mutex_exit(&sc->sc_lock); 527 528 return 0; 529 } 530 531 static int 532 exynos_uart_intr(void *priv) 533 { 534 struct exynos_uart_softc *sc = priv; 535 struct tty *tp = sc->sc_tty; 536 uint32_t uintp, uerstat, ufstat, c; 537 538 mutex_enter(&sc->sc_lock); 539 540 uintp = RD4(sc, SSCOM_UINTP); 541 542 for (;;) { 543 int cn_trapped = 0; 544 545 uerstat = RD4(sc, SSCOM_UERSTAT); 546 if (uerstat & UERSTAT_BREAK) { 547 cn_check_magic(tp->t_dev, CNC_BREAK, 548 exynos_uart_cnm_state); 549 if (cn_trapped) 550 continue; 551 } 552 553 ufstat = RD4(sc, SSCOM_UFSTAT); 554 if (__SHIFTOUT(ufstat, UFSTAT_RXCOUNT) == 0) { 555 break; 556 } 557 558 c = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SSCOM_URXH); 559 cn_check_magic(tp->t_dev, c & 0xff, exynos_uart_cnm_state); 560 if (cn_trapped) 561 continue; 562 tp->t_linesw->l_rint(c & 0xff, tp); 563 } 564 565 WR4(sc, SSCOM_UINTP, uintp); 566 567 mutex_exit(&sc->sc_lock); 568 569 return 1; 570 } 571 572 /* 573 * Console support 574 */ 575 576 static int 577 exynos_uart_console_match(int phandle) 578 { 579 return of_compatible_match(phandle, compat_data); 580 } 581 582 static void 583 exynos_uart_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) 584 { 585 const int phandle = faa->faa_phandle; 586 bus_space_tag_t bst = faa->faa_bst; 587 bus_space_handle_t bsh; 588 bus_addr_t addr; 589 bus_size_t size; 590 tcflag_t flags; 591 int speed; 592 593 speed = fdtbus_get_stdout_speed(); 594 if (speed < 0) 595 speed = 115200; /* default */ 596 flags = fdtbus_get_stdout_flags(); 597 598 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) 599 panic("exynos_uart: couldn't get registers"); 600 if (bus_space_map(bst, addr, size, 0, &bsh) != 0) 601 panic("exynos_uart: couldn't map registers"); 602 603 exynos_uart_consaddr = addr; 604 605 exynos_uart_cnattach(bst, bsh, speed, flags); 606 } 607 608 static const struct fdt_console exynos_uart_console = { 609 .match = exynos_uart_console_match, 610 .consinit = exynos_uart_console_consinit, 611 }; 612 613 FDT_CONSOLE(exynos_uart, &exynos_uart_console); 614
Indexes created Tue Sep 30 20:09:53 GMT 2025