Home | History | Annotate | Line # | Download | only in samsung
exynos_usbphy.c revision 1.3 
      1 /* $NetBSD: exynos_usbphy.c,v 1.3 2021/01/18 02:35:49 thorpej Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 
     31 __KERNEL_RCSID(0, "$NetBSD: exynos_usbphy.c,v 1.3 2021/01/18 02:35:49 thorpej Exp $");
     32 
     33 #include <sys/param.h>
     34 #include <sys/bus.h>
     35 #include <sys/device.h>
     36 #include <sys/intr.h>
     37 #include <sys/systm.h>
     38 #include <sys/kmem.h>
     39 
     40 #include <dev/fdt/fdtvar.h>
     41 #include <dev/fdt/syscon.h>
     42 
     43 #include <arm/samsung/exynos_reg.h>
     44 #include <arm/samsung/exynos5_reg.h>
     45 
     46 /*
     47  * System Registers
     48  */
     49 #define	USB20PHY_CFG			0x230
     50 #define	 USB20PHY_CFG_HOST_LINK_EN	__BIT(0)
     51 
     52 /*
     53  * PMU Registers
     54  */
     55 #define	USBHOST_PHY_CTRL		0x708
     56 #define	 USBHOST_PHY_CTRL_EN		__BIT(0)
     57 
     58 enum {
     59 	PHY_ID_DEVICE = 0,
     60 	PHY_ID_HOST,
     61 	PHY_ID_HSIC0,
     62 	PHY_ID_HSIC1,
     63 	NPHY_ID
     64 };
     65 
     66 static int exynos_usbphy_match(device_t, cfdata_t, void *);
     67 static void exynos_usbphy_attach(device_t, device_t, void *);
     68 
     69 static const struct device_compatible_entry compat_data[] = {
     70 	{ .compat = "samsung,exynos5250-usb2-phy" },
     71 
     72 	{ 0 }
     73 };
     74 
     75 struct exynos_usbphy_softc;
     76 
     77 struct exynos_usbphy {
     78 	struct exynos_usbphy_softc *phy_sc;
     79 	u_int			phy_index;
     80 };
     81 
     82 struct exynos_usbphy_softc {
     83 	device_t		sc_dev;
     84 	bus_space_tag_t		sc_bst;
     85 	bus_space_handle_t	sc_bsh;
     86 	int			sc_phandle;
     87 
     88 	struct syscon		*sc_sysreg;
     89 	struct syscon		*sc_pmureg;
     90 
     91 	u_int			sc_refcnt;
     92 
     93 	struct exynos_usbphy	*sc_phy;
     94 	u_int			sc_nphy;
     95 
     96 	struct fdtbus_gpio_pin	*sc_gpio_id_det;
     97 	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
     98 };
     99 
    100 #define	PHY_READ(sc, reg)				\
    101 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
    102 #define	PHY_WRITE(sc, reg, val)				\
    103 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
    104 
    105 CFATTACH_DECL_NEW(exynos_usbphy, sizeof(struct exynos_usbphy_softc),
    106 	exynos_usbphy_match, exynos_usbphy_attach, NULL, NULL);
    107 
    108 static void *
    109 exynos_usbphy_acquire(device_t dev, const void *data, size_t len)
    110 {
    111 	struct exynos_usbphy_softc * const sc = device_private(dev);
    112 
    113 	if (len != 4)
    114 		return NULL;
    115 
    116 	const u_int index = be32dec(data);
    117 	if (index >= sc->sc_nphy)
    118 		return NULL;
    119 
    120 	return &sc->sc_phy[index];
    121 }
    122 
    123 static void
    124 exynos_usbphy_release(device_t dev, void *priv)
    125 {
    126 }
    127 
    128 static int
    129 exynos_usbphy_enable(device_t dev, void *priv, bool enable)
    130 {
    131 	struct exynos_usbphy * const phy = priv;
    132 	struct exynos_usbphy_softc * const sc = phy->phy_sc;
    133 	bool do_common;
    134 	uint32_t val;
    135 
    136 	if (enable) {
    137 		sc->sc_refcnt++;
    138 	} else {
    139 		KASSERT(sc->sc_refcnt > 0);
    140 		sc->sc_refcnt--;
    141 	}
    142 	do_common = sc->sc_refcnt == enable;
    143 
    144 	if (do_common) {
    145 		syscon_lock(sc->sc_sysreg);
    146 		val = syscon_read_4(sc->sc_sysreg, USB20PHY_CFG);
    147 		if (enable)
    148 			val |= USB20PHY_CFG_HOST_LINK_EN;
    149 		else
    150 			val &= ~USB20PHY_CFG_HOST_LINK_EN;
    151 		syscon_write_4(sc->sc_sysreg, USB20PHY_CFG, val);
    152 		syscon_unlock(sc->sc_sysreg);
    153 
    154 		syscon_lock(sc->sc_pmureg);
    155 		val = syscon_read_4(sc->sc_pmureg, USBHOST_PHY_CTRL);
    156 		if (enable)
    157 			val |= USBHOST_PHY_CTRL_EN;
    158 		else
    159 			val &= ~USBHOST_PHY_CTRL_EN;
    160 		syscon_write_4(sc->sc_pmureg, USBHOST_PHY_CTRL, val);
    161 		syscon_unlock(sc->sc_pmureg);
    162 
    163 		if (enable) {
    164 			val = PHY_READ(sc, USB_PHY_HOST_CTRL0);
    165 			val &= ~HOST_CTRL0_COMMONON_N;
    166 			val &= ~HOST_CTRL0_PHY_SWRST;
    167 			val &= ~HOST_CTRL0_PHY_SWRST_ALL;
    168 			val &= ~HOST_CTRL0_SIDDQ;
    169 			val &= ~HOST_CTRL0_FORCESUSPEND;
    170 			val &= ~HOST_CTRL0_FORCESLEEP;
    171 			val &= ~HOST_CTRL0_FSEL_MASK;
    172 			val |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);
    173 			val |= HOST_CTRL0_LINK_SWRST;
    174 			val |= HOST_CTRL0_UTMI_SWRST;
    175 			PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
    176 
    177 			delay(10000);
    178 
    179 			val &= ~HOST_CTRL0_LINK_SWRST;
    180 			val &= ~HOST_CTRL0_UTMI_SWRST;
    181 			PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
    182 
    183 			delay(10000);
    184 		}
    185 	}
    186 
    187 	switch (phy->phy_index) {
    188 	case PHY_ID_HSIC0:
    189 	case PHY_ID_HSIC1:
    190 		if (enable) {
    191 			const bus_size_t reg = phy->phy_index == PHY_ID_HSIC0 ?
    192 			    USB_PHY_HSIC_CTRL1 : USB_PHY_HSIC_CTRL2;
    193 
    194 			val = HSIC_CTRL_PHY_SWRST;
    195 			val |= __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK);
    196 			val |= __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK);
    197 			PHY_WRITE(sc, reg, val);
    198 
    199 			delay(10000);
    200 
    201 			val &= ~HSIC_CTRL_PHY_SWRST;
    202 			PHY_WRITE(sc, reg, val);
    203 
    204 			delay(10000);
    205 		}
    206 		break;
    207 	}
    208 
    209 	if (do_common) {
    210 		if (enable) {
    211 			val = PHY_READ(sc, USB_PHY_HOST_EHCICTRL);
    212 			val |= HOST_EHCICTRL_ENA_INCRXALIGN;
    213 			val |= HOST_EHCICTRL_ENA_INCR4;
    214 			val |= HOST_EHCICTRL_ENA_INCR8;
    215 			val |= HOST_EHCICTRL_ENA_INCR16;
    216 			PHY_WRITE(sc, USB_PHY_HOST_EHCICTRL, val);
    217 		}
    218 	}
    219 
    220 	return 0;
    221 }
    222 
    223 const struct fdtbus_phy_controller_func exynos_usbphy_funcs = {
    224 	.acquire = exynos_usbphy_acquire,
    225 	.release = exynos_usbphy_release,
    226 	.enable = exynos_usbphy_enable,
    227 };
    228 
    229 static int
    230 exynos_usbphy_match(device_t parent, cfdata_t cf, void *aux)
    231 {
    232 	struct fdt_attach_args * const faa = aux;
    233 
    234 	return of_match_compat_data(faa->faa_phandle, compat_data);
    235 }
    236 
    237 static void
    238 exynos_usbphy_attach(device_t parent, device_t self, void *aux)
    239 {
    240 	struct exynos_usbphy_softc * const sc = device_private(self);
    241 	struct fdt_attach_args * const faa = aux;
    242 	const int phandle = faa->faa_phandle;
    243 	struct clk *clk;
    244 	bus_addr_t addr;
    245 	bus_size_t size;
    246 	u_int n;
    247 
    248 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
    249 		aprint_error(": couldn't get phy registers\n");
    250 		return;
    251 	}
    252 
    253 	sc->sc_dev = self;
    254 	sc->sc_phandle = phandle;
    255 	sc->sc_bst = faa->faa_bst;
    256 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
    257 		aprint_error(": couldn't map phy registers\n");
    258 		return;
    259 	}
    260 	sc->sc_nphy = NPHY_ID;
    261 	sc->sc_phy = kmem_alloc(sizeof(*sc->sc_phy) * sc->sc_nphy, KM_SLEEP);
    262 	for (n = 0; n < sc->sc_nphy; n++) {
    263 		sc->sc_phy[n].phy_sc = sc;
    264 		sc->sc_phy[n].phy_index = n;
    265 	}
    266 
    267 	sc->sc_sysreg = fdtbus_syscon_acquire(phandle, "samsung,sysreg-phandle");
    268 	if (sc->sc_sysreg == NULL) {
    269 		aprint_error(": couldn't acquire sysreg syscon\n");
    270 		return;
    271 	}
    272 	sc->sc_pmureg = fdtbus_syscon_acquire(phandle, "samsung,pmureg-phandle");
    273 	if (sc->sc_pmureg == NULL) {
    274 		aprint_error(": couldn't acquire pmureg syscon\n");
    275 		return;
    276 	}
    277 
    278 	/* Enable clocks */
    279 	clk = fdtbus_clock_get(phandle, "phy");
    280 	if (clk == NULL || clk_enable(clk) != 0) {
    281 		aprint_error(": couldn't enable phy clock\n");
    282 		return;
    283 	}
    284 	clk = fdtbus_clock_get(phandle, "ref");
    285 	if (clk == NULL || clk_enable(clk) != 0) {
    286 		aprint_error(": couldn't enable ref clock\n");
    287 		return;
    288 	}
    289 
    290 	aprint_naive("\n");
    291 	aprint_normal(": USB2 PHY\n");
    292 
    293 	fdtbus_register_phy_controller(self, phandle, &exynos_usbphy_funcs);
    294 }
    295