exynos_wdt.c revision 1.2
1 /* $NetBSD: exynos_wdt.c,v 1.2 2014/04/18 14:32:49 reinoud Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "exynos_wdt.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.2 2014/04/18 14:32:49 reinoud Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 #include <sys/wdog.h> 42 43 #include <prop/proplib.h> 44 45 #include <dev/sysmon/sysmonvar.h> 46 47 #include <arm/samsung/exynos_reg.h> 48 #include <arm/samsung/exynos_var.h> 49 #include <arm/samsung/exynos_wdt_reg.h> 50 51 #if NEXYNOS_WDT > 0 52 static int exynos_wdt_match(device_t, cfdata_t, void *); 53 static void exynos_wdt_attach(device_t, device_t, void *); 54 55 struct exynos_wdt_softc { 56 struct sysmon_wdog sc_smw; 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_wdog_bsh; 60 u_int sc_wdog_period; 61 u_int sc_wdog_clock_select; 62 u_int sc_wdog_prescaler; 63 uint32_t sc_freq; 64 uint32_t sc_wdog_wtdat; 65 uint32_t sc_wdog_wtcon; 66 bool sc_wdog_armed; 67 }; 68 69 #ifndef EXYNOS_WDT_PERIOD_DEFAULT 70 #define EXYNOS_WDT_PERIOD_DEFAULT 12 71 #endif 72 73 CFATTACH_DECL_NEW(exynos_wdt, sizeof(struct exynos_wdt_softc), 74 exynos_wdt_match, exynos_wdt_attach, NULL, NULL); 75 76 static inline uint32_t 77 exynos_wdt_wdog_read(struct exynos_wdt_softc *sc, bus_size_t o) 78 { 79 return bus_space_read_4(sc->sc_bst, sc->sc_wdog_bsh, o); 80 } 81 82 static inline void 83 exynos_wdt_wdog_write(struct exynos_wdt_softc *sc, bus_size_t o, uint32_t v) 84 { 85 bus_space_write_4(sc->sc_bst, sc->sc_wdog_bsh, o, v); 86 } 87 88 /* ARGSUSED */ 89 static int 90 exynos_wdt_match(device_t parent, cfdata_t cf, void *aux) 91 { 92 return 1; 93 } 94 95 static int 96 exynos_wdt_tickle(struct sysmon_wdog *smw) 97 { 98 struct exynos_wdt_softc * const sc = smw->smw_cookie; 99 100 /* 101 * Cause the WDOG to restart counting. 102 */ 103 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 104 aprint_debug_dev(sc->sc_dev, "tickle\n"); 105 return 0; 106 } 107 108 static int 109 exynos_wdt_setmode(struct sysmon_wdog *smw) 110 { 111 struct exynos_wdt_softc * const sc = smw->smw_cookie; 112 113 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 114 /* 115 * Emit magic sequence to turn off WDOG 116 */ 117 sc->sc_wdog_wtcon &= ~(WTCON_ENABLE|WTCON_RESET_ENABLE); 118 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 119 delay(1); 120 aprint_debug_dev(sc->sc_dev, "setmode disable\n"); 121 return 0; 122 } 123 124 /* 125 * If no changes, just tickle it and return. 126 */ 127 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) { 128 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1; 129 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE 130 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT) 131 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER); 132 133 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 134 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat); 135 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 136 aprint_debug_dev(sc->sc_dev, "setmode refresh\n"); 137 return 0; 138 } 139 140 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 141 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT; 142 smw->smw_period = EXYNOS_WDT_PERIOD_DEFAULT; 143 } 144 145 /* 146 * Make sure we don't overflow the counter. 147 */ 148 if (smw->smw_period * sc->sc_freq >= UINT16_MAX) { 149 return EINVAL; 150 } 151 152 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1; 153 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE 154 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT) 155 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER); 156 157 /* 158 * Have to disable to be able to write WTDAT 159 */ 160 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, 161 sc->sc_wdog_wtcon & ~(WTCON_ENABLE | WTCON_RESET_ENABLE)); 162 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 163 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat); 164 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 165 166 aprint_debug_dev(sc->sc_dev, "setmode enable\n"); 167 return 0; 168 } 169 170 171 static void 172 exynos_wdt_attach(device_t parent, device_t self, void *aux) 173 { 174 struct exynos_wdt_softc * const sc = device_private(self); 175 struct exyo_attach_args * const exyo = aux; 176 prop_dictionary_t dict = device_properties(self); 177 178 sc->sc_dev = self; 179 sc->sc_bst = exyo->exyo_core_bst; 180 181 if (bus_space_subregion(sc->sc_bst, exyo->exyo_core_bsh, 182 exyo->exyo_loc.loc_offset, exyo->exyo_loc.loc_size, &sc->sc_wdog_bsh)) { 183 aprint_error(": failed to map registers\n"); 184 return; 185 } 186 187 /* 188 * This runs at the Exynos Pclk. 189 */ 190 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 191 192 sc->sc_wdog_wtcon = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTCON); 193 sc->sc_wdog_armed = (sc->sc_wdog_wtcon & WTCON_ENABLE) 194 && (sc->sc_wdog_wtcon & WTCON_RESET_ENABLE); 195 if (sc->sc_wdog_armed) { 196 sc->sc_wdog_prescaler = 197 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_PRESCALER) + 1; 198 sc->sc_wdog_clock_select = 199 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_CLOCK_SELECT); 200 sc->sc_freq /= sc->sc_wdog_prescaler; 201 sc->sc_freq >>= 4 + sc->sc_wdog_clock_select; 202 sc->sc_wdog_wtdat = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTDAT); 203 sc->sc_wdog_period = (sc->sc_wdog_wtdat + 1) / sc->sc_freq; 204 } else { 205 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT; 206 sc->sc_wdog_prescaler = 1; 207 /* 208 * Let's see what clock select we should use. 209 */ 210 u_int n = __builtin_ffs(sc->sc_freq) - 1; 211 if (n > 7) { 212 sc->sc_wdog_clock_select = WTCON_CLOCK_SELECT_128; 213 sc->sc_freq >>= 7; 214 } else if (n >= 4) { 215 sc->sc_wdog_clock_select = n - 4; 216 sc->sc_freq >>= n; 217 } 218 /* 219 * Let's hope the timer frequency isn't prime. If it is, find 220 * the highest divisor which gives us the least remainder. 221 */ 222 sc->sc_wdog_prescaler = 0; 223 u_int best_remainder = 256; 224 u_int max_period = 2 * EXYNOS_WDT_PERIOD_DEFAULT * sc->sc_freq; 225 for (size_t div = 256; UINT16_MAX > div * max_period; div++) { 226 u_int remainder = sc->sc_freq % div; 227 if (remainder == 0) { 228 sc->sc_wdog_prescaler = div; 229 break; 230 } 231 if (remainder < best_remainder) { 232 sc->sc_wdog_prescaler = div; 233 best_remainder = remainder; 234 } 235 } 236 KASSERT(sc->sc_wdog_prescaler != 0); 237 sc->sc_freq /= sc->sc_wdog_prescaler; 238 } 239 240 /* 241 * Does the config file tell us to turn on the watchdog? 242 */ 243 if (device_cfdata(self)->cf_flags & 1) 244 sc->sc_wdog_armed = true; 245 246 aprint_naive("\n"); 247 aprint_normal(": Exynos Watchdog Timer, default period is %u seconds%s\n", 248 sc->sc_wdog_period, 249 sc->sc_wdog_armed ? " (armed)" : ""); 250 251 sc->sc_smw.smw_name = device_xname(self); 252 sc->sc_smw.smw_cookie = sc; 253 sc->sc_smw.smw_setmode = exynos_wdt_setmode; 254 sc->sc_smw.smw_tickle = exynos_wdt_tickle; 255 sc->sc_smw.smw_period = sc->sc_wdog_period; 256 257 if (sc->sc_wdog_armed) { 258 int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE, 259 sc->sc_wdog_period); 260 if (error) 261 aprint_error_dev(self, 262 "failed to start kernel tickler: %d\n", error); 263 } 264 } 265 #endif /* NEXYNOS_WDOG > 0 */ 266 267 void 268 exynos_wdt_reset(void) 269 { 270 bus_space_tag_t bst = &exynos_bs_tag; 271 bus_space_handle_t bsh = exynos_core_bsh; 272 bus_addr_t wdt_offset = 0; 273 #ifdef EXYNOS4 274 if (IS_EXYNOS4_P()) { 275 wdt_offset = EXYNOS4_WDT_OFFSET; 276 } 277 #endif 278 #ifdef EXYNOS5 279 if (IS_EXYNOS5_P()) { 280 wdt_offset = EXYNOS5_WDT_OFFSET; 281 } 282 #endif 283 KASSERT(wdt_offset); 284 285 (void) splhigh(); 286 bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCON, 0); 287 bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCNT, 1); 288 bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCON, 289 WTCON_ENABLE | WTCON_RESET_ENABLE); 290 } 291
Indexes created Thu Oct 02 14:10:14 GMT 2025