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exynos_wdt.c revision 1.3 
      1 /*	$NetBSD: exynos_wdt.c,v 1.3 2014/04/19 15:30:41 reinoud Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2012 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Matt Thomas
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include "exynos_wdt.h"
     33 
     34 #include <sys/cdefs.h>
     35 __KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.3 2014/04/19 15:30:41 reinoud Exp $");
     36 
     37 #include <sys/param.h>
     38 #include <sys/bus.h>
     39 #include <sys/cpu.h>
     40 #include <sys/device.h>
     41 #include <sys/wdog.h>
     42 
     43 #include <prop/proplib.h>
     44 
     45 #include <dev/sysmon/sysmonvar.h>
     46 
     47 #include <arm/samsung/exynos_reg.h>
     48 #include <arm/samsung/exynos_var.h>
     49 
     50 
     51 /* Watchdog register definitions */
     52 #define EXYNOS_WDT_WTCON		0x0000
     53 #define  WTCON_PRESCALER		__BITS(15,8)
     54 #define  WTCON_ENABLE			__BIT(5)
     55 #define  WTCON_CLOCK_SELECT		__BITS(4,3)
     56 #define  WTCON_CLOCK_SELECT_16		__SHIFTIN(0, WTCON_CLOCK_SELECT)
     57 #define  WTCON_CLOCK_SELECT_32		__SHIFTIN(1, WTCON_CLOCK_SELECT)
     58 #define  WTCON_CLOCK_SELECT_64		__SHIFTIN(2, WTCON_CLOCK_SELECT)
     59 #define  WTCON_CLOCK_SELECT_128		__SHIFTIN(3, WTCON_CLOCK_SELECT)
     60 #define  WTCON_INT_ENABLE		__BIT(2)
     61 #define  WTCON_RESET_ENABLE		__BIT(0)
     62 #define EXYNOS_WDT_WTDAT		0x0004
     63 #define  WTDAT_RELOAD			__BITS(15,0)
     64 #define EXYNOS_WDT_WTCNT		0x0008
     65 #define  WTCNT_COUNT			__BITS(15,0)
     66 #define EXYNOS_WDT_WTCLRINT		0x000C
     67 
     68 
     69 #if NEXYNOS_WDT > 0
     70 static int exynos_wdt_match(device_t, cfdata_t, void *);
     71 static void exynos_wdt_attach(device_t, device_t, void *);
     72 
     73 struct exynos_wdt_softc {
     74 	struct sysmon_wdog sc_smw;
     75 	device_t sc_dev;
     76 	bus_space_tag_t sc_bst;
     77 	bus_space_handle_t sc_wdog_bsh;
     78 	u_int sc_wdog_period;
     79 	u_int sc_wdog_clock_select;
     80 	u_int sc_wdog_prescaler;
     81 	uint32_t sc_freq;
     82 	uint32_t sc_wdog_wtdat;
     83 	uint32_t sc_wdog_wtcon;
     84 	bool sc_wdog_armed;
     85 };
     86 
     87 #ifndef EXYNOS_WDT_PERIOD_DEFAULT
     88 #define	EXYNOS_WDT_PERIOD_DEFAULT	12
     89 #endif
     90 
     91 CFATTACH_DECL_NEW(exynos_wdt, sizeof(struct exynos_wdt_softc),
     92     exynos_wdt_match, exynos_wdt_attach, NULL, NULL);
     93 
     94 static inline uint32_t
     95 exynos_wdt_wdog_read(struct exynos_wdt_softc *sc, bus_size_t o)
     96 {
     97 	return bus_space_read_4(sc->sc_bst, sc->sc_wdog_bsh, o);
     98 }
     99 
    100 static inline void
    101 exynos_wdt_wdog_write(struct exynos_wdt_softc *sc, bus_size_t o, uint32_t v)
    102 {
    103 	bus_space_write_4(sc->sc_bst, sc->sc_wdog_bsh, o, v);
    104 }
    105 
    106 /* ARGSUSED */
    107 static int
    108 exynos_wdt_match(device_t parent, cfdata_t cf, void *aux)
    109 {
    110 	return 1;
    111 }
    112 
    113 static int
    114 exynos_wdt_tickle(struct sysmon_wdog *smw)
    115 {
    116 	struct exynos_wdt_softc * const sc = smw->smw_cookie;
    117 
    118 	/*
    119 	 * Cause the WDOG to restart counting.
    120 	 */
    121 	exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat);
    122 	aprint_debug_dev(sc->sc_dev, "tickle\n");
    123 	return 0;
    124 }
    125 
    126 static int
    127 exynos_wdt_setmode(struct sysmon_wdog *smw)
    128 {
    129 	struct exynos_wdt_softc * const sc = smw->smw_cookie;
    130 
    131 	if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
    132 		/*
    133 		 * Emit magic sequence to turn off WDOG
    134 		 */
    135 		sc->sc_wdog_wtcon &= ~(WTCON_ENABLE|WTCON_RESET_ENABLE);
    136 		exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon);
    137 		delay(1);
    138 		aprint_debug_dev(sc->sc_dev, "setmode disable\n");
    139 		return 0;
    140 	}
    141 
    142 	/*
    143 	 * If no changes, just tickle it and return.
    144 	 */
    145 	if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
    146 		sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1;
    147 		sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE
    148 		    | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT)
    149 		    | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER);
    150 
    151 		exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat);
    152 		exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat);
    153 		exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon);
    154 		aprint_debug_dev(sc->sc_dev, "setmode refresh\n");
    155 		return 0;
    156 	}
    157 
    158 	if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
    159 		sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT;
    160 		smw->smw_period = EXYNOS_WDT_PERIOD_DEFAULT;
    161 	}
    162 
    163 	/*
    164 	 * Make sure we don't overflow the counter.
    165 	 */
    166 	if (smw->smw_period * sc->sc_freq >= UINT16_MAX) {
    167 		return EINVAL;
    168 	}
    169 
    170 	sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1;
    171 	sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE
    172 	    | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT)
    173 	    | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER);
    174 
    175 	/*
    176 	 * Have to disable to be able to write WTDAT
    177 	 */
    178 	exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON,
    179 	    sc->sc_wdog_wtcon & ~(WTCON_ENABLE | WTCON_RESET_ENABLE));
    180 	exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat);
    181 	exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat);
    182 	exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon);
    183 
    184 	aprint_debug_dev(sc->sc_dev, "setmode enable\n");
    185 	return 0;
    186 }
    187 
    188 
    189 static void
    190 exynos_wdt_attach(device_t parent, device_t self, void *aux)
    191 {
    192         struct exynos_wdt_softc * const sc = device_private(self);
    193 	struct exyo_attach_args * const exyo = aux;
    194 	prop_dictionary_t dict = device_properties(self);
    195 
    196 	sc->sc_dev = self;
    197 	sc->sc_bst = exyo->exyo_core_bst;
    198 
    199 	if (bus_space_subregion(sc->sc_bst, exyo->exyo_core_bsh,
    200 	    exyo->exyo_loc.loc_offset, exyo->exyo_loc.loc_size, &sc->sc_wdog_bsh)) {
    201 		aprint_error(": failed to map registers\n");
    202 		return;
    203 	}
    204 
    205 	/*
    206 	 * This runs at the Exynos Pclk.
    207 	 */
    208 	prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
    209 
    210 	sc->sc_wdog_wtcon = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTCON);
    211 	sc->sc_wdog_armed = (sc->sc_wdog_wtcon & WTCON_ENABLE)
    212 	    && (sc->sc_wdog_wtcon & WTCON_RESET_ENABLE);
    213 	if (sc->sc_wdog_armed) {
    214 		sc->sc_wdog_prescaler =
    215 		    __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_PRESCALER) + 1;
    216 		sc->sc_wdog_clock_select =
    217 		    __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_CLOCK_SELECT);
    218 		sc->sc_freq /= sc->sc_wdog_prescaler;
    219 		sc->sc_freq >>= 4 + sc->sc_wdog_clock_select;
    220 		sc->sc_wdog_wtdat = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTDAT);
    221 		sc->sc_wdog_period = (sc->sc_wdog_wtdat + 1) / sc->sc_freq;
    222 	} else {
    223 		sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT;
    224 		sc->sc_wdog_prescaler = 1;
    225 		/*
    226 		 * Let's see what clock select we should use.
    227 		 */
    228 		u_int n = __builtin_ffs(sc->sc_freq) - 1;
    229 		if (n > 7) {
    230 			sc->sc_wdog_clock_select = WTCON_CLOCK_SELECT_128;
    231 			sc->sc_freq >>= 7;
    232 		} else if (n >= 4) {
    233 			sc->sc_wdog_clock_select = n - 4;
    234 			sc->sc_freq >>= n;
    235 		}
    236 		/*
    237 		 * Let's hope the timer frequency isn't prime.  If it is, find
    238 		 * the highest divisor which gives us the least remainder.
    239 		 */
    240 		sc->sc_wdog_prescaler = 0;
    241 		u_int best_remainder = 256;
    242 		u_int max_period = 2 * EXYNOS_WDT_PERIOD_DEFAULT * sc->sc_freq;
    243 		for (size_t div = 256; UINT16_MAX > div * max_period; div++) {
    244 			u_int remainder = sc->sc_freq % div;
    245 			if (remainder == 0) {
    246 				sc->sc_wdog_prescaler = div;
    247 				break;
    248 			}
    249 			if (remainder < best_remainder) {
    250 				sc->sc_wdog_prescaler = div;
    251 				best_remainder = remainder;
    252 			}
    253 		}
    254 		KASSERT(sc->sc_wdog_prescaler != 0);
    255 		sc->sc_freq /= sc->sc_wdog_prescaler;
    256 	}
    257 
    258 	/*
    259 	 * Does the config file tell us to turn on the watchdog?
    260 	 */
    261 	if (device_cfdata(self)->cf_flags & 1)
    262 		sc->sc_wdog_armed = true;
    263 
    264 	aprint_naive("\n");
    265 	aprint_normal(": Exynos Watchdog Timer, default period is %u seconds%s\n",
    266 	    sc->sc_wdog_period,
    267 	    sc->sc_wdog_armed ? " (armed)" : "");
    268 
    269 	sc->sc_smw.smw_name = device_xname(self);
    270 	sc->sc_smw.smw_cookie = sc;
    271 	sc->sc_smw.smw_setmode = exynos_wdt_setmode;
    272 	sc->sc_smw.smw_tickle = exynos_wdt_tickle;
    273 	sc->sc_smw.smw_period = sc->sc_wdog_period;
    274 
    275 	if (sc->sc_wdog_armed) {
    276 		int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE,
    277 		    sc->sc_wdog_period);
    278 		if (error)
    279 			aprint_error_dev(self,
    280 			    "failed to start kernel tickler: %d\n", error);
    281  	}
    282 }
    283 #endif /* NEXYNOS_WDOG > 0 */
    284 
    285 void
    286 exynos_wdt_reset(void)
    287 {
    288 	bus_space_tag_t bst = &exynos_bs_tag;
    289 	bus_space_handle_t bsh = exynos_core_bsh;
    290 	bus_addr_t wdt_offset = 0;
    291 #ifdef EXYNOS4
    292 	if (IS_EXYNOS4_P()) {
    293 		wdt_offset = EXYNOS4_WDT_OFFSET;
    294 	}
    295 #endif
    296 #ifdef EXYNOS5
    297 	if (IS_EXYNOS5_P()) {
    298 		wdt_offset = EXYNOS5_WDT_OFFSET;
    299 	}
    300 #endif
    301 	KASSERT(wdt_offset);
    302 
    303 	(void) splhigh();
    304 	bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCON, 0);
    305 	bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCNT, 1);
    306 	bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCON,
    307 	   WTCON_ENABLE | WTCON_RESET_ENABLE);
    308 }
    309