exynos_wdt.c revision 1.9
1 /* $NetBSD: exynos_wdt.c,v 1.9 2015/12/21 04:58:50 marty Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "exynos_wdt.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.9 2015/12/21 04:58:50 marty Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 #include <sys/wdog.h> 42 43 #include <prop/proplib.h> 44 45 #include <dev/sysmon/sysmonvar.h> 46 47 #include <arm/samsung/exynos_reg.h> 48 #include <arm/samsung/exynos_var.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #if NEXYNOS_WDT > 0 53 static int exynos_wdt_match(device_t, cfdata_t, void *); 54 static void exynos_wdt_attach(device_t, device_t, void *); 55 56 struct exynos_wdt_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_wdog_bsh; 60 struct sysmon_wdog sc_smw; 61 u_int sc_wdog_period; 62 u_int sc_wdog_clock_select; 63 u_int sc_wdog_prescaler; 64 uint32_t sc_freq; 65 uint32_t sc_wdog_wtdat; 66 uint32_t sc_wdog_wtcon; 67 bool sc_wdog_armed; 68 }; 69 70 #ifndef EXYNOS_WDT_PERIOD_DEFAULT 71 #define EXYNOS_WDT_PERIOD_DEFAULT 60 72 #endif 73 74 CFATTACH_DECL_NEW(exynos_wdt, sizeof(struct exynos_wdt_softc), 75 exynos_wdt_match, exynos_wdt_attach, NULL, NULL); 76 77 static inline uint32_t 78 exynos_wdt_wdog_read(struct exynos_wdt_softc *sc, bus_size_t o) 79 { 80 return bus_space_read_4(sc->sc_bst, sc->sc_wdog_bsh, o); 81 } 82 83 static inline void 84 exynos_wdt_wdog_write(struct exynos_wdt_softc *sc, bus_size_t o, uint32_t v) 85 { 86 bus_space_write_4(sc->sc_bst, sc->sc_wdog_bsh, o, v); 87 } 88 89 /* ARGSUSED */ 90 static int 91 exynos_wdt_match(device_t parent, cfdata_t cf, void *aux) 92 { 93 const char * const compatible[] = { "samsung,s3c2410-wdt", NULL }; 94 struct fdt_attach_args * const faa = aux; 95 96 return of_match_compatible(faa->faa_phandle, compatible); 97 } 98 99 static int 100 exynos_wdt_tickle(struct sysmon_wdog *smw) 101 { 102 struct exynos_wdt_softc * const sc = smw->smw_cookie; 103 104 /* 105 * Cause the WDOG to restart counting. 106 */ 107 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 108 aprint_debug_dev(sc->sc_dev, "tickle\n"); 109 return 0; 110 } 111 112 static int 113 exynos_wdt_setmode(struct sysmon_wdog *smw) 114 { 115 struct exynos_wdt_softc * const sc = smw->smw_cookie; 116 117 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 118 /* 119 * Emit magic sequence to turn off WDOG 120 */ 121 sc->sc_wdog_wtcon &= ~(WTCON_ENABLE|WTCON_RESET_ENABLE); 122 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 123 delay(1); 124 aprint_debug_dev(sc->sc_dev, "setmode disable\n"); 125 return 0; 126 } 127 128 /* 129 * If no changes, just tickle it and return. 130 */ 131 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) { 132 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1; 133 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE 134 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT) 135 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER); 136 137 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 138 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat); 139 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 140 aprint_debug_dev(sc->sc_dev, "setmode refresh\n"); 141 return 0; 142 } 143 144 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 145 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT; 146 smw->smw_period = EXYNOS_WDT_PERIOD_DEFAULT; 147 } 148 149 /* 150 * Make sure we don't overflow the counter. 151 */ 152 if (smw->smw_period * sc->sc_freq >= UINT16_MAX) { 153 return EINVAL; 154 } 155 156 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1; 157 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE 158 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT) 159 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER); 160 161 /* 162 * Have to disable to be able to write WTDAT 163 */ 164 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, 165 sc->sc_wdog_wtcon & ~(WTCON_ENABLE | WTCON_RESET_ENABLE)); 166 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 167 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat); 168 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 169 170 aprint_debug_dev(sc->sc_dev, "setmode enable\n"); 171 return 0; 172 } 173 174 175 static void 176 exynos_wdt_attach(device_t parent, device_t self, void *aux) 177 { 178 struct exynos_wdt_softc * const sc = device_private(self); 179 // prop_dictionary_t dict = device_properties(self); 180 struct fdt_attach_args * const faa = aux; 181 bus_addr_t addr; 182 bus_size_t size; 183 int error; 184 185 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 186 aprint_error(": couldn't get registers\n"); 187 return; 188 } 189 190 sc->sc_dev = self; 191 sc->sc_bst = faa->faa_bst; 192 193 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_wdog_bsh); 194 if (error) { 195 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 196 return; 197 } 198 199 /* 200 * This runs at the Exynos Pclk. 201 */ 202 // prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 203 sc->sc_freq = 12000000; /* MJF: HACK hardwire for now */ 204 /* Need to figure out how to get freq from dtb */ 205 sc->sc_wdog_wtcon = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTCON); 206 sc->sc_wdog_armed = (sc->sc_wdog_wtcon & WTCON_ENABLE) 207 && (sc->sc_wdog_wtcon & WTCON_RESET_ENABLE); 208 if (sc->sc_wdog_armed) { 209 sc->sc_wdog_prescaler = 210 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_PRESCALER); 211 sc->sc_wdog_clock_select = 212 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_CLOCK_SELECT); 213 sc->sc_freq /= sc->sc_wdog_prescaler; 214 sc->sc_freq >>= 4 + sc->sc_wdog_clock_select; 215 sc->sc_wdog_wtdat = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTDAT); 216 sc->sc_wdog_period = (sc->sc_wdog_wtdat + 1) / sc->sc_freq; 217 } else { 218 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT; 219 sc->sc_wdog_prescaler = 1; 220 /* 221 * Let's see what clock select we should use. 222 */ 223 u_int n = __builtin_ffs(sc->sc_freq) - 1; 224 if (n > 7) { 225 sc->sc_wdog_clock_select = WTCON_CLOCK_SELECT_128; 226 sc->sc_freq >>= 7; 227 } else if (n >= 4) { 228 sc->sc_wdog_clock_select = n - 4; 229 sc->sc_freq >>= n; 230 } 231 /* 232 * Let's hope the timer frequency isn't prime. If it is, find 233 * the highest divisor which gives us the least remainder. 234 */ 235 sc->sc_wdog_prescaler = 0; 236 u_int best_remainder = 256; 237 u_int max_period = 2 * EXYNOS_WDT_PERIOD_DEFAULT * sc->sc_freq; 238 for (size_t div = 256; UINT16_MAX > div * max_period; div++) { 239 u_int remainder = sc->sc_freq % div; 240 if (remainder == 0) { 241 sc->sc_wdog_prescaler = div; 242 break; 243 } 244 if (remainder < best_remainder) { 245 sc->sc_wdog_prescaler = div; 246 best_remainder = remainder; 247 } 248 } 249 KASSERT(sc->sc_wdog_prescaler != 0); 250 sc->sc_freq /= sc->sc_wdog_prescaler; 251 } 252 253 /* 254 * Does the config file tell us to turn on the watchdog? 255 */ 256 if (device_cfdata(self)->cf_flags & 1) 257 sc->sc_wdog_armed = true; 258 259 aprint_naive("\n"); 260 aprint_normal(": Exynos Watchdog Timer, default period is %u seconds%s\n", 261 sc->sc_wdog_period, 262 sc->sc_wdog_armed ? " (armed)" : ""); 263 264 sc->sc_smw.smw_name = device_xname(self); 265 sc->sc_smw.smw_cookie = sc; 266 sc->sc_smw.smw_setmode = exynos_wdt_setmode; 267 sc->sc_smw.smw_tickle = exynos_wdt_tickle; 268 sc->sc_smw.smw_period = sc->sc_wdog_period; 269 270 if (sc->sc_wdog_armed) { 271 error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE, 272 sc->sc_wdog_period); 273 if (error) 274 aprint_error_dev(self, 275 "failed to start kernel tickler: %d\n", error); 276 } 277 } 278 #endif /* NEXYNOS_WDOG > 0 */ 279 280 void 281 exynos_wdt_reset(void) 282 { 283 bus_space_tag_t bst = &armv7_generic_bs_tag; 284 bus_space_handle_t bsh = exynos_wdt_bsh; 285 286 (void) splhigh(); 287 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON, 0); 288 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCNT, 1); 289 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON, 290 WTCON_ENABLE | WTCON_RESET_ENABLE); 291 } 292 293
Indexes created Thu Oct 02 14:10:14 GMT 2025