mct.c revision 1.14
1 /* $NetBSD: mct.c,v 1.14 2018/07/02 12:49:37 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk and Jared McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: mct.c,v 1.14 2018/07/02 12:49:37 jmcneill Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 #include <sys/kmem.h> 45 46 #include <prop/proplib.h> 47 48 #include <arm/samsung/exynos_reg.h> 49 #include <arm/samsung/exynos_var.h> 50 #include <arm/samsung/mct_reg.h> 51 #include <arm/samsung/mct_var.h> 52 53 #include <dev/fdt/fdtvar.h> 54 #include <arm/fdt/arm_fdtvar.h> 55 56 static struct mct_softc mct_sc; 57 58 static int mct_match(device_t, cfdata_t, void *); 59 static void mct_attach(device_t, device_t, void *); 60 61 static u_int mct_get_timecount(struct timecounter *); 62 63 static struct timecounter mct_timecounter = { 64 .tc_get_timecount = mct_get_timecount, 65 .tc_counter_mask = ~0u, 66 .tc_frequency = EXYNOS_F_IN_FREQ, 67 .tc_name = "MCT", 68 .tc_quality = 500, 69 .tc_priv = &mct_sc, 70 }; 71 72 CFATTACH_DECL_NEW(exyo_mct, 0, mct_match, mct_attach, NULL, NULL); 73 74 static inline uint32_t 75 mct_read_global(struct mct_softc *sc, bus_size_t o) 76 { 77 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, o); 78 } 79 80 static inline void 81 mct_write_global(struct mct_softc *sc, bus_size_t o, uint32_t v) 82 { 83 bus_size_t wreg; 84 uint32_t bit; 85 int i; 86 87 /* do the write */ 88 bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, v); 89 // printf("%s: write %#x at %#x\n", 90 // __func__, ((uint32_t) sc->sc_bsh + (uint32_t) o), v); 91 92 /* dependent on the write address, do the ack dance */ 93 if (o == MCT_G_CNT_L || o == MCT_G_CNT_U) { 94 wreg = MCT_G_CNT_WSTAT; 95 bit = (o == MCT_G_CNT_L) ? G_CNT_WSTAT_L : G_CNT_WSTAT_U; 96 } else { 97 switch (o) { 98 case MCT_G_COMP0_L: 99 wreg = MCT_G_WSTAT; 100 bit = G_WSTAT_COMP0_L; 101 break; 102 case MCT_G_COMP0_U: 103 wreg = MCT_G_WSTAT; 104 bit = G_WSTAT_COMP0_U; 105 break; 106 case MCT_G_COMP0_ADD_INCR: 107 wreg = MCT_G_WSTAT; 108 bit = G_WSTAT_ADD_INCR; 109 break; 110 case MCT_G_TCON: 111 wreg = MCT_G_WSTAT; 112 bit = G_WSTAT_TCON; 113 break; 114 case MCT_G_CNT_L: 115 wreg = MCT_G_CNT_WSTAT; 116 bit = G_CNT_WSTAT_L; 117 break; 118 case MCT_G_CNT_U: 119 wreg = MCT_G_CNT_WSTAT; 120 bit = G_CNT_WSTAT_U; 121 break; 122 default: 123 /* all other registers */ 124 return; 125 } 126 } 127 128 /* wait for ack */ 129 for (i = 0; i < 10000000; i++) { 130 /* value accepted by the hardware/hal ? */ 131 if (mct_read_global(sc, wreg) & bit) { 132 /* ack */ 133 bus_space_write_4(sc->sc_bst, sc->sc_bsh, wreg, bit); 134 return; 135 } 136 } 137 panic("MCT hangs after writing %#x at %#x", v, (uint32_t) o); 138 } 139 140 static void 141 mct_fdt_cpu_hatch(void *priv, struct cpu_info *ci) 142 { 143 panic("%s: not implemented", __func__); 144 } 145 146 static int 147 mct_intr(void *arg) 148 { 149 struct mct_softc * const sc = &mct_sc; 150 struct clockframe *frame = arg; 151 152 mct_write_global(sc, MCT_G_INT_CSTAT, G_INT_CSTAT_CLEAR); 153 154 hardclock(frame); 155 156 return 1; 157 } 158 159 static u_int 160 mct_get_timecount(struct timecounter *tc) 161 { 162 struct mct_softc * const sc = tc->tc_priv; 163 164 return mct_read_global(sc, MCT_G_CNT_L); 165 } 166 167 static uint64_t 168 mct_read_gcnt(struct mct_softc *sc) 169 { 170 uint32_t gcntl, gcntu; 171 172 do { 173 gcntu = mct_read_global(sc, MCT_G_CNT_U); 174 gcntl = mct_read_global(sc, MCT_G_CNT_L); 175 } while (gcntu != mct_read_global(sc, MCT_G_CNT_U)); 176 177 return ((uint64_t)gcntu << 32) | gcntl; 178 } 179 180 static void 181 mct_cpu_initclocks(void) 182 { 183 struct mct_softc * const sc = &mct_sc; 184 char intrstr[128]; 185 186 if (!fdtbus_intr_str(sc->sc_phandle, 0, intrstr, sizeof(intrstr))) 187 panic("%s: failed to decode interrupt", __func__); 188 189 sc->sc_global_ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_CLOCK, 190 FDT_INTR_MPSAFE, mct_intr, NULL); 191 if (sc->sc_global_ih == NULL) 192 panic("%s: failed to establish timer interrupt on %s", __func__, intrstr); 193 194 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 195 196 /* Start the timer */ 197 const u_int autoinc = sc->sc_freq / hz; 198 const uint64_t comp0 = mct_read_gcnt(sc) + autoinc; 199 200 mct_write_global(sc, MCT_G_TCON, G_TCON_START | G_TCON_COMP0_AUTOINC); 201 mct_write_global(sc, MCT_G_COMP0_ADD_INCR, autoinc); 202 mct_write_global(sc, MCT_G_COMP0_L, (uint32_t)comp0); 203 mct_write_global(sc, MCT_G_COMP0_U, (uint32_t)(comp0 >> 32)); 204 mct_write_global(sc, MCT_G_INT_ENB, G_INT_ENB_ENABLE); 205 mct_write_global(sc, MCT_G_TCON, G_TCON_START | G_TCON_COMP0_ENABLE | G_TCON_COMP0_AUTOINC); 206 } 207 208 static int 209 mct_match(device_t parent, cfdata_t cf, void *aux) 210 { 211 const char * const compatible[] = { "samsung,exynos4210-mct", 212 NULL }; 213 214 struct fdt_attach_args * const faa = aux; 215 return of_match_compatible(faa->faa_phandle, compatible); 216 } 217 218 static void 219 mct_attach(device_t parent, device_t self, void *aux) 220 { 221 struct mct_softc * const sc = &mct_sc; 222 struct fdt_attach_args * const faa = aux; 223 bus_addr_t addr; 224 bus_size_t size; 225 int error; 226 227 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 228 aprint_error(": couldn't get registers\n"); 229 return; 230 } 231 232 self->dv_private = sc; 233 sc->sc_dev = self; 234 sc->sc_phandle = faa->faa_phandle; 235 sc->sc_bst = faa->faa_bst; 236 sc->sc_freq = EXYNOS_F_IN_FREQ; 237 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 238 if (error) { 239 aprint_error(": couldn't map %#llx: %d", 240 (uint64_t)addr, error); 241 return; 242 } 243 244 aprint_naive("\n"); 245 aprint_normal(": Exynos SoC multi core timer (64 bits)\n"); 246 247 tc_init(&mct_timecounter); 248 249 arm_fdt_cpu_hatch_register(self, mct_fdt_cpu_hatch); 250 arm_fdt_timer_register(mct_cpu_initclocks); 251 } 252 253 void 254 mct_delay(u_int n) 255 { 256 struct mct_softc * const sc = &mct_sc; 257 uint64_t cur, prev; 258 259 if (sc->sc_bsh == 0) 260 panic("%s: mct driver not attached", __func__); 261 262 const long incs_per_us = sc->sc_freq / 1000000; 263 long ticks = n * incs_per_us; 264 265 prev = mct_read_gcnt(sc); 266 while (ticks > 0) { 267 cur = mct_read_gcnt(sc); 268 if (cur > prev) 269 ticks -= (cur - prev); 270 else 271 ticks -= (UINT64_MAX - cur + prev); 272 prev = cur; 273 } 274 } 275
Indexes created Sun Sep 28 07:09:56 GMT 2025