mct.c revision 1.3
1 /* $NetBSD: mct.c,v 1.3 2014/08/08 14:43:14 reinoud Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: mct.c,v 1.3 2014/08/08 14:43:14 reinoud Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 45 #include <prop/proplib.h> 46 47 #include <arm/samsung/exynos_reg.h> 48 #include <arm/samsung/exynos_var.h> 49 #include <arm/samsung/mct_reg.h> 50 #include <arm/samsung/mct_var.h> 51 52 53 static int mct_match(device_t, cfdata_t, void *); 54 static void mct_attach(device_t, device_t, void *); 55 56 static int clockhandler(void *); 57 static u_int mct_get_timecount(struct timecounter *); 58 59 60 CFATTACH_DECL_NEW(exyo_mct, 0, mct_match, mct_attach, NULL, NULL); 61 62 63 static struct timecounter mct_timecounter = { 64 .tc_get_timecount = mct_get_timecount, 65 .tc_poll_pps = 0, 66 .tc_counter_mask = ~0u, 67 .tc_frequency = 0, /* set by cpu_initclocks() */ 68 .tc_name = NULL, /* set by cpu_initclocks() */ 69 .tc_quality = 500, /* why 500? */ 70 .tc_priv = &mct_sc, 71 .tc_next = NULL, 72 }; 73 74 75 static inline uint32_t 76 mct_read_global(struct mct_softc *sc, bus_size_t o) 77 { 78 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, o); 79 } 80 81 82 static inline void 83 mct_write_global(struct mct_softc *sc, bus_size_t o, uint32_t v) 84 { 85 bus_size_t wreg; 86 uint32_t bit; 87 int i; 88 89 /* do the write */ 90 bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, v); 91 // printf("%s: write %#x at %#x\n", 92 // __func__, ((uint32_t) sc->sc_bsh + (uint32_t) o), v); 93 94 /* dependent on the write address, do the ack dance */ 95 if (o == MCT_G_CNT_L || o == MCT_G_CNT_U) { 96 wreg = MCT_G_CNT_WSTAT; 97 bit = (o == MCT_G_CNT_L) ? G_CNT_WSTAT_L : G_CNT_WSTAT_U; 98 } else { 99 wreg = MCT_G_WSTAT; 100 switch (o) { 101 case MCT_G_COMP0_L: 102 bit = G_WSTAT_COMP0_L; 103 break; 104 case MCT_G_COMP0_U: 105 bit = G_WSTAT_COMP0_U; 106 break; 107 case MCT_G_COMP0_ADD_INCR: 108 bit = G_WSTAT_ADD_INCR; 109 break; 110 case MCT_G_TCON: 111 bit = G_WSTAT_TCON; 112 break; 113 default: 114 /* all other registers */ 115 return; 116 } 117 } 118 119 /* wait for ack */ 120 for (i = 0; i < 10000000; i++) { 121 /* value accepted by the hardware/hal ? */ 122 if (mct_read_global(sc, wreg) & bit) { 123 /* ack */ 124 bus_space_write_4(sc->sc_bst, sc->sc_bsh, wreg, bit); 125 return; 126 } 127 } 128 panic("MCT hangs after writing %#x at %#x", v, (uint32_t) o); 129 } 130 131 132 static int 133 mct_match(device_t parent, cfdata_t cf, void *aux) 134 { 135 /* not used if Generic Timer is Available */ 136 if (armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) 137 return 0; 138 139 /* sanity check, something is mixed up! */ 140 if (!device_is_a(parent, "exyo")) 141 return 1; 142 143 /* there can only be one */ 144 if (mct_sc.sc_dev != NULL) 145 return 0; 146 147 return 1; 148 } 149 150 151 static void 152 mct_attach(device_t parent, device_t self, void *aux) 153 { 154 struct exyo_attach_args *exyo = (struct exyo_attach_args *) aux; 155 struct mct_softc * const sc = &mct_sc; 156 prop_dictionary_t dict = device_properties(self); 157 char freqbuf[sizeof("XXX SHz")]; 158 const char *pin_name; 159 160 self->dv_private = sc; 161 sc->sc_dev = self; 162 sc->sc_bst = exyo->exyo_core_bst; 163 sc->sc_irq = exyo->exyo_loc.loc_intr; 164 165 bus_space_subregion(sc->sc_bst, exyo->exyo_core_bsh, 166 exyo->exyo_loc.loc_offset, exyo->exyo_loc.loc_size, &sc->sc_bsh); 167 168 KASSERTMSG(sc->sc_bsh, 169 "%s: can't map in registers for %#x + %#x for device %s\n", 170 __func__, 171 (uint32_t) exyo->exyo_loc.loc_offset, 172 (uint32_t) exyo->exyo_loc.loc_size, 173 device_xname(sc->sc_dev)); 174 175 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 176 177 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 178 179 aprint_naive("\n"); 180 aprint_normal(": Exynos SoC multi core timer (64 bits) (%s)\n", freqbuf); 181 182 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 183 device_xname(self), "missing interrupts"); 184 185 sc->sc_global_ih = intr_establish(sc->sc_irq, IPL_CLOCK, IST_EDGE, 186 clockhandler, NULL); 187 if (sc->sc_global_ih == NULL) 188 panic("%s: unable to register timer interrupt", __func__); 189 aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n", sc->sc_irq); 190 191 /* blink led */ 192 if (prop_dictionary_get_cstring_nocopy(dict, "heartbeat", &pin_name)) { 193 if (!exynos_gpio_pin_reserve(pin_name, &sc->sc_gpio_led)) { 194 aprint_error_dev(self, 195 "failed to reserve GPIO \"%s\" " 196 "for heartbeat led\n", pin_name); 197 } else { 198 sc->sc_has_blink_led = true; 199 sc->sc_led_state = false; 200 sc->sc_led_timer = hz; 201 } 202 } 203 } 204 205 206 static inline uint64_t 207 mct_gettime(struct mct_softc *sc) 208 { 209 uint32_t lo, hi; 210 do { 211 hi = mct_read_global(sc, MCT_G_CNT_U); 212 lo = mct_read_global(sc, MCT_G_CNT_L); 213 } while (hi != mct_read_global(sc, MCT_G_CNT_U)); 214 return ((uint64_t) hi << 32) | lo; 215 } 216 217 218 static u_int 219 mct_get_timecount(struct timecounter *tc) 220 { 221 struct mct_softc * const sc = tc->tc_priv; 222 return (u_int) (mct_gettime(sc)); 223 } 224 225 226 /* interrupt handler */ 227 static int 228 clockhandler(void *arg) 229 { 230 struct clockframe * const cf = arg; 231 struct mct_softc * const sc = &mct_sc; 232 const uint64_t now = mct_gettime(sc); 233 int64_t delta = now - sc->sc_lastintr; 234 int64_t periods = delta / sc->sc_autoinc; 235 236 KASSERT(delta >= 0); 237 KASSERT(periods >= 0); 238 239 /* ack the interrupt */ 240 mct_write_global(sc, MCT_G_INT_CSTAT, G_INT_CSTAT_CLEAR); 241 242 /* check if we periods clock interrupts */ 243 if (periods > 1) 244 sc->sc_ev_missing_ticks.ev_count += periods - 1; 245 246 sc->sc_lastintr = now; 247 hardclock(cf); 248 249 if (sc->sc_has_blink_led) { 250 sc->sc_led_timer = sc->sc_led_timer - periods - 1; 251 if (sc->sc_led_timer <= 0) { 252 sc->sc_led_state = !sc->sc_led_state; 253 exynos_gpio_pindata_write(&sc->sc_gpio_led, 254 sc->sc_led_state); 255 while (sc->sc_led_timer <= 0) 256 sc->sc_led_timer += hz; 257 } 258 } 259 260 /* handled */ 261 return 1; 262 } 263 264 265 void 266 mct_init_cpu_clock(struct cpu_info *ci) 267 { 268 struct mct_softc * const sc = &mct_sc; 269 uint64_t now = mct_gettime(sc); 270 uint64_t then; 271 uint32_t tcon; 272 273 KASSERT(ci == curcpu()); 274 275 sc->sc_lastintr = now; 276 277 /* get current config */ 278 tcon = mct_read_global(sc, MCT_G_TCON); 279 280 /* setup auto increment */ 281 mct_write_global(sc, MCT_G_COMP0_ADD_INCR, sc->sc_autoinc); 282 283 /* (re)setup comparator */ 284 then = now + sc->sc_autoinc; 285 mct_write_global(sc, MCT_G_COMP0_L, (uint32_t) then); 286 mct_write_global(sc, MCT_G_COMP0_U, (uint32_t) (then >> 32)); 287 tcon |= G_TCON_COMP0_AUTOINC; 288 tcon |= G_TCON_COMP0_ENABLE; 289 290 /* start timer */ 291 tcon |= G_TCON_START; 292 293 /* enable interrupt */ 294 mct_write_global(sc, MCT_G_INT_ENB, G_INT_ENB_ENABLE); 295 296 /* update config, starting the thing */ 297 mct_write_global(sc, MCT_G_TCON, tcon); 298 } 299 300 301 void 302 cpu_initclocks(void) 303 { 304 struct mct_softc * const sc = &mct_sc; 305 306 sc->sc_autoinc = sc->sc_freq / hz; 307 mct_init_cpu_clock(curcpu()); 308 309 mct_timecounter.tc_name = device_xname(sc->sc_dev); 310 mct_timecounter.tc_frequency = sc->sc_freq; 311 312 tc_init(&mct_timecounter); 313 314 #if 0 315 { 316 uint64_t then, now; 317 318 printf("testing timer\n"); 319 for (int i = 0; i < 200; i++) { 320 printf("cstat %d\n", mct_read_global(sc, MCT_G_INT_CSTAT)); 321 then = mct_get_timecount(&mct_timecounter); 322 do { 323 now = mct_get_timecount(&mct_timecounter); 324 } while (now == then); 325 printf("\tgot %"PRIu64"\n", now); 326 for (int j = 0; j < 90000; j++); 327 } 328 printf("passed\n"); 329 } 330 #endif 331 } 332 333 334 void 335 setstatclockrate(int newhz) 336 { 337 } 338 339
Indexes created Sun Sep 28 16:09:52 GMT 2025