if_scx.c revision 1.1
1 /* $NetBSD: if_scx.c,v 1.1 2020/03/23 03:25:06 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 32 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~31 are for supplimental MAC addresses. Independently enabled 47 * for use. Good to catch multicast. Byte-wise selective match available. 48 * Use to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - The size of multicast hash filter store is unknown. Might be 256 bit. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.1 2020/03/23 03:25:06 nisimura Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 #include <sys/device.h> 59 #include <sys/callout.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/errno.h> 63 #include <sys/rndsource.h> 64 #include <sys/kernel.h> 65 #include <sys/systm.h> 66 67 #include <net/if.h> 68 #include <net/if_media.h> 69 #include <net/if_dl.h> 70 #include <net/if_ether.h> 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 #include <net/bpf.h> 74 75 #include <dev/fdt/fdtvar.h> 76 #include <dev/acpi/acpireg.h> 77 #include <dev/acpi/acpivar.h> 78 #include <dev/acpi/acpi_intr.h> 79 80 #define SWRESET 0x104 81 #define COMINIT 0x120 82 #define INTRST 0x200 83 #define IRQ_RX (1U<<1) 84 #define IRQ_TX (1U<<0) 85 #define INTREN 0x204 86 #define INTR_SET 0x234 87 #define INTR_CLR 0x238 88 #define TXINTST 0x400 89 #define TXINTEN 0x404 90 #define TXINT_SET 0x428 91 #define TXINT_CLR 0x42c 92 #define TXI_NTOWNR (1U<<17) 93 #define TXI_TR_ERR (1U<<16) 94 #define TXI_TXDONE (1U<<15) 95 #define TXI_TMREXP (1U<<14) 96 #define RXINTST 0x440 97 #define RXINTEN 0x444 98 #define RXINT_SET 0x468 99 #define RXINT_CLR 0x46c 100 #define RXI_RC_ERR (1U<<16) 101 #define RXI_PKTCNT (1U<<15) 102 #define RXI_TMREXP (1U<<14) 103 #define TXTIMER 0x41c 104 #define RXTIMER 0x45c 105 #define TXCOUNT 0x410 106 #define RXCOUNT 0x454 107 #define DMACH2M 0x210 /* DMAC host2media ucode port */ 108 #define DMACM2H 0x21c /* DMAC media2host ucode port */ 109 #define PKTENG 0x0d0 /* packet engine ucode port */ 110 #define HWVER0 0x22c 111 #define HWVER1 0x230 112 113 #define MACSTAT 0x1024 /* gmac status */ 114 #define MACDATA 0x11c0 /* gmac rd/wr data */ 115 #define MACCMD 0x11c4 /* gmac operation */ 116 #define CMD_IOWR (1U<<28) /* write op */ 117 #define CMD_BUSY (1U<<31) /* busy bit */ 118 #define DESCENG_INIT 0x11fc 119 #define DESCENG_SRST 0x1204 120 121 #define GMACMCR 0x0000 /* MAC configuration */ 122 #define MCR_IBN (1U<<30) /* */ 123 #define MCR_CST (1U<<25) /* strip CRC */ 124 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 125 #define MCR_JE (1U<<20) /* ignore oversized >9018 frame */ 126 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 127 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 128 #define MCR_USEFDX (1U<<11) /* force full duplex */ 129 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 130 #define MCR_ACS (1U<<7) /* auto pad CRC strip */ 131 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 132 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 133 #define _MCR_FDX 0x0000280c /* XXX TBD */ 134 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 135 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 136 #define AFR_RA (1U<<31) /* receive all on */ 137 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 138 #define AFR_SAF (1U<<9) /* source address filter */ 139 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 140 #define AFR_PCF (3U<<6) /* */ 141 #define AFR_RB (1U<<5) /* reject broadcast frame */ 142 #define AFR_AM (1U<<4) /* accept all multicast frame */ 143 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 144 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 145 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 146 #define AFR_PM (1U<<0) /* run promisc mode */ 147 #define _AFR 0x80000001 /* XXX TBD */ 148 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 149 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 150 #define GMACGAR 0x0010 /* MDIO operation */ 151 #define GAR_PHY (11) /* mii phy 15:11 */ 152 #define GAR_REG (6) /* mii reg 10:6 */ 153 #define GAR_CTL (2) /* control 5:2 */ 154 #define GAR_IOWR (1U<<1) /* MDIO write op */ 155 #define GAR_BUSY (1U) /* busy bit */ 156 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 157 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 158 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 159 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 160 #define GMACIMPL 0x0020 /* (dig this number XXXX.YYYY) */ 161 #define GMACVTAG 0x001c /* VLAN tag control */ 162 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 163 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 164 #define GMACMAH(i) ((i)*8+0x40) /* 0 - 15 */ 165 #define GMACMAL(i) ((i)*8+0x44) 166 #define GMACMHT0 0x0500 /* multcast hash table 0 - 8*/ 167 #define GMACBMR 0x1000 /* DMA bus mode 168 * 24 4PBL 169 * 22:17 RPBL 170 * 16 fix burst 171 * 15:14 priority between Rx and Tx 172 * 3 rxtx41 173 * 2 rxtx31 174 * 1 rxtx21 175 * 0 rxtx11 176 * 13:8 PBL possible DMA burst len 177 * 0 reset op. self clear 178 */ 179 #define _BMR 0x00412080 /* XXX TBD */ 180 #define _BMR0 0x00020181 /* XXX TBD */ 181 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 182 #define GMACRDLAR 0x100c /* */ 183 #define _RDLAR 0x18000 /* XXX TBD */ 184 #define GMACTDLAR 0x1010 /* */ 185 #define _TDLAR 0x1c000 /* XXX TBD */ 186 #define GMACOMR 0x1018 /* DMA operation */ 187 #define OMR_TXE (1U<<13) /* start Tx DMA engine */ 188 #define OMR_RXE (1U<<1) /* start Rx DMA engine */ 189 190 const struct { 191 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 192 } garclk[] = { 193 { 35, 2 }, /* 25-35 MHz */ 194 { 60, 3 }, /* 35-60 MHz */ 195 { 100, 0 }, /* 60-100 MHz */ 196 { 150, 1 }, /* 100-150 MHz */ 197 { 250, 4 }, /* 150-250 MHz */ 198 { 300, 5 }, /* 250-300 MHz */ 199 { 0 }, 200 }; 201 static int get_garclk(uint32_t); 202 203 /* descriptor format definition */ 204 struct tdes { 205 uint32_t t0, t1, t2, t3; 206 }; 207 208 struct rdes { 209 uint32_t r0, r1, r2, r3; 210 }; 211 212 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 213 #define T0_EOD (1U<<30) /* end of descriptor array */ 214 #define T0_DRID (24) /* 29:24 DRID */ 215 #define T0_PT (1U<<21) /* 23:21 PT */ 216 #define T0_TRID (16) /* 20:16 TRID */ 217 #define T0_FS (1U<<9) /* first segment of frame */ 218 #define T0_LS (1U<<8) /* last segment of frame */ 219 #define T0_CSUM (1U<<7) /* enable check sum offload */ 220 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 221 #define T0_TRS (1U<<4) /* 5:4 TRS */ 222 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 223 /* T1 segment address 63:32 */ 224 /* T2 segment address 31:0 */ 225 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 226 #define R0_OWN (1U<<31) /* desc is empty */ 227 #define R0_EOD (1U<<30) /* end of descriptor array */ 228 #define R0_SRID (24) /* 29:24 SRID */ 229 #define R0_FR (1U<<23) /* FR */ 230 #define R0_ER (1U<<21) /* Rx error indication */ 231 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 232 #define R0_TDRID (14) /* 15:14 TDRID */ 233 #define R0_FS (1U<<9) /* first segment of frame */ 234 #define R0_LS (1U<<8) /* last segment of frame */ 235 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 236 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 237 /* R1 frame address 63:32 */ 238 /* R2 frame address 31:0 */ 239 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 240 241 #define SCX_NTXSEGS 16 242 #define SCX_TXQUEUELEN 16 243 #define SCX_TXQUEUELEN_MASK (SCX_TXQUEUELEN - 1) 244 #define SCX_TXQUEUE_GC (SCX_TXQUEUELEN / 4) 245 #define SCX_NTXDESC (SCX_TXQUEUELEN * SCX_NTXSEGS) 246 #define SCX_NTXDESC_MASK (SCX_NTXDESC - 1) 247 #define SCX_NEXTTX(x) (((x) + 1) & SCX_NTXDESC_MASK) 248 #define SCX_NEXTTXS(x) (((x) + 1) & SCX_TXQUEUELEN_MASK) 249 250 #define SCX_NRXDESC 64 251 #define SCX_NRXDESC_MASK (SCX_NRXDESC - 1) 252 #define SCX_NEXTRX(x) (((x) + 1) & SCX_NRXDESC_MASK) 253 254 #define SCX_INIT_RXDESC(sc, x) \ 255 do { \ 256 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 257 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 258 struct mbuf *__m = __rxs->rxs_mbuf; \ 259 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 260 __m->m_data = __m->m_ext.ext_buf; \ 261 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 262 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 263 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 264 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 265 if ((x) == SCX_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 266 } while (/*CONSTCOND*/0) 267 268 struct control_data { 269 struct tdes cd_txdescs[SCX_NTXDESC]; 270 struct rdes cd_rxdescs[SCX_NRXDESC]; 271 }; 272 #define SCX_CDOFF(x) offsetof(struct control_data, x) 273 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 274 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 275 276 struct scx_txsoft { 277 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 278 bus_dmamap_t txs_dmamap; /* our DMA map */ 279 int txs_firstdesc; /* first descriptor in packet */ 280 int txs_lastdesc; /* last descriptor in packet */ 281 int txs_ndesc; /* # of descriptors used */ 282 }; 283 284 struct scx_rxsoft { 285 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 286 bus_dmamap_t rxs_dmamap; /* our DMA map */ 287 }; 288 289 struct scx_softc { 290 device_t sc_dev; /* generic device information */ 291 bus_space_tag_t sc_st; /* bus space tag */ 292 bus_space_handle_t sc_sh; /* bus space handle */ 293 bus_size_t sc_sz; /* csr map size */ 294 bus_space_handle_t sc_eesh; /* eeprom section handle */ 295 bus_size_t sc_eesz; /* eeprom map size */ 296 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 297 struct ethercom sc_ethercom; /* Ethernet common data */ 298 struct mii_data sc_mii; /* MII */ 299 callout_t sc_tick_ch; /* PHY monitor callout */ 300 int sc_flowflags; /* 802.3x PAUSE flow control */ 301 void *sc_ih; /* interrupt cookie */ 302 bus_dma_segment_t sc_seg; /* descriptor store seg */ 303 int sc_nseg; /* descriptor store nseg */ 304 int sc_phy_id; /* PHY address */ 305 uint32_t sc_gar; /* GAR 5:2 clock selection */ 306 int sc_phandle; /* fdt phandle */ 307 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL */ 308 309 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 310 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 311 312 struct control_data *sc_control_data; 313 #define sc_txdescs sc_control_data->cd_txdescs 314 #define sc_rxdescs sc_control_data->cd_rxdescs 315 316 struct scx_txsoft sc_txsoft[SCX_TXQUEUELEN]; 317 struct scx_rxsoft sc_rxsoft[SCX_NRXDESC]; 318 int sc_txfree; /* number of free Tx descriptors */ 319 int sc_txnext; /* next ready Tx descriptor */ 320 int sc_txsfree; /* number of free Tx jobs */ 321 int sc_txsnext; /* next ready Tx job */ 322 int sc_txsdirty; /* dirty Tx jobs */ 323 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 324 325 krndsource_t rnd_source; /* random source */ 326 }; 327 328 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 329 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 330 331 #define SCX_CDTXSYNC(sc, x, n, ops) \ 332 do { \ 333 int __x, __n; \ 334 \ 335 __x = (x); \ 336 __n = (n); \ 337 \ 338 /* If it will wrap around, sync to the end of the ring. */ \ 339 if ((__x + __n) > SCX_NTXDESC) { \ 340 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 341 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 342 (SCX_NTXDESC - __x), (ops)); \ 343 __n -= (SCX_NTXDESC - __x); \ 344 __x = 0; \ 345 } \ 346 \ 347 /* Now sync whatever is left. */ \ 348 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 349 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 350 } while (/*CONSTCOND*/0) 351 352 #define SCX_CDRXSYNC(sc, x, ops) \ 353 do { \ 354 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 355 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 356 } while (/*CONSTCOND*/0) 357 358 static int scx_fdt_match(device_t, cfdata_t, void *); 359 static void scx_fdt_attach(device_t, device_t, void *); 360 static int scx_acpi_match(device_t, cfdata_t, void *); 361 static void scx_acpi_attach(device_t, device_t, void *); 362 363 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 364 scx_fdt_match, scx_fdt_attach, NULL, NULL); 365 366 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 367 scx_acpi_match, scx_acpi_attach, NULL, NULL); 368 369 static void scx_attach_i(struct scx_softc *); 370 static void scx_reset(struct scx_softc *); 371 static int scx_init(struct ifnet *); 372 static void scx_start(struct ifnet *); 373 static void scx_stop(struct ifnet *, int); 374 static void scx_watchdog(struct ifnet *); 375 static int scx_ioctl(struct ifnet *, u_long, void *); 376 static void scx_set_rcvfilt(struct scx_softc *); 377 static int scx_ifmedia_upd(struct ifnet *); 378 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 379 static void mii_statchg(struct ifnet *); 380 static void phy_tick(void *); 381 static int mii_readreg(device_t, int, int, uint16_t *); 382 static int mii_writereg(device_t, int, int, uint16_t); 383 static int scx_intr(void *); 384 static void txreap(struct scx_softc *); 385 static void rxintr(struct scx_softc *); 386 static int add_rxbuf(struct scx_softc *, int); 387 static int spin_waitfor(struct scx_softc *, int, int); 388 static int mac_read(struct scx_softc *, int); 389 static void mac_write(struct scx_softc *, int, int); 390 static void loaducode(struct scx_softc *); 391 static void injectucode(struct scx_softc *, int, uint64_t, uint32_t); 392 393 #define CSR_READ(sc,off) \ 394 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 395 #define CSR_WRITE(sc,off,val) \ 396 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 397 #define EE_READ(sc,off) \ 398 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 399 400 static int 401 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 402 { 403 static const char * compatible[] = { 404 "socionext,synquacer-netsec", 405 NULL 406 }; 407 struct fdt_attach_args * const faa = aux; 408 409 return of_match_compatible(faa->faa_phandle, compatible); 410 } 411 412 static void 413 scx_fdt_attach(device_t parent, device_t self, void *aux) 414 { 415 struct scx_softc * const sc = device_private(self); 416 struct fdt_attach_args * const faa = aux; 417 const int phandle = faa->faa_phandle; 418 bus_space_tag_t bst = faa->faa_bst; 419 bus_space_handle_t bsh; 420 bus_space_handle_t eebsh; 421 bus_addr_t addr; 422 bus_size_t size; 423 char intrstr[128]; 424 425 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 426 || bus_space_map(faa->faa_bst, addr, size, 0, &bsh) != 0) { 427 aprint_error(": unable to map device csr\n"); 428 return; 429 } 430 sc->sc_sz = size; 431 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 432 aprint_error(": failed to decode interrupt\n"); 433 goto fail; 434 } 435 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 436 NOT_MP_SAFE, scx_intr, sc); 437 if (sc->sc_ih == NULL) { 438 aprint_error_dev(self, "couldn't establish interrupt\n"); 439 goto fail; 440 } 441 if (fdtbus_get_reg(phandle, 1, &addr, &size) != 0 442 || bus_space_map(faa->faa_bst, addr, size, 0, &eebsh) != 0) { 443 aprint_error(": unable to map device eeprom\n"); 444 goto fail; 445 } 446 sc->sc_eesz = size; 447 448 aprint_naive("\n"); 449 aprint_normal(": Gigabit Ethernet Controller\n"); 450 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 451 452 sc->sc_dev = self; 453 sc->sc_st = bst; 454 sc->sc_sh = bsh; 455 sc->sc_eesh = eebsh; 456 sc->sc_dmat = faa->faa_dmat; 457 sc->sc_phandle = phandle; 458 459 scx_attach_i(sc); 460 return; 461 fail: 462 if (sc->sc_eesz) 463 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 464 if (sc->sc_sz) 465 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 466 return; 467 } 468 469 static int 470 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 471 { 472 static const char * compatible[] = { 473 "SCX0001", 474 NULL 475 }; 476 struct acpi_attach_args *aa = aux; 477 478 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 479 return 0; 480 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 481 } 482 483 static void 484 scx_acpi_attach(device_t parent, device_t self, void *aux) 485 { 486 struct scx_softc * const sc = device_private(self); 487 struct acpi_attach_args * const aa = aux; 488 ACPI_HANDLE handle = aa->aa_node->ad_handle; 489 bus_space_tag_t bst = aa->aa_memt; 490 bus_space_handle_t bsh, eebsh; 491 struct acpi_resources res; 492 struct acpi_mem *mem; 493 struct acpi_irq *irq; 494 ACPI_STATUS rv; 495 496 rv = acpi_resource_parse(self, handle, "_CRS", 497 &res, &acpi_resource_parse_ops_default); 498 if (ACPI_FAILURE(rv)) 499 return; 500 mem = acpi_res_mem(&res, 0); 501 irq = acpi_res_irq(&res, 0); 502 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 503 aprint_error(": incomplete csr resources\n"); 504 return; 505 } 506 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 507 aprint_error(": couldn't map registers\n"); 508 return; 509 } 510 sc->sc_sz = mem->ar_length; 511 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 512 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 513 if (sc->sc_ih == NULL) { 514 aprint_error_dev(self, "couldn't establish interrupt\n"); 515 goto fail; 516 } 517 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 518 if (mem == NULL || mem->ar_length == 0) { 519 aprint_error(": incomplete eeprom resources\n"); 520 goto fail; 521 } 522 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 523 aprint_error(": couldn't map registers\n"); 524 goto fail; 525 } 526 sc->sc_eesz = mem->ar_length; 527 528 aprint_naive("\n"); 529 aprint_normal(": Gigabit Ethernet Controller\n"); 530 531 sc->sc_dev = self; 532 sc->sc_st = bst; 533 sc->sc_sh = bsh; 534 sc->sc_eesh = eebsh; 535 sc->sc_dmat = aa->aa_dmat64; 536 537 scx_attach_i(sc); 538 539 acpi_resource_cleanup(&res); 540 return; 541 fail: 542 if (sc->sc_eesz > 0) 543 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 544 if (sc->sc_sz > 0) 545 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 546 acpi_resource_cleanup(&res); 547 return; 548 } 549 550 static void 551 scx_attach_i(struct scx_softc *sc) 552 { 553 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 554 struct mii_data * const mii = &sc->sc_mii; 555 struct ifmedia * const ifm = &mii->mii_media; 556 uint32_t hwver, phyfreq; 557 uint8_t enaddr[ETHER_ADDR_LEN]; 558 bus_dma_segment_t seg; 559 uint32_t csr; 560 int i, nseg, error = 0; 561 562 hwver = CSR_READ(sc, HWVER1); 563 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 564 enaddr[0] = csr >> 24; 565 enaddr[1] = csr >> 16; 566 enaddr[2] = csr >> 8; 567 enaddr[3] = csr; 568 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 569 enaddr[4] = csr >> 24; 570 enaddr[5] = csr >> 16; 571 572 aprint_normal_dev(sc->sc_dev, "NetSec GbE (%d.%d)\n", 573 hwver >> 16, hwver & 0xffff); 574 aprint_normal_dev(sc->sc_dev, 575 "Ethernet address %s\n", ether_sprintf(enaddr)); 576 577 phyfreq = 0; 578 sc->sc_phy_id = MII_PHY_ANY; 579 sc->sc_gar = get_garclk(phyfreq) << GAR_CTL; /* 5:2 gar control */ 580 581 sc->sc_flowflags = 0; 582 583 if (0/*CONSTCOND*/) 584 loaducode(sc); 585 586 mii->mii_ifp = ifp; 587 mii->mii_readreg = mii_readreg; 588 mii->mii_writereg = mii_writereg; 589 mii->mii_statchg = mii_statchg; 590 591 sc->sc_ethercom.ec_mii = mii; 592 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 593 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 594 MII_OFFSET_ANY, MIIF_DOPAUSE); 595 if (LIST_FIRST(&mii->mii_phys) == NULL) { 596 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 597 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 598 } else 599 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 600 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 601 602 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 603 ifp->if_softc = sc; 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_ioctl = scx_ioctl; 606 ifp->if_start = scx_start; 607 ifp->if_watchdog = scx_watchdog; 608 ifp->if_init = scx_init; 609 ifp->if_stop = scx_stop; 610 IFQ_SET_READY(&ifp->if_snd); 611 612 if_attach(ifp); 613 if_deferred_start_init(ifp, NULL); 614 ether_ifattach(ifp, enaddr); 615 616 callout_init(&sc->sc_tick_ch, 0); 617 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 618 619 /* 620 * Allocate the control data structures, and create and load the 621 * DMA map for it. 622 */ 623 error = bus_dmamem_alloc(sc->sc_dmat, 624 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 625 if (error != 0) { 626 aprint_error_dev(sc->sc_dev, 627 "unable to allocate control data, error = %d\n", error); 628 goto fail_0; 629 } 630 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 631 sizeof(struct control_data), (void **)&sc->sc_control_data, 632 BUS_DMA_COHERENT); 633 if (error != 0) { 634 aprint_error_dev(sc->sc_dev, 635 "unable to map control data, error = %d\n", error); 636 goto fail_1; 637 } 638 error = bus_dmamap_create(sc->sc_dmat, 639 sizeof(struct control_data), 1, 640 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 641 if (error != 0) { 642 aprint_error_dev(sc->sc_dev, 643 "unable to create control data DMA map, " 644 "error = %d\n", error); 645 goto fail_2; 646 } 647 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 648 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 649 if (error != 0) { 650 aprint_error_dev(sc->sc_dev, 651 "unable to load control data DMA map, error = %d\n", 652 error); 653 goto fail_3; 654 } 655 for (i = 0; i < SCX_TXQUEUELEN; i++) { 656 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 657 SCX_NTXSEGS, MCLBYTES, 0, 0, 658 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 659 aprint_error_dev(sc->sc_dev, 660 "unable to create tx DMA map %d, error = %d\n", 661 i, error); 662 goto fail_4; 663 } 664 } 665 for (i = 0; i < SCX_NRXDESC; i++) { 666 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 667 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 668 aprint_error_dev(sc->sc_dev, 669 "unable to create rx DMA map %d, error = %d\n", 670 i, error); 671 goto fail_5; 672 } 673 sc->sc_rxsoft[i].rxs_mbuf = NULL; 674 } 675 sc->sc_seg = seg; 676 sc->sc_nseg = nseg; 677 printf("bus_dmaseg ds_addr %08lx, ds_len %08lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 678 679 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 680 pmf_class_network_register(sc->sc_dev, ifp); 681 else 682 aprint_error_dev(sc->sc_dev, 683 "couldn't establish power handler\n"); 684 685 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 686 RND_TYPE_NET, RND_FLAG_DEFAULT); 687 688 return; 689 690 fail_5: 691 for (i = 0; i < SCX_NRXDESC; i++) { 692 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 693 bus_dmamap_destroy(sc->sc_dmat, 694 sc->sc_rxsoft[i].rxs_dmamap); 695 } 696 fail_4: 697 for (i = 0; i < SCX_TXQUEUELEN; i++) { 698 if (sc->sc_txsoft[i].txs_dmamap != NULL) 699 bus_dmamap_destroy(sc->sc_dmat, 700 sc->sc_txsoft[i].txs_dmamap); 701 } 702 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 703 fail_3: 704 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 705 fail_2: 706 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 707 sizeof(struct control_data)); 708 fail_1: 709 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 710 fail_0: 711 if (sc->sc_phandle) 712 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 713 else 714 acpi_intr_disestablish(sc->sc_ih); 715 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 716 return; 717 } 718 719 static void 720 scx_reset(struct scx_softc *sc) 721 { 722 723 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 724 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 725 726 CSR_WRITE(sc, DESCENG_SRST, 1); 727 CSR_WRITE(sc, DESCENG_INIT, 1); 728 mac_write(sc, GMACBMR, _BMR); 729 mac_write(sc, GMACRDLAR, _RDLAR); 730 mac_write(sc, GMACTDLAR, _TDLAR); 731 mac_write(sc, GMACAFR, _AFR); 732 } 733 734 static int 735 scx_init(struct ifnet *ifp) 736 { 737 struct scx_softc *sc = ifp->if_softc; 738 const uint8_t *ea = CLLADDR(ifp->if_sadl); 739 uint32_t csr; 740 int i; 741 742 /* Cancel pending I/O. */ 743 scx_stop(ifp, 0); 744 745 /* Reset the chip to a known state. */ 746 scx_reset(sc); 747 748 /* build sane Tx and load Rx descriptors with mbuf */ 749 for (i = 0; i < SCX_NTXDESC; i++) 750 sc->sc_txdescs[i].t0 = T0_OWN; 751 sc->sc_txdescs[SCX_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 752 for (i = 0; i < SCX_NRXDESC; i++) 753 (void)add_rxbuf(sc, i); 754 755 /* set my address in perfect match slot 0 */ 756 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 757 CSR_WRITE(sc, GMACMAL0, csr); 758 csr = (ea[5] << 8) | ea[4]; 759 CSR_WRITE(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 760 761 /* accept multicast frame or run promisc mode */ 762 scx_set_rcvfilt(sc); 763 764 (void)scx_ifmedia_upd(ifp); 765 766 /* kick to start GMAC engine */ 767 csr = mac_read(sc, GMACOMR); 768 CSR_WRITE(sc, RXINT_CLR, ~0); 769 CSR_WRITE(sc, TXINT_CLR, ~0); 770 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 771 772 ifp->if_flags |= IFF_RUNNING; 773 ifp->if_flags &= ~IFF_OACTIVE; 774 775 /* start one second timer */ 776 callout_schedule(&sc->sc_tick_ch, hz); 777 778 return 0; 779 } 780 781 static void 782 scx_stop(struct ifnet *ifp, int disable) 783 { 784 struct scx_softc *sc = ifp->if_softc; 785 786 /* Stop the one second clock. */ 787 callout_stop(&sc->sc_tick_ch); 788 789 /* Down the MII. */ 790 mii_down(&sc->sc_mii); 791 792 /* Mark the interface down and cancel the watchdog timer. */ 793 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 794 ifp->if_timer = 0; 795 } 796 797 static void 798 scx_watchdog(struct ifnet *ifp) 799 { 800 struct scx_softc *sc = ifp->if_softc; 801 802 /* 803 * Since we're not interrupting every packet, sweep 804 * up before we report an error. 805 */ 806 txreap(sc); 807 808 if (sc->sc_txfree != SCX_NTXDESC) { 809 aprint_error_dev(sc->sc_dev, 810 "device timeout (txfree %d txsfree %d txnext %d)\n", 811 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 812 if_statinc(ifp, if_oerrors); 813 814 /* Reset the interface. */ 815 scx_init(ifp); 816 } 817 818 scx_start(ifp); 819 } 820 821 static int 822 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 823 { 824 struct scx_softc *sc = ifp->if_softc; 825 struct ifreq *ifr = (struct ifreq *)data; 826 struct ifmedia *ifm; 827 int s, error; 828 829 s = splnet(); 830 831 switch (cmd) { 832 case SIOCSIFMEDIA: 833 /* Flow control requires full-duplex mode. */ 834 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 835 (ifr->ifr_media & IFM_FDX) == 0) 836 ifr->ifr_media &= ~IFM_ETH_FMASK; 837 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 838 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 839 /* We can do both TXPAUSE and RXPAUSE. */ 840 ifr->ifr_media |= 841 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 842 } 843 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 844 } 845 ifm = &sc->sc_mii.mii_media; 846 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 847 break; 848 default: 849 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 850 break; 851 852 error = 0; 853 854 if (cmd == SIOCSIFCAP) 855 error = (*ifp->if_init)(ifp); 856 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 857 ; 858 else if (ifp->if_flags & IFF_RUNNING) { 859 /* 860 * Multicast list has changed; set the hardware filter 861 * accordingly. 862 */ 863 scx_set_rcvfilt(sc); 864 } 865 break; 866 } 867 868 splx(s); 869 return error; 870 } 871 872 static void 873 scx_set_rcvfilt(struct scx_softc *sc) 874 { 875 struct ethercom * const ec = &sc->sc_ethercom; 876 struct ifnet * const ifp = &ec->ec_if; 877 struct ether_multistep step; 878 struct ether_multi *enm; 879 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 880 uint32_t csr, crc; 881 int i; 882 883 csr = CSR_READ(sc, GMACAFR); 884 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 885 CSR_WRITE(sc, GMACAFR, csr); 886 887 ETHER_LOCK(ec); 888 if (ifp->if_flags & IFF_PROMISC) { 889 ec->ec_flags |= ETHER_F_ALLMULTI; 890 ETHER_UNLOCK(ec); 891 goto update; 892 } 893 ec->ec_flags &= ~ETHER_F_ALLMULTI; 894 895 /* clear 15 entry supplimental perfect match filter */ 896 for (i = 1; i < 16; i++) 897 CSR_WRITE(sc, GMACMAH(i), 0); 898 /* build 256 bit multicast hash filter */ 899 memset(mchash, 0, sizeof(mchash)); 900 crc = 0; 901 902 ETHER_FIRST_MULTI(step, ec, enm); 903 i = 1; /* slot 0 is occupied */ 904 while (enm != NULL) { 905 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 906 /* 907 * We must listen to a range of multicast addresses. 908 * For now, just accept all multicasts, rather than 909 * trying to set only those filter bits needed to match 910 * the range. (At this time, the only use of address 911 * ranges is for IP multicast routing, for which the 912 * range is big enough to require all bits set.) 913 */ 914 ec->ec_flags |= ETHER_F_ALLMULTI; 915 ETHER_UNLOCK(ec); 916 goto update; 917 } 918 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 919 if (i < 16) { 920 /* use 31 entry perfect match filter */ 921 uint32_t addr; 922 uint8_t *ep = enm->enm_addrlo; 923 addr = (ep[3] << 24) | (ep[2] << 16) 924 | (ep[1] << 8) | ep[0]; 925 CSR_WRITE(sc, GMACMAL(i), addr); 926 addr = (ep[5] << 8) | ep[4]; 927 CSR_WRITE(sc, GMACMAH(i), addr | 1U<<31); 928 } else { 929 /* use hash table when too many */ 930 /* bit_reserve_32(~crc) !? */ 931 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 932 /* 3(31:29) 5(28:24) bit sampling */ 933 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 934 } 935 ETHER_NEXT_MULTI(step, enm); 936 i++; 937 } 938 ETHER_UNLOCK(ec); 939 940 if (crc) 941 csr |= AFR_MHTE; 942 for (i = 0; i < 8; i++) 943 CSR_WRITE(sc, GMACMHT0 + i * 4, mchash[i]); 944 CSR_WRITE(sc, GMACAFR, csr); 945 return; 946 947 update: 948 /* With PM or AM, MHTE/MTL/MTH are never consulted. really? */ 949 if (ifp->if_flags & IFF_PROMISC) 950 csr |= AFR_PM; /* run promisc. mode */ 951 else 952 csr |= AFR_AM; /* accept all multicast */ 953 CSR_WRITE(sc, GMACAFR, csr); 954 return; 955 } 956 957 static int 958 scx_ifmedia_upd(struct ifnet *ifp) 959 { 960 struct scx_softc *sc = ifp->if_softc; 961 struct ifmedia *ifm = &sc->sc_mii.mii_media; 962 963 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 964 ; /* restart AN */ 965 ; /* enable AN */ 966 ; /* advertise flow control pause */ 967 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 968 } else { 969 #if 1 970 uint32_t mcr = mac_read(sc, GMACMCR); 971 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 972 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 973 else { 974 mcr |= MCR_USEMII; /* RMII/MII */ 975 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX) 976 mcr |= MCR_SPD100; 977 } 978 if (ifm->ifm_cur->ifm_media & IFM_FDX) 979 mcr |= MCR_USEFDX; 980 mcr |= MCR_CST | MCR_JE; 981 mcr |= MCR_IBN; 982 mac_write(sc, GMACMCR, mcr); 983 #endif 984 } 985 return 0; 986 } 987 988 static void 989 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 990 { 991 struct scx_softc *sc = ifp->if_softc; 992 struct mii_data *mii = &sc->sc_mii; 993 994 mii_pollstat(mii); 995 ifmr->ifm_status = mii->mii_media_status; 996 ifmr->ifm_active = sc->sc_flowflags | 997 (mii->mii_media_active & ~IFM_ETH_FMASK); 998 } 999 1000 void 1001 mii_statchg(struct ifnet *ifp) 1002 { 1003 struct scx_softc *sc = ifp->if_softc; 1004 struct mii_data *mii = &sc->sc_mii; 1005 uint32_t fcr; 1006 1007 /* Get flow control negotiation result. */ 1008 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1009 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1010 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1011 1012 /* Adjust PAUSE flow control. */ 1013 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1014 if (mii->mii_media_active & IFM_FDX) { 1015 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1016 fcr |= FCR_TFE; 1017 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1018 fcr |= FCR_RFE; 1019 } 1020 mac_write(sc, GMACFCR, fcr); 1021 1022 printf("%ctxfe, %crxfe\n", 1023 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1024 } 1025 1026 static void 1027 phy_tick(void *arg) 1028 { 1029 struct scx_softc *sc = arg; 1030 struct mii_data *mii = &sc->sc_mii; 1031 int s; 1032 1033 s = splnet(); 1034 mii_tick(mii); 1035 splx(s); 1036 1037 callout_schedule(&sc->sc_tick_ch, hz); 1038 } 1039 1040 static int 1041 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1042 { 1043 struct scx_softc *sc = device_private(self); 1044 uint32_t gar; 1045 int error; 1046 1047 gar = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_gar; 1048 mac_write(sc, GMACGAR, gar | GAR_BUSY); 1049 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1050 if (error) 1051 return error; 1052 *val = mac_read(sc, GMACGDR); 1053 return 0; 1054 } 1055 1056 static int 1057 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1058 { 1059 struct scx_softc *sc = device_private(self); 1060 uint32_t gar; 1061 uint16_t dummy; 1062 int error; 1063 1064 gar = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_gar; 1065 mac_write(sc, GMACGDR, val); 1066 mac_write(sc, GMACGAR, gar | GAR_IOWR | GAR_BUSY); 1067 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1068 if (error) 1069 return error; 1070 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1071 return 0; 1072 } 1073 1074 static void 1075 scx_start(struct ifnet *ifp) 1076 { 1077 struct scx_softc *sc = ifp->if_softc; 1078 struct mbuf *m0, *m; 1079 struct scx_txsoft *txs; 1080 bus_dmamap_t dmamap; 1081 int error, nexttx, lasttx, ofree, seg; 1082 uint32_t tdes0; 1083 1084 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1085 return; 1086 1087 /* Remember the previous number of free descriptors. */ 1088 ofree = sc->sc_txfree; 1089 1090 /* 1091 * Loop through the send queue, setting up transmit descriptors 1092 * until we drain the queue, or use up all available transmit 1093 * descriptors. 1094 */ 1095 for (;;) { 1096 IFQ_POLL(&ifp->if_snd, m0); 1097 if (m0 == NULL) 1098 break; 1099 1100 if (sc->sc_txsfree < SCX_TXQUEUE_GC) { 1101 txreap(sc); 1102 if (sc->sc_txsfree == 0) 1103 break; 1104 } 1105 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1106 dmamap = txs->txs_dmamap; 1107 1108 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1109 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1110 if (error) { 1111 if (error == EFBIG) { 1112 aprint_error_dev(sc->sc_dev, 1113 "Tx packet consumes too many " 1114 "DMA segments, dropping...\n"); 1115 IFQ_DEQUEUE(&ifp->if_snd, m0); 1116 m_freem(m0); 1117 continue; 1118 } 1119 /* Short on resources, just stop for now. */ 1120 break; 1121 } 1122 1123 if (dmamap->dm_nsegs > sc->sc_txfree) { 1124 /* 1125 * Not enough free descriptors to transmit this 1126 * packet. We haven't committed anything yet, 1127 * so just unload the DMA map, put the packet 1128 * back on the queue, and punt. Notify the upper 1129 * layer that there are not more slots left. 1130 */ 1131 ifp->if_flags |= IFF_OACTIVE; 1132 bus_dmamap_unload(sc->sc_dmat, dmamap); 1133 break; 1134 } 1135 1136 IFQ_DEQUEUE(&ifp->if_snd, m0); 1137 1138 /* 1139 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1140 */ 1141 1142 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1143 BUS_DMASYNC_PREWRITE); 1144 1145 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1146 lasttx = -1; 1147 for (nexttx = sc->sc_txnext, seg = 0; 1148 seg < dmamap->dm_nsegs; 1149 seg++, nexttx = SCX_NEXTTX(nexttx)) { 1150 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1151 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1152 /* 1153 * If this is the first descriptor we're 1154 * enqueueing, don't set the OWN bit just 1155 * yet. That could cause a race condition. 1156 * We'll do it below. 1157 */ 1158 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1159 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1160 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1161 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1162 (15 << T0_TRID) | T0_PT | 1163 sc->sc_t0coso | T0_TRS; 1164 tdes0 = T0_OWN; /* 2nd and other segments */ 1165 lasttx = nexttx; 1166 } 1167 /* 1168 * Outgoing NFS mbuf must be unloaded when Tx completed. 1169 * Without T1_IC NFS mbuf is left unack'ed for excessive 1170 * time and NFS stops to proceed until scx_watchdog() 1171 * calls txreap() to reclaim the unack'ed mbuf. 1172 * It's painful to traverse every mbuf chain to determine 1173 * whether someone is waiting for Tx completion. 1174 */ 1175 m = m0; 1176 do { 1177 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1178 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1179 break; 1180 } 1181 } while ((m = m->m_next) != NULL); 1182 1183 /* Write deferred 1st segment T0_OWN at the final stage */ 1184 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1185 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1186 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1187 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1188 1189 /* Tell DMA start transmit */ 1190 /* CSR_WRITE(sc, MDTSC, 1); */ 1191 1192 txs->txs_mbuf = m0; 1193 txs->txs_firstdesc = sc->sc_txnext; 1194 txs->txs_lastdesc = lasttx; 1195 txs->txs_ndesc = dmamap->dm_nsegs; 1196 1197 sc->sc_txfree -= txs->txs_ndesc; 1198 sc->sc_txnext = nexttx; 1199 sc->sc_txsfree--; 1200 sc->sc_txsnext = SCX_NEXTTXS(sc->sc_txsnext); 1201 /* 1202 * Pass the packet to any BPF listeners. 1203 */ 1204 bpf_mtap(ifp, m0, BPF_D_OUT); 1205 } 1206 1207 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1208 /* No more slots left; notify upper layer. */ 1209 ifp->if_flags |= IFF_OACTIVE; 1210 } 1211 if (sc->sc_txfree != ofree) { 1212 /* Set a watchdog timer in case the chip flakes out. */ 1213 ifp->if_timer = 5; 1214 } 1215 } 1216 1217 static int 1218 scx_intr(void *arg) 1219 { 1220 struct scx_softc *sc = arg; 1221 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1222 1223 (void)ifp; 1224 rxintr(sc); 1225 txreap(sc); 1226 return 1; 1227 } 1228 1229 static void 1230 txreap(struct scx_softc *sc) 1231 { 1232 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1233 struct scx_txsoft *txs; 1234 uint32_t txstat; 1235 int i; 1236 1237 ifp->if_flags &= ~IFF_OACTIVE; 1238 1239 for (i = sc->sc_txsdirty; sc->sc_txsfree != SCX_TXQUEUELEN; 1240 i = SCX_NEXTTXS(i), sc->sc_txsfree++) { 1241 txs = &sc->sc_txsoft[i]; 1242 1243 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1244 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1245 1246 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1247 if (txstat & T0_OWN) /* desc is still in use */ 1248 break; 1249 1250 /* There is no way to tell transmission status per frame */ 1251 1252 if_statinc(ifp, if_opackets); 1253 1254 sc->sc_txfree += txs->txs_ndesc; 1255 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1256 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1257 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1258 m_freem(txs->txs_mbuf); 1259 txs->txs_mbuf = NULL; 1260 } 1261 sc->sc_txsdirty = i; 1262 if (sc->sc_txsfree == SCX_TXQUEUELEN) 1263 ifp->if_timer = 0; 1264 } 1265 1266 static void 1267 rxintr(struct scx_softc *sc) 1268 { 1269 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1270 struct scx_rxsoft *rxs; 1271 struct mbuf *m; 1272 uint32_t rxstat; 1273 int i, len; 1274 1275 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = SCX_NEXTRX(i)) { 1276 rxs = &sc->sc_rxsoft[i]; 1277 1278 SCX_CDRXSYNC(sc, i, 1279 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1280 1281 rxstat = sc->sc_rxdescs[i].r0; 1282 if (rxstat & R0_OWN) /* desc is left empty */ 1283 break; 1284 1285 /* R0_FS | R0_LS must have been marked for this desc */ 1286 1287 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1288 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1289 1290 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1291 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1292 m = rxs->rxs_mbuf; 1293 1294 if (add_rxbuf(sc, i) != 0) { 1295 if_statinc(ifp, if_ierrors); 1296 SCX_INIT_RXDESC(sc, i); 1297 bus_dmamap_sync(sc->sc_dmat, 1298 rxs->rxs_dmamap, 0, 1299 rxs->rxs_dmamap->dm_mapsize, 1300 BUS_DMASYNC_PREREAD); 1301 continue; 1302 } 1303 1304 m_set_rcvif(m, ifp); 1305 m->m_pkthdr.len = m->m_len = len; 1306 1307 if (rxstat & R0_CSUM) { 1308 uint32_t csum = M_CSUM_IPv4; 1309 if (rxstat & R0_CERR) 1310 csum |= M_CSUM_IPv4_BAD; 1311 m->m_pkthdr.csum_flags |= csum; 1312 } 1313 if_percpuq_enqueue(ifp->if_percpuq, m); 1314 } 1315 sc->sc_rxptr = i; 1316 } 1317 1318 static int 1319 add_rxbuf(struct scx_softc *sc, int i) 1320 { 1321 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1322 struct mbuf *m; 1323 int error; 1324 1325 MGETHDR(m, M_DONTWAIT, MT_DATA); 1326 if (m == NULL) 1327 return ENOBUFS; 1328 1329 MCLGET(m, M_DONTWAIT); 1330 if ((m->m_flags & M_EXT) == 0) { 1331 m_freem(m); 1332 return ENOBUFS; 1333 } 1334 1335 if (rxs->rxs_mbuf != NULL) 1336 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1337 1338 rxs->rxs_mbuf = m; 1339 1340 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1341 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1342 if (error) { 1343 aprint_error_dev(sc->sc_dev, 1344 "can't load rx DMA map %d, error = %d\n", i, error); 1345 panic("add_rxbuf"); 1346 } 1347 1348 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1349 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1350 SCX_INIT_RXDESC(sc, i); 1351 1352 return 0; 1353 } 1354 1355 static int 1356 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1357 { 1358 int val, loop; 1359 1360 val = CSR_READ(sc, reg); 1361 if ((val & exist) == 0) 1362 return 0; 1363 loop = 3000; 1364 do { 1365 DELAY(10); 1366 val = CSR_READ(sc, reg); 1367 } while (--loop > 0 && (val & exist) != 0); 1368 return (loop > 0) ? 0 : ETIMEDOUT; 1369 } 1370 1371 static int 1372 mac_read(struct scx_softc *sc, int reg) 1373 { 1374 1375 CSR_WRITE(sc, MACCMD, reg); 1376 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1377 return CSR_READ(sc, MACDATA); 1378 } 1379 1380 static void 1381 mac_write(struct scx_softc *sc, int reg, int val) 1382 { 1383 1384 CSR_WRITE(sc, MACDATA, val); 1385 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1386 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1387 } 1388 1389 static int 1390 get_garclk(uint32_t freq) 1391 { 1392 int i; 1393 1394 for (i = 0; garclk[i].freq != 0; i++) { 1395 if (freq < garclk[i].freq) 1396 return garclk[i].bit; 1397 } 1398 return garclk[i - 1].bit; 1399 } 1400 1401 static void 1402 loaducode(struct scx_softc *sc) 1403 { 1404 uint32_t up, lo, sz; 1405 uint64_t addr; 1406 1407 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1408 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1409 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1410 addr = ((uint64_t)up << 32) | lo; 1411 aprint_normal_dev(sc->sc_dev, "H2M ucode %u\n", sz); 1412 injectucode(sc, DMACH2M, addr, sz); 1413 printf("H->M ucode %08x-%08x\n", up, lo); 1414 1415 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1416 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1417 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1418 addr = ((uint64_t)up << 32) | lo; 1419 aprint_normal_dev(sc->sc_dev, "M2H ucode %u\n", sz); 1420 injectucode(sc, DMACM2H, addr, sz); 1421 printf("M->H ucode %08x-%08x\n", up, lo); 1422 1423 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1424 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1425 aprint_normal_dev(sc->sc_dev, "PKT ucode %u\n", sz); 1426 injectucode(sc, DMACH2M, (uint64_t)lo, sz); 1427 printf("PKT ucode %08x-%08x\n", 0, lo); 1428 } 1429 1430 static void 1431 injectucode(struct scx_softc *sc, int port, uint64_t addr, uint32_t size) 1432 { 1433 uint32_t ucode; 1434 bus_size_t off; 1435 int i; 1436 1437 /* XXX addr is ucode paddr_t itself XXX */ 1438 for (i = 0; i < size; i++) { 1439 off = addr + i * 4; 1440 off -= (bus_addr_t)sc->sc_eesh; /* XXX */ 1441 ucode = bus_space_read_4(sc->sc_st, sc->sc_eesh, off); 1442 CSR_WRITE(sc, port, ucode); 1443 } 1444 } 1445
Indexes created Fri Sep 26 20:09:58 GMT 2025