if_scx.c revision 1.12
1 /* $NetBSD: if_scx.c,v 1.12 2020/03/24 13:44:21 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 16 or even 128. 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~16 are for supplimental MAC addresses. Independently enabled for 47 * use. Good to catch multicast. Byte-wise selective match available. 48 * Use the mask to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - 16~128 might be exact match without byte-mask. 50 * - The size of multicast hash filter store is unknown. Might be 256 bit. 51 * - Socionext/Linaro "NetSec" code makes many cut shorts. Some constants 52 * are left unexplained. The values should be handled via external 53 * controls like FDT descriptions. Fortunately, Intel/Altera CycloneV PDFs 54 * describe every detail of "such the instance of" DW EMAC IP and 55 * most of them are likely applicable to SC2A11 GbE. 56 */ 57 58 #include <sys/cdefs.h> 59 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.12 2020/03/24 13:44:21 nisimura Exp $"); 60 61 #include <sys/param.h> 62 #include <sys/bus.h> 63 #include <sys/intr.h> 64 #include <sys/device.h> 65 #include <sys/callout.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/errno.h> 69 #include <sys/rndsource.h> 70 #include <sys/kernel.h> 71 #include <sys/systm.h> 72 73 #include <net/if.h> 74 #include <net/if_media.h> 75 #include <net/if_dl.h> 76 #include <net/if_ether.h> 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <net/bpf.h> 80 81 #include <dev/fdt/fdtvar.h> 82 #include <dev/acpi/acpireg.h> 83 #include <dev/acpi/acpivar.h> 84 #include <dev/acpi/acpi_intr.h> 85 86 #define SWRESET 0x104 87 #define COMINIT 0x120 88 #define INTRST 0x200 89 #define IRQ_RX (1U<<1) 90 #define IRQ_TX (1U<<0) 91 #define INTREN 0x204 92 #define INTR_SET 0x234 93 #define INTR_CLR 0x238 94 #define TXINTST 0x400 95 #define TXINTEN 0x404 96 #define TXINT_SET 0x428 97 #define TXINT_CLR 0x42c 98 #define TXI_NTOWNR (1U<<17) 99 #define TXI_TR_ERR (1U<<16) 100 #define TXI_TXDONE (1U<<15) 101 #define TXI_TMREXP (1U<<14) 102 #define RXINTST 0x440 103 #define RXINTEN 0x444 104 #define RXINT_SET 0x468 105 #define RXINT_CLR 0x46c 106 #define RXI_RC_ERR (1U<<16) 107 #define RXI_PKTCNT (1U<<15) 108 #define RXI_TMREXP (1U<<14) 109 #define TXTIMER 0x41c 110 #define RXTIMER 0x45c 111 #define TXCOUNT 0x410 112 #define RXCOUNT 0x454 113 #define H2MENG 0x210 /* DMAC host2media ucode port */ 114 #define M2HENG 0x21c /* DMAC media2host ucode port */ 115 #define PKTENG 0x0d0 /* packet engine ucode port */ 116 #define HWVER0 0x22c 117 #define HWVER1 0x230 118 119 #define MACSTAT 0x1024 /* gmac status */ 120 #define MACDATA 0x11c0 /* gmac rd/wr data */ 121 #define MACCMD 0x11c4 /* gmac operation */ 122 #define CMD_IOWR (1U<<28) /* write op */ 123 #define CMD_BUSY (1U<<31) /* busy bit */ 124 #define DESCENG_INIT 0x11fc 125 #define DESCENG_SRST 0x1204 126 127 #define GMACMCR 0x0000 /* MAC configuration */ 128 #define MCR_IBN (1U<<30) /* */ 129 #define MCR_CST (1U<<25) /* strip CRC */ 130 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 131 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 132 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 133 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 134 #define MCR_USEFDX (1U<<11) /* force full duplex */ 135 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 136 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 137 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 138 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 139 #define _MCR_FDX 0x0000280c /* XXX TBD */ 140 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 141 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 142 #define AFR_RA (1U<<31) /* receive block all on */ 143 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 144 #define AFR_SAF (1U<<9) /* source address filter */ 145 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 146 #define AFR_PCF (3U<<6) /* */ 147 #define AFR_RB (1U<<5) /* reject broadcast frame */ 148 #define AFR_AM (1U<<4) /* accept all multicast frame */ 149 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 150 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 151 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 152 #define AFR_PM (1U<<0) /* run promisc mode */ 153 #define _AFR 0x80000001 /* XXX TBD */ 154 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 155 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 156 #define GMACGAR 0x0010 /* MDIO operation */ 157 #define GAR_PHY (11) /* mii phy 15:11 */ 158 #define GAR_REG (6) /* mii reg 10:6 */ 159 #define GAR_CTL (2) /* control 5:2 */ 160 #define GAR_IOWR (1U<<1) /* MDIO write op */ 161 #define GAR_BUSY (1U) /* busy bit */ 162 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 163 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 164 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 165 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 166 #define GMACVTAG 0x001c /* VLAN tag control */ 167 #define GMACIMPL 0x0020 /* implementation number XXXX.YYYY */ 168 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 169 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 170 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */ 171 #define GMACMAL(i) ((i)*8+0x44) 172 #define GMACMDSR 0x00d8 /* GMII/RGMII/MII command/status */ 173 #define GMACMHT0 0x0500 /* multicast hash table 0 - 7 */ 174 #define GMACMHT(i) ((i)*4+0x500) 175 #define GMACVHT 0x0588 /* VLAN tag hash */ 176 #define GMACAMAH(i) ((i)*8+0x800) /* supplimental MAC addr 16-127 */ 177 #define GMACAMAL(i) ((i)*8+0x804) 178 #define GMACEVCNT(i) ((i)*4+0x114) /* event counter 0x114~284 */ 179 180 #define GMACBMR 0x1000 /* DMA bus mode control 181 * 24 4PBL 182 * 22:17 RPBL 183 * 16 fix burst 184 * 15:14 priority between Rx and Tx 185 * 3 rxtx ratio 41 186 * 2 rxtx ratio 31 187 * 1 rxtx ratio 21 188 * 0 rxtx ratio 11 189 * 13:8 PBL possible DMA burst len 190 * 0 reset op. self clear 191 */ 192 #define _BMR 0x00412080 /* XXX TBD */ 193 #define _BMR0 0x00020181 /* XXX TBD */ 194 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 195 #define GMACTDS 0x1004 /* write any to resume tdes */ 196 #define GMACRDS 0x1008 /* write any to resume rdes */ 197 #define GMACRDLAR 0x100c /* rdes base address 32bit paddr */ 198 #define _RDLAR 0x18000 /* XXX TBD system SRAM with CC ? */ 199 #define GMACTDLAR 0x1010 /* tdes base address 32bit paddr */ 200 #define _TDLAR 0x1c000 /* XXX TBD system SRAM with CC ? */ 201 #define GMACOMR 0x1018 /* DMA operation */ 202 #define OMR_TXE (1U<<13) /* start Tx DMA engine, 0 to stop */ 203 #define OMR_RXE (1U<<1) /* start Rx DMA engine, 0 to stop */ 204 205 static int get_mdioclk(uint32_t); 206 207 /* descriptor format definition */ 208 struct tdes { 209 uint32_t t0, t1, t2, t3; 210 }; 211 212 struct rdes { 213 uint32_t r0, r1, r2, r3; 214 }; 215 216 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 217 #define T0_EOD (1U<<30) /* end of descriptor array */ 218 #define T0_DRID (24) /* 29:24 D-RID */ 219 #define T0_PT (1U<<21) /* 23:21 PT */ 220 #define T0_TRID (16) /* 20:16 T-RID */ 221 #define T0_FS (1U<<9) /* first segment of frame */ 222 #define T0_LS (1U<<8) /* last segment of frame */ 223 #define T0_CSUM (1U<<7) /* enable check sum offload */ 224 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 225 #define T0_TRS (1U<<4) /* 5:4 TRS */ 226 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 227 /* T1 segment address 63:32 */ 228 /* T2 segment address 31:0 */ 229 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 230 #define R0_OWN (1U<<31) /* desc is empty */ 231 #define R0_EOD (1U<<30) /* end of descriptor array */ 232 #define R0_SRID (24) /* 29:24 S-RID */ 233 #define R0_FR (1U<<23) /* FR */ 234 #define R0_ER (1U<<21) /* Rx error indication */ 235 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 236 #define R0_TDRID (14) /* 15:14 TD-RID */ 237 #define R0_FS (1U<<9) /* first segment of frame */ 238 #define R0_LS (1U<<8) /* last segment of frame */ 239 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 240 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 241 /* R1 frame address 63:32 */ 242 /* R2 frame address 31:0 */ 243 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 244 245 #define MD_NTXSEGS 16 /* fixed */ 246 #define MD_TXQUEUELEN 16 /* tunable */ 247 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 248 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 249 #define MD_NTXDESC (MD_TXQUEUELEN * MD_NTXSEGS) 250 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 251 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 252 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 253 254 #define MD_NRXDESC 64 /* tunable */ 255 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 256 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 257 258 #define SCX_INIT_RXDESC(sc, x) \ 259 do { \ 260 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 261 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 262 struct mbuf *__m = __rxs->rxs_mbuf; \ 263 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 264 __m->m_data = __m->m_ext.ext_buf; \ 265 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 266 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 267 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 268 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 269 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 270 } while (/*CONSTCOND*/0) 271 272 struct control_data { 273 struct tdes cd_txdescs[MD_NTXDESC]; 274 struct rdes cd_rxdescs[MD_NRXDESC]; 275 }; 276 #define SCX_CDOFF(x) offsetof(struct control_data, x) 277 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 278 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 279 280 struct scx_txsoft { 281 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 282 bus_dmamap_t txs_dmamap; /* our DMA map */ 283 int txs_firstdesc; /* first descriptor in packet */ 284 int txs_lastdesc; /* last descriptor in packet */ 285 int txs_ndesc; /* # of descriptors used */ 286 }; 287 288 struct scx_rxsoft { 289 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 290 bus_dmamap_t rxs_dmamap; /* our DMA map */ 291 }; 292 293 struct scx_softc { 294 device_t sc_dev; /* generic device information */ 295 bus_space_tag_t sc_st; /* bus space tag */ 296 bus_space_handle_t sc_sh; /* bus space handle */ 297 bus_size_t sc_sz; /* csr map size */ 298 bus_space_handle_t sc_eesh; /* eeprom section handle */ 299 bus_size_t sc_eesz; /* eeprom map size */ 300 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 301 struct ethercom sc_ethercom; /* Ethernet common data */ 302 struct mii_data sc_mii; /* MII */ 303 callout_t sc_tick_ch; /* PHY monitor callout */ 304 bus_dma_segment_t sc_seg; /* descriptor store seg */ 305 int sc_nseg; /* descriptor store nseg */ 306 void *sc_ih; /* interrupt cookie */ 307 int sc_phy_id; /* PHY address */ 308 int sc_flowflags; /* 802.3x PAUSE flow control */ 309 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 310 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 311 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 312 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 313 int sc_phandle; /* fdt phandle */ 314 315 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 316 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 317 318 struct control_data *sc_control_data; 319 #define sc_txdescs sc_control_data->cd_txdescs 320 #define sc_rxdescs sc_control_data->cd_rxdescs 321 322 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 323 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 324 int sc_txfree; /* number of free Tx descriptors */ 325 int sc_txnext; /* next ready Tx descriptor */ 326 int sc_txsfree; /* number of free Tx jobs */ 327 int sc_txsnext; /* next ready Tx job */ 328 int sc_txsdirty; /* dirty Tx jobs */ 329 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 330 331 krndsource_t rnd_source; /* random source */ 332 }; 333 334 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 335 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 336 337 #define SCX_CDTXSYNC(sc, x, n, ops) \ 338 do { \ 339 int __x, __n; \ 340 \ 341 __x = (x); \ 342 __n = (n); \ 343 \ 344 /* If it will wrap around, sync to the end of the ring. */ \ 345 if ((__x + __n) > MD_NTXDESC) { \ 346 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 347 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 348 (MD_NTXDESC - __x), (ops)); \ 349 __n -= (MD_NTXDESC - __x); \ 350 __x = 0; \ 351 } \ 352 \ 353 /* Now sync whatever is left. */ \ 354 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 355 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 356 } while (/*CONSTCOND*/0) 357 358 #define SCX_CDRXSYNC(sc, x, ops) \ 359 do { \ 360 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 361 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 362 } while (/*CONSTCOND*/0) 363 364 static int scx_fdt_match(device_t, cfdata_t, void *); 365 static void scx_fdt_attach(device_t, device_t, void *); 366 static int scx_acpi_match(device_t, cfdata_t, void *); 367 static void scx_acpi_attach(device_t, device_t, void *); 368 369 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 370 scx_fdt_match, scx_fdt_attach, NULL, NULL); 371 372 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 373 scx_acpi_match, scx_acpi_attach, NULL, NULL); 374 375 static void scx_attach_i(struct scx_softc *); 376 static void scx_reset(struct scx_softc *); 377 static int scx_init(struct ifnet *); 378 static void scx_start(struct ifnet *); 379 static void scx_stop(struct ifnet *, int); 380 static void scx_watchdog(struct ifnet *); 381 static int scx_ioctl(struct ifnet *, u_long, void *); 382 static void scx_set_rcvfilt(struct scx_softc *); 383 static int scx_ifmedia_upd(struct ifnet *); 384 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 385 static void mii_statchg(struct ifnet *); 386 static void phy_tick(void *); 387 static int mii_readreg(device_t, int, int, uint16_t *); 388 static int mii_writereg(device_t, int, int, uint16_t); 389 static int scx_intr(void *); 390 static void txreap(struct scx_softc *); 391 static void rxintr(struct scx_softc *); 392 static int add_rxbuf(struct scx_softc *, int); 393 static int spin_waitfor(struct scx_softc *, int, int); 394 static int mac_read(struct scx_softc *, int); 395 static void mac_write(struct scx_softc *, int, int); 396 static void loaducode(struct scx_softc *); 397 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 398 399 #define CSR_READ(sc,off) \ 400 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 401 #define CSR_WRITE(sc,off,val) \ 402 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 403 #define EE_READ(sc,off) \ 404 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 405 406 static int 407 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 408 { 409 static const char * compatible[] = { 410 "socionext,synquacer-netsec", 411 NULL 412 }; 413 struct fdt_attach_args * const faa = aux; 414 415 return of_match_compatible(faa->faa_phandle, compatible); 416 } 417 418 static void 419 scx_fdt_attach(device_t parent, device_t self, void *aux) 420 { 421 struct scx_softc * const sc = device_private(self); 422 struct fdt_attach_args * const faa = aux; 423 const int phandle = faa->faa_phandle; 424 bus_space_tag_t bst = faa->faa_bst; 425 bus_space_handle_t bsh; 426 bus_space_handle_t eebsh; 427 bus_addr_t addr[2]; 428 bus_size_t size[2]; 429 char intrstr[128]; 430 const char *phy_mode; 431 432 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 433 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 434 aprint_error(": unable to map device csr\n"); 435 return; 436 } 437 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 438 aprint_error(": failed to decode interrupt\n"); 439 goto fail; 440 } 441 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 442 NOT_MP_SAFE, scx_intr, sc); 443 if (sc->sc_ih == NULL) { 444 aprint_error_dev(self, "couldn't establish interrupt\n"); 445 goto fail; 446 } 447 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 448 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 449 aprint_error(": unable to map device eeprom\n"); 450 goto fail; 451 } 452 453 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 454 if (phy_mode == NULL) { 455 aprint_error(": missing 'phy-mode' property\n"); 456 phy_mode = "rgmii"; 457 } 458 459 aprint_naive("\n"); 460 aprint_normal(": Gigabit Ethernet Controller\n"); 461 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 462 463 sc->sc_dev = self; 464 sc->sc_st = bst; 465 sc->sc_sh = bsh; 466 sc->sc_sz = size[0]; 467 sc->sc_eesh = eebsh; 468 sc->sc_eesz = size[1]; 469 sc->sc_dmat = faa->faa_dmat; 470 sc->sc_phandle = phandle; 471 sc->sc_100mii = (strcmp(phy_mode, "rgmii") != 0); 472 473 scx_attach_i(sc); 474 return; 475 fail: 476 if (sc->sc_eesz) 477 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 478 if (sc->sc_sz) 479 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 480 return; 481 } 482 483 static int 484 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 485 { 486 static const char * compatible[] = { 487 "SCX0001", 488 NULL 489 }; 490 struct acpi_attach_args *aa = aux; 491 492 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 493 return 0; 494 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 495 } 496 497 static void 498 scx_acpi_attach(device_t parent, device_t self, void *aux) 499 { 500 struct scx_softc * const sc = device_private(self); 501 struct acpi_attach_args * const aa = aux; 502 ACPI_HANDLE handle = aa->aa_node->ad_handle; 503 bus_space_tag_t bst = aa->aa_memt; 504 bus_space_handle_t bsh, eebsh; 505 struct acpi_resources res; 506 struct acpi_mem *mem; 507 struct acpi_irq *irq; 508 ACPI_STATUS rv; 509 510 rv = acpi_resource_parse(self, handle, "_CRS", 511 &res, &acpi_resource_parse_ops_default); 512 if (ACPI_FAILURE(rv)) 513 return; 514 acpi_resource_print(self, &res); 515 mem = acpi_res_mem(&res, 0); 516 irq = acpi_res_irq(&res, 0); 517 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 518 aprint_error(": incomplete csr resources\n"); 519 return; 520 } 521 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 522 aprint_error(": couldn't map registers\n"); 523 return; 524 } 525 sc->sc_sz = mem->ar_length; 526 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 527 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 528 if (sc->sc_ih == NULL) { 529 aprint_error_dev(self, "couldn't establish interrupt\n"); 530 goto fail; 531 } 532 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 533 if (mem == NULL || mem->ar_length == 0) { 534 aprint_error(": incomplete eeprom resources\n"); 535 goto fail; 536 } 537 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 538 aprint_error(": couldn't map registers\n"); 539 goto fail; 540 } 541 sc->sc_eesz = mem->ar_length; 542 543 aprint_naive("\n"); 544 aprint_normal(": Gigabit Ethernet Controller\n"); 545 546 sc->sc_dev = self; 547 sc->sc_st = bst; 548 sc->sc_sh = bsh; 549 sc->sc_eesh = eebsh; 550 sc->sc_dmat = aa->aa_dmat64; 551 552 /* dig _DSD to see parameters. safe to assume RGMII/spd1000 though */ 553 554 scx_attach_i(sc); 555 556 acpi_resource_cleanup(&res); 557 return; 558 fail: 559 if (sc->sc_eesz > 0) 560 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 561 if (sc->sc_sz > 0) 562 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 563 acpi_resource_cleanup(&res); 564 return; 565 } 566 567 static void 568 scx_attach_i(struct scx_softc *sc) 569 { 570 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 571 struct mii_data * const mii = &sc->sc_mii; 572 struct ifmedia * const ifm = &mii->mii_media; 573 uint32_t hwver, phyfreq; 574 uint8_t enaddr[ETHER_ADDR_LEN]; 575 bus_dma_segment_t seg; 576 uint32_t csr; 577 int i, nseg, error = 0; 578 579 hwver = CSR_READ(sc, HWVER1); 580 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 581 enaddr[0] = csr >> 24; 582 enaddr[1] = csr >> 16; 583 enaddr[2] = csr >> 8; 584 enaddr[3] = csr; 585 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 586 enaddr[4] = csr >> 24; 587 enaddr[5] = csr >> 16; 588 csr = CSR_READ(sc, GMACIMPL); 589 590 aprint_normal_dev(sc->sc_dev, "NetSec GbE (%d.%d) impl (%x.%x)\n", 591 hwver >> 16, hwver & 0xffff, csr >> 16, csr & 0xffff); 592 aprint_normal_dev(sc->sc_dev, 593 "Ethernet address %s\n", ether_sprintf(enaddr)); 594 595 phyfreq = 0; 596 sc->sc_phy_id = MII_PHY_ANY; 597 sc->sc_mdclk = get_mdioclk(phyfreq); /* 5:2 clk control */ 598 599 sc->sc_flowflags = 0; 600 601 if (sc->sc_ucodeloaded == 0) 602 loaducode(sc); 603 604 mii->mii_ifp = ifp; 605 mii->mii_readreg = mii_readreg; 606 mii->mii_writereg = mii_writereg; 607 mii->mii_statchg = mii_statchg; 608 609 sc->sc_ethercom.ec_mii = mii; 610 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 611 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 612 MII_OFFSET_ANY, MIIF_DOPAUSE); 613 if (LIST_FIRST(&mii->mii_phys) == NULL) { 614 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 615 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 616 } else 617 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 618 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 619 620 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 621 ifp->if_softc = sc; 622 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 623 ifp->if_ioctl = scx_ioctl; 624 ifp->if_start = scx_start; 625 ifp->if_watchdog = scx_watchdog; 626 ifp->if_init = scx_init; 627 ifp->if_stop = scx_stop; 628 IFQ_SET_READY(&ifp->if_snd); 629 630 if_attach(ifp); 631 if_deferred_start_init(ifp, NULL); 632 ether_ifattach(ifp, enaddr); 633 634 callout_init(&sc->sc_tick_ch, 0); 635 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 636 637 /* 638 * Allocate the control data structures, and create and load the 639 * DMA map for it. 640 */ 641 error = bus_dmamem_alloc(sc->sc_dmat, 642 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 643 if (error != 0) { 644 aprint_error_dev(sc->sc_dev, 645 "unable to allocate control data, error = %d\n", error); 646 goto fail_0; 647 } 648 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 649 sizeof(struct control_data), (void **)&sc->sc_control_data, 650 BUS_DMA_COHERENT); 651 if (error != 0) { 652 aprint_error_dev(sc->sc_dev, 653 "unable to map control data, error = %d\n", error); 654 goto fail_1; 655 } 656 error = bus_dmamap_create(sc->sc_dmat, 657 sizeof(struct control_data), 1, 658 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 659 if (error != 0) { 660 aprint_error_dev(sc->sc_dev, 661 "unable to create control data DMA map, " 662 "error = %d\n", error); 663 goto fail_2; 664 } 665 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 666 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 667 if (error != 0) { 668 aprint_error_dev(sc->sc_dev, 669 "unable to load control data DMA map, error = %d\n", 670 error); 671 goto fail_3; 672 } 673 for (i = 0; i < MD_TXQUEUELEN; i++) { 674 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 675 MD_NTXSEGS, MCLBYTES, 0, 0, 676 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 677 aprint_error_dev(sc->sc_dev, 678 "unable to create tx DMA map %d, error = %d\n", 679 i, error); 680 goto fail_4; 681 } 682 } 683 for (i = 0; i < MD_NRXDESC; i++) { 684 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 685 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 686 aprint_error_dev(sc->sc_dev, 687 "unable to create rx DMA map %d, error = %d\n", 688 i, error); 689 goto fail_5; 690 } 691 sc->sc_rxsoft[i].rxs_mbuf = NULL; 692 } 693 sc->sc_seg = seg; 694 sc->sc_nseg = nseg; 695 printf("bus_dmaseg ds_addr %08lx, ds_len %08lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 696 697 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 698 pmf_class_network_register(sc->sc_dev, ifp); 699 else 700 aprint_error_dev(sc->sc_dev, 701 "couldn't establish power handler\n"); 702 703 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 704 RND_TYPE_NET, RND_FLAG_DEFAULT); 705 706 return; 707 708 fail_5: 709 for (i = 0; i < MD_NRXDESC; i++) { 710 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 711 bus_dmamap_destroy(sc->sc_dmat, 712 sc->sc_rxsoft[i].rxs_dmamap); 713 } 714 fail_4: 715 for (i = 0; i < MD_TXQUEUELEN; i++) { 716 if (sc->sc_txsoft[i].txs_dmamap != NULL) 717 bus_dmamap_destroy(sc->sc_dmat, 718 sc->sc_txsoft[i].txs_dmamap); 719 } 720 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 721 fail_3: 722 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 723 fail_2: 724 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 725 sizeof(struct control_data)); 726 fail_1: 727 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 728 fail_0: 729 if (sc->sc_phandle) 730 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 731 else 732 acpi_intr_disestablish(sc->sc_ih); 733 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 734 return; 735 } 736 737 static void 738 scx_reset(struct scx_softc *sc) 739 { 740 741 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 742 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 743 744 CSR_WRITE(sc, DESCENG_SRST, 1); 745 CSR_WRITE(sc, DESCENG_INIT, 1); 746 mac_write(sc, GMACBMR, _BMR); 747 mac_write(sc, GMACRDLAR, _RDLAR); 748 mac_write(sc, GMACTDLAR, _TDLAR); 749 mac_write(sc, GMACAFR, _AFR); 750 } 751 752 static int 753 scx_init(struct ifnet *ifp) 754 { 755 struct scx_softc *sc = ifp->if_softc; 756 const uint8_t *ea = CLLADDR(ifp->if_sadl); 757 uint32_t csr; 758 int i; 759 760 /* Cancel pending I/O. */ 761 scx_stop(ifp, 0); 762 763 /* Reset the chip to a known state. */ 764 scx_reset(sc); 765 766 /* build sane Tx and load Rx descriptors with mbuf */ 767 for (i = 0; i < MD_NTXDESC; i++) 768 sc->sc_txdescs[i].t0 = T0_OWN; 769 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 770 for (i = 0; i < MD_NRXDESC; i++) 771 (void)add_rxbuf(sc, i); 772 773 /* set my address in perfect match slot 0 */ 774 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 775 CSR_WRITE(sc, GMACMAL0, csr); 776 csr = (ea[5] << 8) | ea[4]; 777 CSR_WRITE(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 778 779 /* accept multicast frame or run promisc mode */ 780 scx_set_rcvfilt(sc); 781 782 (void)scx_ifmedia_upd(ifp); 783 784 /* kick to start GMAC engine */ 785 csr = mac_read(sc, GMACOMR); 786 CSR_WRITE(sc, RXINT_CLR, ~0); 787 CSR_WRITE(sc, TXINT_CLR, ~0); 788 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 789 790 ifp->if_flags |= IFF_RUNNING; 791 ifp->if_flags &= ~IFF_OACTIVE; 792 793 /* start one second timer */ 794 callout_schedule(&sc->sc_tick_ch, hz); 795 796 return 0; 797 } 798 799 static void 800 scx_stop(struct ifnet *ifp, int disable) 801 { 802 struct scx_softc *sc = ifp->if_softc; 803 804 /* Stop the one second clock. */ 805 callout_stop(&sc->sc_tick_ch); 806 807 /* Down the MII. */ 808 mii_down(&sc->sc_mii); 809 810 /* Mark the interface down and cancel the watchdog timer. */ 811 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 812 ifp->if_timer = 0; 813 } 814 815 static void 816 scx_watchdog(struct ifnet *ifp) 817 { 818 struct scx_softc *sc = ifp->if_softc; 819 820 /* 821 * Since we're not interrupting every packet, sweep 822 * up before we report an error. 823 */ 824 txreap(sc); 825 826 if (sc->sc_txfree != MD_NTXDESC) { 827 aprint_error_dev(sc->sc_dev, 828 "device timeout (txfree %d txsfree %d txnext %d)\n", 829 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 830 if_statinc(ifp, if_oerrors); 831 832 /* Reset the interface. */ 833 scx_init(ifp); 834 } 835 836 scx_start(ifp); 837 } 838 839 static int 840 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 841 { 842 struct scx_softc *sc = ifp->if_softc; 843 struct ifreq *ifr = (struct ifreq *)data; 844 struct ifmedia *ifm; 845 int s, error; 846 847 s = splnet(); 848 849 switch (cmd) { 850 case SIOCSIFMEDIA: 851 /* Flow control requires full-duplex mode. */ 852 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 853 (ifr->ifr_media & IFM_FDX) == 0) 854 ifr->ifr_media &= ~IFM_ETH_FMASK; 855 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 856 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 857 /* We can do both TXPAUSE and RXPAUSE. */ 858 ifr->ifr_media |= 859 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 860 } 861 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 862 } 863 ifm = &sc->sc_mii.mii_media; 864 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 865 break; 866 default: 867 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 868 break; 869 870 error = 0; 871 872 if (cmd == SIOCSIFCAP) 873 error = (*ifp->if_init)(ifp); 874 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 875 ; 876 else if (ifp->if_flags & IFF_RUNNING) { 877 /* 878 * Multicast list has changed; set the hardware filter 879 * accordingly. 880 */ 881 scx_set_rcvfilt(sc); 882 } 883 break; 884 } 885 886 splx(s); 887 return error; 888 } 889 890 static void 891 scx_set_rcvfilt(struct scx_softc *sc) 892 { 893 struct ethercom * const ec = &sc->sc_ethercom; 894 struct ifnet * const ifp = &ec->ec_if; 895 struct ether_multistep step; 896 struct ether_multi *enm; 897 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 898 uint32_t csr, crc; 899 int i; 900 901 csr = CSR_READ(sc, GMACAFR); 902 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 903 CSR_WRITE(sc, GMACAFR, csr); 904 905 ETHER_LOCK(ec); 906 if (ifp->if_flags & IFF_PROMISC) { 907 ec->ec_flags |= ETHER_F_ALLMULTI; 908 ETHER_UNLOCK(ec); 909 goto update; 910 } 911 ec->ec_flags &= ~ETHER_F_ALLMULTI; 912 913 /* clear 15 entry supplimental perfect match filter */ 914 for (i = 1; i < 16; i++) 915 CSR_WRITE(sc, GMACMAH(i), 0); 916 /* build 256 bit multicast hash filter */ 917 memset(mchash, 0, sizeof(mchash)); 918 crc = 0; 919 920 ETHER_FIRST_MULTI(step, ec, enm); 921 i = 1; /* slot 0 is occupied */ 922 while (enm != NULL) { 923 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 924 /* 925 * We must listen to a range of multicast addresses. 926 * For now, just accept all multicasts, rather than 927 * trying to set only those filter bits needed to match 928 * the range. (At this time, the only use of address 929 * ranges is for IP multicast routing, for which the 930 * range is big enough to require all bits set.) 931 */ 932 ec->ec_flags |= ETHER_F_ALLMULTI; 933 ETHER_UNLOCK(ec); 934 goto update; 935 } 936 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 937 if (i < 16) { 938 /* use 15 entry perfect match filter */ 939 uint32_t addr; 940 uint8_t *ep = enm->enm_addrlo; 941 addr = (ep[3] << 24) | (ep[2] << 16) 942 | (ep[1] << 8) | ep[0]; 943 CSR_WRITE(sc, GMACMAL(i), addr); 944 addr = (ep[5] << 8) | ep[4]; 945 CSR_WRITE(sc, GMACMAH(i), addr | 1U<<31); 946 } else { 947 /* use hash table when too many */ 948 /* bit_reserve_32(~crc) !? */ 949 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 950 /* 3(31:29) 5(28:24) bit sampling */ 951 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 952 } 953 ETHER_NEXT_MULTI(step, enm); 954 i++; 955 } 956 ETHER_UNLOCK(ec); 957 958 if (crc) 959 csr |= AFR_MHTE; 960 for (i = 0; i < __arraycount(mchash); i++) 961 CSR_WRITE(sc, GMACMHT(i), mchash[i]); 962 CSR_WRITE(sc, GMACAFR, csr); 963 return; 964 965 update: 966 /* With PM or AM, MHTE/MHT0-7 are never consulted. really? */ 967 if (ifp->if_flags & IFF_PROMISC) 968 csr |= AFR_PM; /* run promisc. mode */ 969 else 970 csr |= AFR_AM; /* accept all multicast */ 971 CSR_WRITE(sc, GMACAFR, csr); 972 return; 973 } 974 975 static int 976 scx_ifmedia_upd(struct ifnet *ifp) 977 { 978 struct scx_softc *sc = ifp->if_softc; 979 struct ifmedia *ifm = &sc->sc_mii.mii_media; 980 981 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 982 ; /* restart AN */ 983 ; /* enable AN */ 984 ; /* advertise flow control pause */ 985 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 986 } else { 987 #if 1 /* XXX not sure to belong here XXX */ 988 uint32_t mcr = mac_read(sc, GMACMCR); 989 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 990 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 991 else { 992 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX 993 && sc->sc_100mii) 994 mcr |= MCR_SPD100; 995 mcr |= MCR_USEMII; 996 } 997 if (ifm->ifm_cur->ifm_media & IFM_FDX) 998 mcr |= MCR_USEFDX; 999 mcr |= MCR_CST | MCR_JE; 1000 if (sc->sc_100mii == 0) 1001 mcr |= MCR_IBN; 1002 mac_write(sc, GMACMCR, mcr); 1003 #endif 1004 } 1005 return 0; 1006 } 1007 1008 static void 1009 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1010 { 1011 struct scx_softc *sc = ifp->if_softc; 1012 struct mii_data *mii = &sc->sc_mii; 1013 1014 mii_pollstat(mii); 1015 ifmr->ifm_status = mii->mii_media_status; 1016 ifmr->ifm_active = sc->sc_flowflags | 1017 (mii->mii_media_active & ~IFM_ETH_FMASK); 1018 } 1019 1020 void 1021 mii_statchg(struct ifnet *ifp) 1022 { 1023 struct scx_softc *sc = ifp->if_softc; 1024 struct mii_data *mii = &sc->sc_mii; 1025 uint32_t fcr; 1026 1027 /* Get flow control negotiation result. */ 1028 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1029 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1030 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1031 1032 /* Adjust PAUSE flow control. */ 1033 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1034 if (mii->mii_media_active & IFM_FDX) { 1035 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1036 fcr |= FCR_TFE; 1037 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1038 fcr |= FCR_RFE; 1039 } 1040 mac_write(sc, GMACFCR, fcr); 1041 1042 printf("%ctxfe, %crxfe\n", 1043 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1044 } 1045 1046 static void 1047 phy_tick(void *arg) 1048 { 1049 struct scx_softc *sc = arg; 1050 struct mii_data *mii = &sc->sc_mii; 1051 int s; 1052 1053 s = splnet(); 1054 mii_tick(mii); 1055 splx(s); 1056 1057 callout_schedule(&sc->sc_tick_ch, hz); 1058 } 1059 1060 static int 1061 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1062 { 1063 struct scx_softc *sc = device_private(self); 1064 uint32_t miia; 1065 int error; 1066 1067 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1068 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1069 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1070 if (error) 1071 return error; 1072 *val = mac_read(sc, GMACGDR); 1073 return 0; 1074 } 1075 1076 static int 1077 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1078 { 1079 struct scx_softc *sc = device_private(self); 1080 uint32_t miia; 1081 uint16_t dummy; 1082 int error; 1083 1084 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1085 mac_write(sc, GMACGDR, val); 1086 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1087 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1088 if (error) 1089 return error; 1090 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1091 return 0; 1092 } 1093 1094 static void 1095 scx_start(struct ifnet *ifp) 1096 { 1097 struct scx_softc *sc = ifp->if_softc; 1098 struct mbuf *m0, *m; 1099 struct scx_txsoft *txs; 1100 bus_dmamap_t dmamap; 1101 int error, nexttx, lasttx, ofree, seg; 1102 uint32_t tdes0; 1103 1104 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1105 return; 1106 1107 /* Remember the previous number of free descriptors. */ 1108 ofree = sc->sc_txfree; 1109 1110 /* 1111 * Loop through the send queue, setting up transmit descriptors 1112 * until we drain the queue, or use up all available transmit 1113 * descriptors. 1114 */ 1115 for (;;) { 1116 IFQ_POLL(&ifp->if_snd, m0); 1117 if (m0 == NULL) 1118 break; 1119 1120 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1121 txreap(sc); 1122 if (sc->sc_txsfree == 0) 1123 break; 1124 } 1125 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1126 dmamap = txs->txs_dmamap; 1127 1128 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1129 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1130 if (error) { 1131 if (error == EFBIG) { 1132 aprint_error_dev(sc->sc_dev, 1133 "Tx packet consumes too many " 1134 "DMA segments, dropping...\n"); 1135 IFQ_DEQUEUE(&ifp->if_snd, m0); 1136 m_freem(m0); 1137 continue; 1138 } 1139 /* Short on resources, just stop for now. */ 1140 break; 1141 } 1142 1143 if (dmamap->dm_nsegs > sc->sc_txfree) { 1144 /* 1145 * Not enough free descriptors to transmit this 1146 * packet. We haven't committed anything yet, 1147 * so just unload the DMA map, put the packet 1148 * back on the queue, and punt. Notify the upper 1149 * layer that there are not more slots left. 1150 */ 1151 ifp->if_flags |= IFF_OACTIVE; 1152 bus_dmamap_unload(sc->sc_dmat, dmamap); 1153 break; 1154 } 1155 1156 IFQ_DEQUEUE(&ifp->if_snd, m0); 1157 1158 /* 1159 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1160 */ 1161 1162 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1163 BUS_DMASYNC_PREWRITE); 1164 1165 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1166 lasttx = -1; 1167 for (nexttx = sc->sc_txnext, seg = 0; 1168 seg < dmamap->dm_nsegs; 1169 seg++, nexttx = MD_NEXTTX(nexttx)) { 1170 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1171 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1172 /* 1173 * If this is the first descriptor we're 1174 * enqueueing, don't set the OWN bit just 1175 * yet. That could cause a race condition. 1176 * We'll do it below. 1177 */ 1178 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1179 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1180 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1181 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1182 (15 << T0_TRID) | T0_PT | 1183 sc->sc_t0coso | T0_TRS; 1184 tdes0 = T0_OWN; /* 2nd and other segments */ 1185 lasttx = nexttx; 1186 } 1187 /* 1188 * Outgoing NFS mbuf must be unloaded when Tx completed. 1189 * Without T1_IC NFS mbuf is left unack'ed for excessive 1190 * time and NFS stops to proceed until scx_watchdog() 1191 * calls txreap() to reclaim the unack'ed mbuf. 1192 * It's painful to traverse every mbuf chain to determine 1193 * whether someone is waiting for Tx completion. 1194 */ 1195 m = m0; 1196 do { 1197 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1198 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1199 break; 1200 } 1201 } while ((m = m->m_next) != NULL); 1202 1203 /* Write deferred 1st segment T0_OWN at the final stage */ 1204 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1205 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1206 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1207 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1208 1209 /* Tell DMA start transmit */ 1210 /* CSR_WRITE(sc, GMACTDS, 1); */ 1211 1212 txs->txs_mbuf = m0; 1213 txs->txs_firstdesc = sc->sc_txnext; 1214 txs->txs_lastdesc = lasttx; 1215 txs->txs_ndesc = dmamap->dm_nsegs; 1216 1217 sc->sc_txfree -= txs->txs_ndesc; 1218 sc->sc_txnext = nexttx; 1219 sc->sc_txsfree--; 1220 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1221 /* 1222 * Pass the packet to any BPF listeners. 1223 */ 1224 bpf_mtap(ifp, m0, BPF_D_OUT); 1225 } 1226 1227 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1228 /* No more slots left; notify upper layer. */ 1229 ifp->if_flags |= IFF_OACTIVE; 1230 } 1231 if (sc->sc_txfree != ofree) { 1232 /* Set a watchdog timer in case the chip flakes out. */ 1233 ifp->if_timer = 5; 1234 } 1235 } 1236 1237 static int 1238 scx_intr(void *arg) 1239 { 1240 struct scx_softc *sc = arg; 1241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1242 1243 (void)ifp; 1244 rxintr(sc); 1245 txreap(sc); 1246 return 1; 1247 } 1248 1249 static void 1250 txreap(struct scx_softc *sc) 1251 { 1252 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1253 struct scx_txsoft *txs; 1254 uint32_t txstat; 1255 int i; 1256 1257 ifp->if_flags &= ~IFF_OACTIVE; 1258 1259 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1260 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1261 txs = &sc->sc_txsoft[i]; 1262 1263 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1264 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1265 1266 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1267 if (txstat & T0_OWN) /* desc is still in use */ 1268 break; 1269 1270 /* There is no way to tell transmission status per frame */ 1271 1272 if_statinc(ifp, if_opackets); 1273 1274 sc->sc_txfree += txs->txs_ndesc; 1275 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1276 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1277 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1278 m_freem(txs->txs_mbuf); 1279 txs->txs_mbuf = NULL; 1280 } 1281 sc->sc_txsdirty = i; 1282 if (sc->sc_txsfree == MD_TXQUEUELEN) 1283 ifp->if_timer = 0; 1284 } 1285 1286 static void 1287 rxintr(struct scx_softc *sc) 1288 { 1289 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1290 struct scx_rxsoft *rxs; 1291 struct mbuf *m; 1292 uint32_t rxstat; 1293 int i, len; 1294 1295 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1296 rxs = &sc->sc_rxsoft[i]; 1297 1298 SCX_CDRXSYNC(sc, i, 1299 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1300 1301 rxstat = sc->sc_rxdescs[i].r0; 1302 if (rxstat & R0_OWN) /* desc is left empty */ 1303 break; 1304 1305 /* R0_FS | R0_LS must have been marked for this desc */ 1306 1307 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1308 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1309 1310 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1311 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1312 m = rxs->rxs_mbuf; 1313 1314 if (add_rxbuf(sc, i) != 0) { 1315 if_statinc(ifp, if_ierrors); 1316 SCX_INIT_RXDESC(sc, i); 1317 bus_dmamap_sync(sc->sc_dmat, 1318 rxs->rxs_dmamap, 0, 1319 rxs->rxs_dmamap->dm_mapsize, 1320 BUS_DMASYNC_PREREAD); 1321 continue; 1322 } 1323 1324 m_set_rcvif(m, ifp); 1325 m->m_pkthdr.len = m->m_len = len; 1326 1327 if (rxstat & R0_CSUM) { 1328 uint32_t csum = M_CSUM_IPv4; 1329 if (rxstat & R0_CERR) 1330 csum |= M_CSUM_IPv4_BAD; 1331 m->m_pkthdr.csum_flags |= csum; 1332 } 1333 if_percpuq_enqueue(ifp->if_percpuq, m); 1334 } 1335 sc->sc_rxptr = i; 1336 } 1337 1338 static int 1339 add_rxbuf(struct scx_softc *sc, int i) 1340 { 1341 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1342 struct mbuf *m; 1343 int error; 1344 1345 MGETHDR(m, M_DONTWAIT, MT_DATA); 1346 if (m == NULL) 1347 return ENOBUFS; 1348 1349 MCLGET(m, M_DONTWAIT); 1350 if ((m->m_flags & M_EXT) == 0) { 1351 m_freem(m); 1352 return ENOBUFS; 1353 } 1354 1355 if (rxs->rxs_mbuf != NULL) 1356 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1357 1358 rxs->rxs_mbuf = m; 1359 1360 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1361 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1362 if (error) { 1363 aprint_error_dev(sc->sc_dev, 1364 "can't load rx DMA map %d, error = %d\n", i, error); 1365 panic("add_rxbuf"); 1366 } 1367 1368 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1369 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1370 SCX_INIT_RXDESC(sc, i); 1371 1372 return 0; 1373 } 1374 1375 static int 1376 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1377 { 1378 int val, loop; 1379 1380 val = CSR_READ(sc, reg); 1381 if ((val & exist) == 0) 1382 return 0; 1383 loop = 3000; 1384 do { 1385 DELAY(10); 1386 val = CSR_READ(sc, reg); 1387 } while (--loop > 0 && (val & exist)); 1388 return (loop > 0) ? 0 : ETIMEDOUT; 1389 } 1390 1391 static int 1392 mac_read(struct scx_softc *sc, int reg) 1393 { 1394 1395 CSR_WRITE(sc, MACCMD, reg); 1396 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1397 return CSR_READ(sc, MACDATA); 1398 } 1399 1400 static void 1401 mac_write(struct scx_softc *sc, int reg, int val) 1402 { 1403 1404 CSR_WRITE(sc, MACDATA, val); 1405 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1406 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1407 } 1408 1409 static int 1410 get_mdioclk(uint32_t freq) 1411 { 1412 1413 const struct { 1414 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 1415 } mdioclk[] = { 1416 { 35, 2 }, /* 25-35 MHz */ 1417 { 60, 3 }, /* 35-60 MHz */ 1418 { 100, 0 }, /* 60-100 MHz */ 1419 { 150, 1 }, /* 100-150 MHz */ 1420 { 250, 4 }, /* 150-250 MHz */ 1421 { 300, 5 }, /* 250-300 MHz */ 1422 }; 1423 int i; 1424 1425 /* convert MDIO clk to a divisor value */ 1426 if (freq < mdioclk[0].freq) 1427 return mdioclk[0].bit; 1428 for (i = 1; i < __arraycount(mdioclk); i++) { 1429 if (freq < mdioclk[i].freq) 1430 return mdioclk[i-1].bit; 1431 } 1432 return mdioclk[__arraycount(mdioclk) - 1].bit << GAR_CTL; 1433 } 1434 1435 static void 1436 loaducode(struct scx_softc *sc) 1437 { 1438 uint32_t up, lo, sz; 1439 uint64_t addr; 1440 1441 sc->sc_ucodeloaded = 1; 1442 1443 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1444 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1445 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1446 sz *= 4; 1447 addr = ((uint64_t)up << 32) | lo; 1448 aprint_normal_dev(sc->sc_dev, "H2M ucode %u\n", sz); 1449 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1450 1451 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1452 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1453 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1454 sz *= 4; 1455 addr = ((uint64_t)up << 32) | lo; 1456 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1457 aprint_normal_dev(sc->sc_dev, "M2H ucode %u\n", sz); 1458 1459 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1460 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1461 sz *= 4; 1462 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1463 aprint_normal_dev(sc->sc_dev, "PKT ucode %u\n", sz); 1464 } 1465 1466 static void 1467 injectucode(struct scx_softc *sc, int port, 1468 bus_addr_t addr, bus_size_t size) 1469 { 1470 bus_space_handle_t bsh; 1471 bus_size_t off; 1472 uint32_t ucode; 1473 1474 if (!bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1475 aprint_error_dev(sc->sc_dev, 1476 "eeprom map failure for ucode port 0x%x\n", port); 1477 return; 1478 } 1479 for (off = 0; off < size; off += 4) { 1480 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1481 CSR_WRITE(sc, port, ucode); 1482 } 1483 bus_space_unmap(sc->sc_st, bsh, size); 1484 } 1485
Indexes created Sun Sep 28 07:09:56 GMT 2025