if_scx.c revision 1.13
1 /* $NetBSD: if_scx.c,v 1.13 2020/03/25 01:39:49 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 16 or even 128. 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~16 are for supplimental MAC addresses. Independently enabled for 47 * use. Good to catch multicast. Byte-wise selective match available. 48 * Use the mask to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - 16~128 might be exact match without byte-mask. 50 * - The size of multicast hash filter store is unknown. Might be 256 bit. 51 * - Socionext/Linaro "NetSec" code makes many cut shorts. Some constants 52 * are left unexplained. The values should be handled via external 53 * controls like FDT descriptions. Fortunately, Intel/Altera CycloneV PDFs 54 * describe every detail of "such the instance of" DW EMAC IP and 55 * most of them are likely applicable to SC2A11 GbE. 56 */ 57 58 #include <sys/cdefs.h> 59 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.13 2020/03/25 01:39:49 nisimura Exp $"); 60 61 #include <sys/param.h> 62 #include <sys/bus.h> 63 #include <sys/intr.h> 64 #include <sys/device.h> 65 #include <sys/callout.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/errno.h> 69 #include <sys/rndsource.h> 70 #include <sys/kernel.h> 71 #include <sys/systm.h> 72 73 #include <net/if.h> 74 #include <net/if_media.h> 75 #include <net/if_dl.h> 76 #include <net/if_ether.h> 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <net/bpf.h> 80 81 #include <dev/fdt/fdtvar.h> 82 #include <dev/acpi/acpireg.h> 83 #include <dev/acpi/acpivar.h> 84 #include <dev/acpi/acpi_intr.h> 85 86 /* SC2A11 register block */ 87 #define SWRESET 0x104 88 #define COMINIT 0x120 89 #define INTRST 0x200 90 #define IRQ_RX (1U<<1) 91 #define IRQ_TX (1U<<0) 92 #define INTREN 0x204 93 #define INTR_SET 0x234 94 #define INTR_CLR 0x238 95 #define TXINTST 0x400 96 #define TXINTEN 0x404 97 #define TXINT_SET 0x428 98 #define TXINT_CLR 0x42c 99 #define TXI_NTOWNR (1U<<17) 100 #define TXI_TR_ERR (1U<<16) 101 #define TXI_TXDONE (1U<<15) 102 #define TXI_TMREXP (1U<<14) 103 #define RXINTST 0x440 104 #define RXINTEN 0x444 105 #define RXINT_SET 0x468 106 #define RXINT_CLR 0x46c 107 #define RXI_RC_ERR (1U<<16) 108 #define RXI_PKTCNT (1U<<15) 109 #define RXI_TMREXP (1U<<14) 110 #define TXTIMER 0x41c 111 #define RXTIMER 0x45c 112 #define TXCOUNT 0x410 113 #define RXCOUNT 0x454 114 #define H2MENG 0x210 /* DMAC host2media ucode port */ 115 #define M2HENG 0x21c /* DMAC media2host ucode port */ 116 #define PKTENG 0x0d0 /* packet engine ucode port */ 117 #define HWVER0 0x22c 118 #define HWVER1 0x230 119 120 #define MACSTAT 0x1024 /* gmac status */ 121 #define MACDATA 0x11c0 /* gmac rd/wr data */ 122 #define MACCMD 0x11c4 /* gmac operation */ 123 #define CMD_IOWR (1U<<28) /* write op */ 124 #define CMD_BUSY (1U<<31) /* busy bit */ 125 #define DESCENG_INIT 0x11fc 126 #define DESCENG_SRST 0x1204 127 128 /* GMAC register block. use mac_write()/mac_read() to handle */ 129 #define GMACMCR 0x0000 /* MAC configuration */ 130 #define MCR_IBN (1U<<30) /* */ 131 #define MCR_CST (1U<<25) /* strip CRC */ 132 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 133 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 134 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 135 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 136 #define MCR_USEFDX (1U<<11) /* force full duplex */ 137 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 138 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 139 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 140 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 141 #define _MCR_FDX 0x0000280c /* XXX TBD */ 142 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 143 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 144 #define AFR_RA (1U<<31) /* receive block all on */ 145 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 146 #define AFR_SAF (1U<<9) /* source address filter */ 147 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 148 #define AFR_PCF (3U<<6) /* */ 149 #define AFR_RB (1U<<5) /* reject broadcast frame */ 150 #define AFR_AM (1U<<4) /* accept all multicast frame */ 151 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 152 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 153 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 154 #define AFR_PM (1U<<0) /* run promisc mode */ 155 #define _AFR 0x80000001 /* XXX TBD */ 156 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 157 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 158 #define GMACGAR 0x0010 /* MDIO operation */ 159 #define GAR_PHY (11) /* mii phy 15:11 */ 160 #define GAR_REG (6) /* mii reg 10:6 */ 161 #define GAR_CTL (2) /* control 5:2 */ 162 #define GAR_IOWR (1U<<1) /* MDIO write op */ 163 #define GAR_BUSY (1U) /* busy bit */ 164 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 165 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 166 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 167 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 168 #define GMACVTAG 0x001c /* VLAN tag control */ 169 #define GMACIMPL 0x0020 /* implementation number XXXX.YYYY */ 170 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 171 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 172 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */ 173 #define GMACMAL(i) ((i)*8+0x44) 174 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 175 /* 3 link up detected 176 * 2:1 resovled speed 177 * 0 2.5Mhz (10Mbps) 178 * 1 25Mhz (100bps) 179 * 2 125Mhz (1000Mbps) 180 * 1 full duplex detected */ 181 182 #define GMACMHT0 0x0500 /* multicast hash table 0 - 7 */ 183 #define GMACMHT(i) ((i)*4+0x500) 184 #define GMACVHT 0x0588 /* VLAN tag hash */ 185 #define GMACAMAH(i) ((i)*8+0x800) /* supplimental MAC addr 16-127 */ 186 #define GMACAMAL(i) ((i)*8+0x804) 187 #define GMACEVCNT(i) ((i)*4+0x114) /* event counter 0x114~284 */ 188 #define GMACEVCTL 0x0100 /* clear event counter registers */ 189 190 #define GMACBMR 0x1000 /* DMA bus mode control 191 * 24 4PBL 192 * 22:17 RPBL 193 * 16 fix burst 194 * 15:14 priority between Rx and Tx 195 * 3 rxtx ratio 41 196 * 2 rxtx ratio 31 197 * 1 rxtx ratio 21 198 * 0 rxtx ratio 11 199 * 13:8 PBL possible DMA burst len 200 * 0 reset op. self clear 201 */ 202 #define _BMR 0x00412080 /* XXX TBD */ 203 #define _BMR0 0x00020181 /* XXX TBD */ 204 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 205 #define GMACTDS 0x1004 /* write any to resume tdes */ 206 #define GMACRDS 0x1008 /* write any to resume rdes */ 207 #define GMACRDLAR 0x100c /* rdes base address 32bit paddr */ 208 #define _RDLAR 0x18000 /* XXX TBD system SRAM with CC ? */ 209 #define GMACTDLAR 0x1010 /* tdes base address 32bit paddr */ 210 #define _TDLAR 0x1c000 /* XXX TBD system SRAM with CC ? */ 211 #define GMACOMR 0x1018 /* DMA operation */ 212 #define OMR_TXE (1U<<13) /* start Tx DMA engine, 0 to stop */ 213 #define OMR_RXE (1U<<1) /* start Rx DMA engine, 0 to stop */ 214 215 /* descriptor format definition */ 216 struct tdes { 217 uint32_t t0, t1, t2, t3; 218 }; 219 220 struct rdes { 221 uint32_t r0, r1, r2, r3; 222 }; 223 224 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 225 #define T0_EOD (1U<<30) /* end of descriptor array */ 226 #define T0_DRID (24) /* 29:24 D-RID */ 227 #define T0_PT (1U<<21) /* 23:21 PT */ 228 #define T0_TRID (16) /* 20:16 T-RID */ 229 #define T0_FS (1U<<9) /* first segment of frame */ 230 #define T0_LS (1U<<8) /* last segment of frame */ 231 #define T0_CSUM (1U<<7) /* enable check sum offload */ 232 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 233 #define T0_TRS (1U<<4) /* 5:4 TRS */ 234 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 235 /* T1 segment address 63:32 */ 236 /* T2 segment address 31:0 */ 237 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 238 #define R0_OWN (1U<<31) /* desc is empty */ 239 #define R0_EOD (1U<<30) /* end of descriptor array */ 240 #define R0_SRID (24) /* 29:24 S-RID */ 241 #define R0_FR (1U<<23) /* FR */ 242 #define R0_ER (1U<<21) /* Rx error indication */ 243 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 244 #define R0_TDRID (14) /* 15:14 TD-RID */ 245 #define R0_FS (1U<<9) /* first segment of frame */ 246 #define R0_LS (1U<<8) /* last segment of frame */ 247 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 248 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 249 /* R1 frame address 63:32 */ 250 /* R2 frame address 31:0 */ 251 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 252 253 #define MD_NTXSEGS 16 /* fixed */ 254 #define MD_TXQUEUELEN 16 /* tunable */ 255 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 256 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 257 #define MD_NTXDESC (MD_TXQUEUELEN * MD_NTXSEGS) 258 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 259 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 260 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 261 262 #define MD_NRXDESC 64 /* tunable */ 263 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 264 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 265 266 #define SCX_INIT_RXDESC(sc, x) \ 267 do { \ 268 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 269 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 270 struct mbuf *__m = __rxs->rxs_mbuf; \ 271 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 272 __m->m_data = __m->m_ext.ext_buf; \ 273 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 274 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 275 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 276 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 277 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 278 } while (/*CONSTCOND*/0) 279 280 struct control_data { 281 struct tdes cd_txdescs[MD_NTXDESC]; 282 struct rdes cd_rxdescs[MD_NRXDESC]; 283 }; 284 #define SCX_CDOFF(x) offsetof(struct control_data, x) 285 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 286 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 287 288 struct scx_txsoft { 289 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 290 bus_dmamap_t txs_dmamap; /* our DMA map */ 291 int txs_firstdesc; /* first descriptor in packet */ 292 int txs_lastdesc; /* last descriptor in packet */ 293 int txs_ndesc; /* # of descriptors used */ 294 }; 295 296 struct scx_rxsoft { 297 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 298 bus_dmamap_t rxs_dmamap; /* our DMA map */ 299 }; 300 301 struct scx_softc { 302 device_t sc_dev; /* generic device information */ 303 bus_space_tag_t sc_st; /* bus space tag */ 304 bus_space_handle_t sc_sh; /* bus space handle */ 305 bus_size_t sc_sz; /* csr map size */ 306 bus_space_handle_t sc_eesh; /* eeprom section handle */ 307 bus_size_t sc_eesz; /* eeprom map size */ 308 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 309 struct ethercom sc_ethercom; /* Ethernet common data */ 310 struct mii_data sc_mii; /* MII */ 311 callout_t sc_tick_ch; /* PHY monitor callout */ 312 bus_dma_segment_t sc_seg; /* descriptor store seg */ 313 int sc_nseg; /* descriptor store nseg */ 314 void *sc_ih; /* interrupt cookie */ 315 int sc_phy_id; /* PHY address */ 316 int sc_flowflags; /* 802.3x PAUSE flow control */ 317 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 318 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 319 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 320 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 321 int sc_phandle; /* fdt phandle */ 322 323 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 324 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 325 326 struct control_data *sc_control_data; 327 #define sc_txdescs sc_control_data->cd_txdescs 328 #define sc_rxdescs sc_control_data->cd_rxdescs 329 330 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 331 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 332 int sc_txfree; /* number of free Tx descriptors */ 333 int sc_txnext; /* next ready Tx descriptor */ 334 int sc_txsfree; /* number of free Tx jobs */ 335 int sc_txsnext; /* next ready Tx job */ 336 int sc_txsdirty; /* dirty Tx jobs */ 337 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 338 339 krndsource_t rnd_source; /* random source */ 340 }; 341 342 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 343 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 344 345 #define SCX_CDTXSYNC(sc, x, n, ops) \ 346 do { \ 347 int __x, __n; \ 348 \ 349 __x = (x); \ 350 __n = (n); \ 351 \ 352 /* If it will wrap around, sync to the end of the ring. */ \ 353 if ((__x + __n) > MD_NTXDESC) { \ 354 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 355 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 356 (MD_NTXDESC - __x), (ops)); \ 357 __n -= (MD_NTXDESC - __x); \ 358 __x = 0; \ 359 } \ 360 \ 361 /* Now sync whatever is left. */ \ 362 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 363 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 364 } while (/*CONSTCOND*/0) 365 366 #define SCX_CDRXSYNC(sc, x, ops) \ 367 do { \ 368 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 369 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 370 } while (/*CONSTCOND*/0) 371 372 static int scx_fdt_match(device_t, cfdata_t, void *); 373 static void scx_fdt_attach(device_t, device_t, void *); 374 static int scx_acpi_match(device_t, cfdata_t, void *); 375 static void scx_acpi_attach(device_t, device_t, void *); 376 377 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 378 scx_fdt_match, scx_fdt_attach, NULL, NULL); 379 380 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 381 scx_acpi_match, scx_acpi_attach, NULL, NULL); 382 383 static void scx_attach_i(struct scx_softc *); 384 static void scx_reset(struct scx_softc *); 385 static int scx_init(struct ifnet *); 386 static void scx_start(struct ifnet *); 387 static void scx_stop(struct ifnet *, int); 388 static void scx_watchdog(struct ifnet *); 389 static int scx_ioctl(struct ifnet *, u_long, void *); 390 static void scx_set_rcvfilt(struct scx_softc *); 391 static int scx_ifmedia_upd(struct ifnet *); 392 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 393 static void mii_statchg(struct ifnet *); 394 static void phy_tick(void *); 395 static int mii_readreg(device_t, int, int, uint16_t *); 396 static int mii_writereg(device_t, int, int, uint16_t); 397 static int scx_intr(void *); 398 static void txreap(struct scx_softc *); 399 static void rxintr(struct scx_softc *); 400 static int add_rxbuf(struct scx_softc *, int); 401 402 static int get_mdioclk(uint32_t); 403 static int spin_waitfor(struct scx_softc *, int, int); 404 static int mac_read(struct scx_softc *, int); 405 static void mac_write(struct scx_softc *, int, int); 406 static void loaducode(struct scx_softc *); 407 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 408 409 #define CSR_READ(sc,off) \ 410 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 411 #define CSR_WRITE(sc,off,val) \ 412 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 413 #define EE_READ(sc,off) \ 414 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 415 416 static int 417 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 418 { 419 static const char * compatible[] = { 420 "socionext,synquacer-netsec", 421 NULL 422 }; 423 struct fdt_attach_args * const faa = aux; 424 425 return of_match_compatible(faa->faa_phandle, compatible); 426 } 427 428 static void 429 scx_fdt_attach(device_t parent, device_t self, void *aux) 430 { 431 struct scx_softc * const sc = device_private(self); 432 struct fdt_attach_args * const faa = aux; 433 const int phandle = faa->faa_phandle; 434 bus_space_tag_t bst = faa->faa_bst; 435 bus_space_handle_t bsh; 436 bus_space_handle_t eebsh; 437 bus_addr_t addr[2]; 438 bus_size_t size[2]; 439 char intrstr[128]; 440 const char *phy_mode; 441 442 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 443 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 444 aprint_error(": unable to map device csr\n"); 445 return; 446 } 447 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 448 aprint_error(": failed to decode interrupt\n"); 449 goto fail; 450 } 451 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 452 NOT_MP_SAFE, scx_intr, sc); 453 if (sc->sc_ih == NULL) { 454 aprint_error_dev(self, "couldn't establish interrupt\n"); 455 goto fail; 456 } 457 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 458 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 459 aprint_error(": unable to map device eeprom\n"); 460 goto fail; 461 } 462 463 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 464 if (phy_mode == NULL) { 465 aprint_error(": missing 'phy-mode' property\n"); 466 phy_mode = "rgmii"; 467 } 468 469 aprint_naive("\n"); 470 aprint_normal(": Gigabit Ethernet Controller\n"); 471 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 472 473 sc->sc_dev = self; 474 sc->sc_st = bst; 475 sc->sc_sh = bsh; 476 sc->sc_sz = size[0]; 477 sc->sc_eesh = eebsh; 478 sc->sc_eesz = size[1]; 479 sc->sc_dmat = faa->faa_dmat; 480 sc->sc_phandle = phandle; 481 sc->sc_100mii = (strcmp(phy_mode, "rgmii") != 0); 482 483 scx_attach_i(sc); 484 return; 485 fail: 486 if (sc->sc_eesz) 487 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 488 if (sc->sc_sz) 489 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 490 return; 491 } 492 493 static int 494 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 495 { 496 static const char * compatible[] = { 497 "SCX0001", 498 NULL 499 }; 500 struct acpi_attach_args *aa = aux; 501 502 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 503 return 0; 504 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 505 } 506 507 static void 508 scx_acpi_attach(device_t parent, device_t self, void *aux) 509 { 510 struct scx_softc * const sc = device_private(self); 511 struct acpi_attach_args * const aa = aux; 512 ACPI_HANDLE handle = aa->aa_node->ad_handle; 513 bus_space_tag_t bst = aa->aa_memt; 514 bus_space_handle_t bsh, eebsh; 515 struct acpi_resources res; 516 struct acpi_mem *mem; 517 struct acpi_irq *irq; 518 ACPI_STATUS rv; 519 520 rv = acpi_resource_parse(self, handle, "_CRS", 521 &res, &acpi_resource_parse_ops_default); 522 if (ACPI_FAILURE(rv)) 523 return; 524 acpi_resource_print(self, &res); 525 mem = acpi_res_mem(&res, 0); 526 irq = acpi_res_irq(&res, 0); 527 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 528 aprint_error(": incomplete csr resources\n"); 529 return; 530 } 531 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 532 aprint_error(": couldn't map registers\n"); 533 return; 534 } 535 sc->sc_sz = mem->ar_length; 536 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 537 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 538 if (sc->sc_ih == NULL) { 539 aprint_error_dev(self, "couldn't establish interrupt\n"); 540 goto fail; 541 } 542 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 543 if (mem == NULL || mem->ar_length == 0) { 544 aprint_error(": incomplete eeprom resources\n"); 545 goto fail; 546 } 547 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 548 aprint_error(": couldn't map registers\n"); 549 goto fail; 550 } 551 sc->sc_eesz = mem->ar_length; 552 553 aprint_naive("\n"); 554 aprint_normal(": Gigabit Ethernet Controller\n"); 555 556 sc->sc_dev = self; 557 sc->sc_st = bst; 558 sc->sc_sh = bsh; 559 sc->sc_eesh = eebsh; 560 sc->sc_dmat = aa->aa_dmat64; 561 562 /* dig _DSD to see parameters. safe to assume RGMII/spd1000 though */ 563 564 scx_attach_i(sc); 565 566 acpi_resource_cleanup(&res); 567 return; 568 fail: 569 if (sc->sc_eesz > 0) 570 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 571 if (sc->sc_sz > 0) 572 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 573 acpi_resource_cleanup(&res); 574 return; 575 } 576 577 static void 578 scx_attach_i(struct scx_softc *sc) 579 { 580 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 581 struct mii_data * const mii = &sc->sc_mii; 582 struct ifmedia * const ifm = &mii->mii_media; 583 uint32_t hwver, phyfreq; 584 uint8_t enaddr[ETHER_ADDR_LEN]; 585 bus_dma_segment_t seg; 586 uint32_t csr; 587 int i, nseg, error = 0; 588 589 hwver = CSR_READ(sc, HWVER1); 590 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 591 enaddr[0] = csr >> 24; 592 enaddr[1] = csr >> 16; 593 enaddr[2] = csr >> 8; 594 enaddr[3] = csr; 595 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 596 enaddr[4] = csr >> 24; 597 enaddr[5] = csr >> 16; 598 csr = mac_read(sc, GMACIMPL); 599 600 aprint_normal_dev(sc->sc_dev, "NetSec GbE (%d.%d) impl (%x.%x)\n", 601 hwver >> 16, hwver & 0xffff, csr >> 16, csr & 0xffff); 602 aprint_normal_dev(sc->sc_dev, 603 "Ethernet address %s\n", ether_sprintf(enaddr)); 604 605 phyfreq = 0; 606 sc->sc_phy_id = MII_PHY_ANY; 607 sc->sc_mdclk = get_mdioclk(phyfreq); /* 5:2 clk control */ 608 609 sc->sc_flowflags = 0; 610 611 if (sc->sc_ucodeloaded == 0) 612 loaducode(sc); 613 614 mii->mii_ifp = ifp; 615 mii->mii_readreg = mii_readreg; 616 mii->mii_writereg = mii_writereg; 617 mii->mii_statchg = mii_statchg; 618 619 sc->sc_ethercom.ec_mii = mii; 620 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 621 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 622 MII_OFFSET_ANY, MIIF_DOPAUSE); 623 if (LIST_FIRST(&mii->mii_phys) == NULL) { 624 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 625 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 626 } else 627 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 628 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 629 630 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 631 ifp->if_softc = sc; 632 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 633 ifp->if_ioctl = scx_ioctl; 634 ifp->if_start = scx_start; 635 ifp->if_watchdog = scx_watchdog; 636 ifp->if_init = scx_init; 637 ifp->if_stop = scx_stop; 638 IFQ_SET_READY(&ifp->if_snd); 639 640 if_attach(ifp); 641 if_deferred_start_init(ifp, NULL); 642 ether_ifattach(ifp, enaddr); 643 644 callout_init(&sc->sc_tick_ch, 0); 645 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 646 647 /* 648 * Allocate the control data structures, and create and load the 649 * DMA map for it. 650 */ 651 error = bus_dmamem_alloc(sc->sc_dmat, 652 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 653 if (error != 0) { 654 aprint_error_dev(sc->sc_dev, 655 "unable to allocate control data, error = %d\n", error); 656 goto fail_0; 657 } 658 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 659 sizeof(struct control_data), (void **)&sc->sc_control_data, 660 BUS_DMA_COHERENT); 661 if (error != 0) { 662 aprint_error_dev(sc->sc_dev, 663 "unable to map control data, error = %d\n", error); 664 goto fail_1; 665 } 666 error = bus_dmamap_create(sc->sc_dmat, 667 sizeof(struct control_data), 1, 668 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 669 if (error != 0) { 670 aprint_error_dev(sc->sc_dev, 671 "unable to create control data DMA map, " 672 "error = %d\n", error); 673 goto fail_2; 674 } 675 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 676 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 677 if (error != 0) { 678 aprint_error_dev(sc->sc_dev, 679 "unable to load control data DMA map, error = %d\n", 680 error); 681 goto fail_3; 682 } 683 for (i = 0; i < MD_TXQUEUELEN; i++) { 684 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 685 MD_NTXSEGS, MCLBYTES, 0, 0, 686 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 687 aprint_error_dev(sc->sc_dev, 688 "unable to create tx DMA map %d, error = %d\n", 689 i, error); 690 goto fail_4; 691 } 692 } 693 for (i = 0; i < MD_NRXDESC; i++) { 694 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 695 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 696 aprint_error_dev(sc->sc_dev, 697 "unable to create rx DMA map %d, error = %d\n", 698 i, error); 699 goto fail_5; 700 } 701 sc->sc_rxsoft[i].rxs_mbuf = NULL; 702 } 703 sc->sc_seg = seg; 704 sc->sc_nseg = nseg; 705 printf("bus_dmaseg ds_addr %08lx, ds_len %08lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 706 707 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 708 pmf_class_network_register(sc->sc_dev, ifp); 709 else 710 aprint_error_dev(sc->sc_dev, 711 "couldn't establish power handler\n"); 712 713 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 714 RND_TYPE_NET, RND_FLAG_DEFAULT); 715 716 return; 717 718 fail_5: 719 for (i = 0; i < MD_NRXDESC; i++) { 720 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 721 bus_dmamap_destroy(sc->sc_dmat, 722 sc->sc_rxsoft[i].rxs_dmamap); 723 } 724 fail_4: 725 for (i = 0; i < MD_TXQUEUELEN; i++) { 726 if (sc->sc_txsoft[i].txs_dmamap != NULL) 727 bus_dmamap_destroy(sc->sc_dmat, 728 sc->sc_txsoft[i].txs_dmamap); 729 } 730 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 731 fail_3: 732 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 733 fail_2: 734 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 735 sizeof(struct control_data)); 736 fail_1: 737 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 738 fail_0: 739 if (sc->sc_phandle) 740 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 741 else 742 acpi_intr_disestablish(sc->sc_ih); 743 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 744 return; 745 } 746 747 static void 748 scx_reset(struct scx_softc *sc) 749 { 750 751 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 752 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 753 754 CSR_WRITE(sc, DESCENG_SRST, 1); 755 CSR_WRITE(sc, DESCENG_INIT, 1); 756 mac_write(sc, GMACBMR, _BMR); 757 mac_write(sc, GMACRDLAR, _RDLAR); 758 mac_write(sc, GMACTDLAR, _TDLAR); 759 mac_write(sc, GMACAFR, _AFR); 760 mac_write(sc, GMACEVCTL, 1); 761 } 762 763 static int 764 scx_init(struct ifnet *ifp) 765 { 766 struct scx_softc *sc = ifp->if_softc; 767 const uint8_t *ea = CLLADDR(ifp->if_sadl); 768 uint32_t csr; 769 int i; 770 771 /* Cancel pending I/O. */ 772 scx_stop(ifp, 0); 773 774 /* Reset the chip to a known state. */ 775 scx_reset(sc); 776 777 /* set my address in perfect match slot 0 */ 778 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 779 mac_write(sc, GMACMAL0, csr); 780 csr = (ea[5] << 8) | ea[4]; 781 mac_write(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 782 783 /* accept multicast frame or run promisc mode */ 784 scx_set_rcvfilt(sc); 785 786 (void)scx_ifmedia_upd(ifp); 787 788 /* build sane Tx */ 789 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 790 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 791 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 792 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 793 sc->sc_txfree = MD_NTXDESC; 794 sc->sc_txnext = 0; 795 for (i = 0; i < MD_TXQUEUELEN; i++) 796 sc->sc_txsoft[i].txs_mbuf = NULL; 797 sc->sc_txsfree = MD_TXQUEUELEN; 798 sc->sc_txsnext = 0; 799 sc->sc_txsdirty = 0; 800 801 /* load Rx descriptors with fresh mbuf */ 802 for (i = 0; i < MD_NRXDESC; i++) 803 (void)add_rxbuf(sc, i); 804 sc->sc_rxptr = 0; 805 806 /* XXX 32 bit paddr XXX hand Tx/Rx rings to HW XXX */ 807 mac_write(sc, GMACTDLAR, SCX_CDTXADDR(sc, 0)); 808 mac_write(sc, GMACRDLAR, SCX_CDRXADDR(sc, 0)); 809 810 /* kick to start GMAC engine */ 811 CSR_WRITE(sc, RXINT_CLR, ~0); 812 CSR_WRITE(sc, TXINT_CLR, ~0); 813 csr = mac_read(sc, GMACOMR); 814 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 815 816 ifp->if_flags |= IFF_RUNNING; 817 ifp->if_flags &= ~IFF_OACTIVE; 818 819 /* start one second timer */ 820 callout_schedule(&sc->sc_tick_ch, hz); 821 822 return 0; 823 } 824 825 static void 826 scx_stop(struct ifnet *ifp, int disable) 827 { 828 struct scx_softc *sc = ifp->if_softc; 829 830 /* Stop the one second clock. */ 831 callout_stop(&sc->sc_tick_ch); 832 833 /* Down the MII. */ 834 mii_down(&sc->sc_mii); 835 836 /* Mark the interface down and cancel the watchdog timer. */ 837 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 838 ifp->if_timer = 0; 839 } 840 841 static void 842 scx_watchdog(struct ifnet *ifp) 843 { 844 struct scx_softc *sc = ifp->if_softc; 845 846 /* 847 * Since we're not interrupting every packet, sweep 848 * up before we report an error. 849 */ 850 txreap(sc); 851 852 if (sc->sc_txfree != MD_NTXDESC) { 853 aprint_error_dev(sc->sc_dev, 854 "device timeout (txfree %d txsfree %d txnext %d)\n", 855 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 856 if_statinc(ifp, if_oerrors); 857 858 /* Reset the interface. */ 859 scx_init(ifp); 860 } 861 862 scx_start(ifp); 863 } 864 865 static int 866 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 867 { 868 struct scx_softc *sc = ifp->if_softc; 869 struct ifreq *ifr = (struct ifreq *)data; 870 struct ifmedia *ifm; 871 int s, error; 872 873 s = splnet(); 874 875 switch (cmd) { 876 case SIOCSIFMEDIA: 877 /* Flow control requires full-duplex mode. */ 878 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 879 (ifr->ifr_media & IFM_FDX) == 0) 880 ifr->ifr_media &= ~IFM_ETH_FMASK; 881 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 882 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 883 /* We can do both TXPAUSE and RXPAUSE. */ 884 ifr->ifr_media |= 885 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 886 } 887 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 888 } 889 ifm = &sc->sc_mii.mii_media; 890 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 891 break; 892 default: 893 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 894 break; 895 896 error = 0; 897 898 if (cmd == SIOCSIFCAP) 899 error = (*ifp->if_init)(ifp); 900 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 901 ; 902 else if (ifp->if_flags & IFF_RUNNING) { 903 /* 904 * Multicast list has changed; set the hardware filter 905 * accordingly. 906 */ 907 scx_set_rcvfilt(sc); 908 } 909 break; 910 } 911 912 splx(s); 913 return error; 914 } 915 916 static void 917 scx_set_rcvfilt(struct scx_softc *sc) 918 { 919 struct ethercom * const ec = &sc->sc_ethercom; 920 struct ifnet * const ifp = &ec->ec_if; 921 struct ether_multistep step; 922 struct ether_multi *enm; 923 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 924 uint32_t csr, crc; 925 int i; 926 927 csr = mac_read(sc, GMACAFR); 928 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 929 mac_write(sc, GMACAFR, csr); 930 931 ETHER_LOCK(ec); 932 if (ifp->if_flags & IFF_PROMISC) { 933 ec->ec_flags |= ETHER_F_ALLMULTI; 934 ETHER_UNLOCK(ec); 935 goto update; 936 } 937 ec->ec_flags &= ~ETHER_F_ALLMULTI; 938 939 /* clear 15 entry supplimental perfect match filter */ 940 for (i = 1; i < 16; i++) 941 mac_write(sc, GMACMAH(i), 0); 942 /* build 256 bit multicast hash filter */ 943 memset(mchash, 0, sizeof(mchash)); 944 crc = 0; 945 946 ETHER_FIRST_MULTI(step, ec, enm); 947 i = 1; /* slot 0 is occupied */ 948 while (enm != NULL) { 949 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 950 /* 951 * We must listen to a range of multicast addresses. 952 * For now, just accept all multicasts, rather than 953 * trying to set only those filter bits needed to match 954 * the range. (At this time, the only use of address 955 * ranges is for IP multicast routing, for which the 956 * range is big enough to require all bits set.) 957 */ 958 ec->ec_flags |= ETHER_F_ALLMULTI; 959 ETHER_UNLOCK(ec); 960 goto update; 961 } 962 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 963 if (i < 16) { 964 /* use 15 entry perfect match filter */ 965 uint32_t addr; 966 uint8_t *ep = enm->enm_addrlo; 967 addr = (ep[3] << 24) | (ep[2] << 16) 968 | (ep[1] << 8) | ep[0]; 969 mac_write(sc, GMACMAL(i), addr); 970 addr = (ep[5] << 8) | ep[4]; 971 mac_write(sc, GMACMAH(i), addr | 1U<<31); 972 } else { 973 /* use hash table when too many */ 974 /* bit_reserve_32(~crc) !? */ 975 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 976 /* 3(31:29) 5(28:24) bit sampling */ 977 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 978 } 979 ETHER_NEXT_MULTI(step, enm); 980 i++; 981 } 982 ETHER_UNLOCK(ec); 983 984 if (crc) 985 csr |= AFR_MHTE; 986 for (i = 0; i < __arraycount(mchash); i++) 987 mac_write(sc, GMACMHT(i), mchash[i]); 988 mac_write(sc, GMACAFR, csr); 989 return; 990 991 update: 992 /* With PM or AM, MHTE/MHT0-7 are never consulted. really? */ 993 if (ifp->if_flags & IFF_PROMISC) 994 csr |= AFR_PM; /* run promisc. mode */ 995 else 996 csr |= AFR_AM; /* accept all multicast */ 997 mac_write(sc, GMACAFR, csr); 998 return; 999 } 1000 1001 static int 1002 scx_ifmedia_upd(struct ifnet *ifp) 1003 { 1004 struct scx_softc *sc = ifp->if_softc; 1005 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1006 1007 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 1008 ; /* restart AN */ 1009 ; /* enable AN */ 1010 ; /* advertise flow control pause */ 1011 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 1012 } else { 1013 #if 1 /* XXX not sure to belong here XXX */ 1014 uint32_t mcr = mac_read(sc, GMACMCR); 1015 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 1016 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1017 else { 1018 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX 1019 && sc->sc_100mii) 1020 mcr |= MCR_SPD100; 1021 mcr |= MCR_USEMII; 1022 } 1023 if (ifm->ifm_cur->ifm_media & IFM_FDX) 1024 mcr |= MCR_USEFDX; 1025 mcr |= MCR_CST | MCR_JE; 1026 if (sc->sc_100mii == 0) 1027 mcr |= MCR_IBN; 1028 mac_write(sc, GMACMCR, mcr); 1029 #endif 1030 } 1031 return 0; 1032 } 1033 1034 static void 1035 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1036 { 1037 struct scx_softc *sc = ifp->if_softc; 1038 struct mii_data *mii = &sc->sc_mii; 1039 1040 mii_pollstat(mii); 1041 ifmr->ifm_status = mii->mii_media_status; 1042 ifmr->ifm_active = sc->sc_flowflags | 1043 (mii->mii_media_active & ~IFM_ETH_FMASK); 1044 } 1045 1046 void 1047 mii_statchg(struct ifnet *ifp) 1048 { 1049 struct scx_softc *sc = ifp->if_softc; 1050 struct mii_data *mii = &sc->sc_mii; 1051 uint32_t fcr; 1052 #if 1 1053 /* decode MIISR register value */ 1054 uint32_t miisr = mac_read(sc, GMACMIISR); 1055 int spd = (miisr >> 1) & 03; 1056 printf("xMII link status (0x%x) spd%d", miisr, 1057 (spd == 2) ? 1000 : (spd == 1) ? 100 : 10); 1058 if (miisr & 1) 1059 printf(",full-duplex"); 1060 printf("\n"); 1061 #endif 1062 /* Get flow control negotiation result. */ 1063 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1064 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1065 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1066 1067 /* Adjust PAUSE flow control. */ 1068 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1069 if (mii->mii_media_active & IFM_FDX) { 1070 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1071 fcr |= FCR_TFE; 1072 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1073 fcr |= FCR_RFE; 1074 } 1075 mac_write(sc, GMACFCR, fcr); 1076 1077 printf("%ctxfe, %crxfe\n", 1078 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1079 } 1080 1081 static void 1082 phy_tick(void *arg) 1083 { 1084 struct scx_softc *sc = arg; 1085 struct mii_data *mii = &sc->sc_mii; 1086 int s; 1087 1088 s = splnet(); 1089 mii_tick(mii); 1090 splx(s); 1091 1092 callout_schedule(&sc->sc_tick_ch, hz); 1093 } 1094 1095 static int 1096 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1097 { 1098 struct scx_softc *sc = device_private(self); 1099 uint32_t miia; 1100 int error; 1101 1102 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1103 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1104 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1105 if (error) 1106 return error; 1107 *val = mac_read(sc, GMACGDR); 1108 return 0; 1109 } 1110 1111 static int 1112 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1113 { 1114 struct scx_softc *sc = device_private(self); 1115 uint32_t miia; 1116 uint16_t dummy; 1117 int error; 1118 1119 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1120 mac_write(sc, GMACGDR, val); 1121 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1122 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1123 if (error) 1124 return error; 1125 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1126 return 0; 1127 } 1128 1129 static void 1130 scx_start(struct ifnet *ifp) 1131 { 1132 struct scx_softc *sc = ifp->if_softc; 1133 struct mbuf *m0, *m; 1134 struct scx_txsoft *txs; 1135 bus_dmamap_t dmamap; 1136 int error, nexttx, lasttx, ofree, seg; 1137 uint32_t tdes0; 1138 1139 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1140 return; 1141 1142 /* Remember the previous number of free descriptors. */ 1143 ofree = sc->sc_txfree; 1144 1145 /* 1146 * Loop through the send queue, setting up transmit descriptors 1147 * until we drain the queue, or use up all available transmit 1148 * descriptors. 1149 */ 1150 for (;;) { 1151 IFQ_POLL(&ifp->if_snd, m0); 1152 if (m0 == NULL) 1153 break; 1154 1155 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1156 txreap(sc); 1157 if (sc->sc_txsfree == 0) 1158 break; 1159 } 1160 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1161 dmamap = txs->txs_dmamap; 1162 1163 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1164 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1165 if (error) { 1166 if (error == EFBIG) { 1167 aprint_error_dev(sc->sc_dev, 1168 "Tx packet consumes too many " 1169 "DMA segments, dropping...\n"); 1170 IFQ_DEQUEUE(&ifp->if_snd, m0); 1171 m_freem(m0); 1172 continue; 1173 } 1174 /* Short on resources, just stop for now. */ 1175 break; 1176 } 1177 1178 if (dmamap->dm_nsegs > sc->sc_txfree) { 1179 /* 1180 * Not enough free descriptors to transmit this 1181 * packet. We haven't committed anything yet, 1182 * so just unload the DMA map, put the packet 1183 * back on the queue, and punt. Notify the upper 1184 * layer that there are not more slots left. 1185 */ 1186 ifp->if_flags |= IFF_OACTIVE; 1187 bus_dmamap_unload(sc->sc_dmat, dmamap); 1188 break; 1189 } 1190 1191 IFQ_DEQUEUE(&ifp->if_snd, m0); 1192 1193 /* 1194 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1195 */ 1196 1197 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1198 BUS_DMASYNC_PREWRITE); 1199 1200 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1201 lasttx = -1; 1202 for (nexttx = sc->sc_txnext, seg = 0; 1203 seg < dmamap->dm_nsegs; 1204 seg++, nexttx = MD_NEXTTX(nexttx)) { 1205 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1206 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1207 /* 1208 * If this is the first descriptor we're 1209 * enqueueing, don't set the OWN bit just 1210 * yet. That could cause a race condition. 1211 * We'll do it below. 1212 */ 1213 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1214 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1215 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1216 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1217 (15 << T0_TRID) | T0_PT | 1218 sc->sc_t0coso | T0_TRS; 1219 tdes0 = T0_OWN; /* 2nd and other segments */ 1220 lasttx = nexttx; 1221 } 1222 /* 1223 * Outgoing NFS mbuf must be unloaded when Tx completed. 1224 * Without T1_IC NFS mbuf is left unack'ed for excessive 1225 * time and NFS stops to proceed until scx_watchdog() 1226 * calls txreap() to reclaim the unack'ed mbuf. 1227 * It's painful to traverse every mbuf chain to determine 1228 * whether someone is waiting for Tx completion. 1229 */ 1230 m = m0; 1231 do { 1232 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1233 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1234 break; 1235 } 1236 } while ((m = m->m_next) != NULL); 1237 1238 /* Write deferred 1st segment T0_OWN at the final stage */ 1239 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1240 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1241 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1242 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1243 1244 /* Tell DMA start transmit */ 1245 mac_write(sc, GMACTDS, 1); 1246 1247 txs->txs_mbuf = m0; 1248 txs->txs_firstdesc = sc->sc_txnext; 1249 txs->txs_lastdesc = lasttx; 1250 txs->txs_ndesc = dmamap->dm_nsegs; 1251 1252 sc->sc_txfree -= txs->txs_ndesc; 1253 sc->sc_txnext = nexttx; 1254 sc->sc_txsfree--; 1255 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1256 /* 1257 * Pass the packet to any BPF listeners. 1258 */ 1259 bpf_mtap(ifp, m0, BPF_D_OUT); 1260 } 1261 1262 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1263 /* No more slots left; notify upper layer. */ 1264 ifp->if_flags |= IFF_OACTIVE; 1265 } 1266 if (sc->sc_txfree != ofree) { 1267 /* Set a watchdog timer in case the chip flakes out. */ 1268 ifp->if_timer = 5; 1269 } 1270 } 1271 1272 static int 1273 scx_intr(void *arg) 1274 { 1275 struct scx_softc *sc = arg; 1276 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1277 1278 (void)ifp; 1279 /* XXX decode interrupt cause to pick isr() XXX */ 1280 rxintr(sc); 1281 txreap(sc); 1282 return 1; 1283 } 1284 1285 static void 1286 txreap(struct scx_softc *sc) 1287 { 1288 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1289 struct scx_txsoft *txs; 1290 uint32_t txstat; 1291 int i; 1292 1293 ifp->if_flags &= ~IFF_OACTIVE; 1294 1295 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1296 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1297 txs = &sc->sc_txsoft[i]; 1298 1299 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1300 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1301 1302 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1303 if (txstat & T0_OWN) /* desc is still in use */ 1304 break; 1305 1306 /* There is no way to tell transmission status per frame */ 1307 1308 if_statinc(ifp, if_opackets); 1309 1310 sc->sc_txfree += txs->txs_ndesc; 1311 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1312 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1313 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1314 m_freem(txs->txs_mbuf); 1315 txs->txs_mbuf = NULL; 1316 } 1317 sc->sc_txsdirty = i; 1318 if (sc->sc_txsfree == MD_TXQUEUELEN) 1319 ifp->if_timer = 0; 1320 } 1321 1322 static void 1323 rxintr(struct scx_softc *sc) 1324 { 1325 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1326 struct scx_rxsoft *rxs; 1327 struct mbuf *m; 1328 uint32_t rxstat; 1329 int i, len; 1330 1331 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1332 rxs = &sc->sc_rxsoft[i]; 1333 1334 SCX_CDRXSYNC(sc, i, 1335 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1336 1337 rxstat = sc->sc_rxdescs[i].r0; 1338 if (rxstat & R0_OWN) /* desc is left empty */ 1339 break; 1340 1341 /* R0_FS | R0_LS must have been marked for this desc */ 1342 1343 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1344 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1345 1346 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1347 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1348 m = rxs->rxs_mbuf; 1349 1350 if (add_rxbuf(sc, i) != 0) { 1351 if_statinc(ifp, if_ierrors); 1352 SCX_INIT_RXDESC(sc, i); 1353 bus_dmamap_sync(sc->sc_dmat, 1354 rxs->rxs_dmamap, 0, 1355 rxs->rxs_dmamap->dm_mapsize, 1356 BUS_DMASYNC_PREREAD); 1357 continue; 1358 } 1359 1360 m_set_rcvif(m, ifp); 1361 m->m_pkthdr.len = m->m_len = len; 1362 1363 if (rxstat & R0_CSUM) { 1364 uint32_t csum = M_CSUM_IPv4; 1365 if (rxstat & R0_CERR) 1366 csum |= M_CSUM_IPv4_BAD; 1367 m->m_pkthdr.csum_flags |= csum; 1368 } 1369 if_percpuq_enqueue(ifp->if_percpuq, m); 1370 } 1371 sc->sc_rxptr = i; 1372 } 1373 1374 static int 1375 add_rxbuf(struct scx_softc *sc, int i) 1376 { 1377 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1378 struct mbuf *m; 1379 int error; 1380 1381 MGETHDR(m, M_DONTWAIT, MT_DATA); 1382 if (m == NULL) 1383 return ENOBUFS; 1384 1385 MCLGET(m, M_DONTWAIT); 1386 if ((m->m_flags & M_EXT) == 0) { 1387 m_freem(m); 1388 return ENOBUFS; 1389 } 1390 1391 if (rxs->rxs_mbuf != NULL) 1392 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1393 1394 rxs->rxs_mbuf = m; 1395 1396 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1397 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1398 if (error) { 1399 aprint_error_dev(sc->sc_dev, 1400 "can't load rx DMA map %d, error = %d\n", i, error); 1401 panic("add_rxbuf"); 1402 } 1403 1404 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1405 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1406 SCX_INIT_RXDESC(sc, i); 1407 1408 return 0; 1409 } 1410 1411 static int 1412 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1413 { 1414 int val, loop; 1415 1416 val = CSR_READ(sc, reg); 1417 if ((val & exist) == 0) 1418 return 0; 1419 loop = 3000; 1420 do { 1421 DELAY(10); 1422 val = CSR_READ(sc, reg); 1423 } while (--loop > 0 && (val & exist)); 1424 return (loop > 0) ? 0 : ETIMEDOUT; 1425 } 1426 1427 /* GMAC register needs to use indirect rd/wr via memory mapped registers. */ 1428 1429 static int 1430 mac_read(struct scx_softc *sc, int reg) 1431 { 1432 1433 CSR_WRITE(sc, MACCMD, reg); 1434 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1435 return CSR_READ(sc, MACDATA); 1436 } 1437 1438 static void 1439 mac_write(struct scx_softc *sc, int reg, int val) 1440 { 1441 1442 CSR_WRITE(sc, MACDATA, val); 1443 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1444 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1445 } 1446 1447 /* 1448 * 3 independent uengines exist * to process host2media, media2host and 1449 * packet data flows. 1450 */ 1451 static void 1452 loaducode(struct scx_softc *sc) 1453 { 1454 uint32_t up, lo, sz; 1455 uint64_t addr; 1456 1457 sc->sc_ucodeloaded = 1; 1458 1459 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1460 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1461 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1462 sz *= 4; 1463 addr = ((uint64_t)up << 32) | lo; 1464 aprint_normal_dev(sc->sc_dev, "H2M ucode %u\n", sz); 1465 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1466 1467 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1468 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1469 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1470 sz *= 4; 1471 addr = ((uint64_t)up << 32) | lo; 1472 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1473 aprint_normal_dev(sc->sc_dev, "M2H ucode %u\n", sz); 1474 1475 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1476 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1477 sz *= 4; 1478 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1479 aprint_normal_dev(sc->sc_dev, "PKT ucode %u\n", sz); 1480 } 1481 1482 static void 1483 injectucode(struct scx_softc *sc, int port, 1484 bus_addr_t addr, bus_size_t size) 1485 { 1486 bus_space_handle_t bsh; 1487 bus_size_t off; 1488 uint32_t ucode; 1489 1490 if (!bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1491 aprint_error_dev(sc->sc_dev, 1492 "eeprom map failure for ucode port 0x%x\n", port); 1493 return; 1494 } 1495 for (off = 0; off < size; off += 4) { 1496 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1497 CSR_WRITE(sc, port, ucode); 1498 } 1499 bus_space_unmap(sc->sc_st, bsh, size); 1500 } 1501 1502 /* bit selection to determine MDIO speed */ 1503 1504 static int 1505 get_mdioclk(uint32_t freq) 1506 { 1507 1508 const struct { 1509 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 1510 } mdioclk[] = { 1511 { 35, 2 }, /* 25-35 MHz */ 1512 { 60, 3 }, /* 35-60 MHz */ 1513 { 100, 0 }, /* 60-100 MHz */ 1514 { 150, 1 }, /* 100-150 MHz */ 1515 { 250, 4 }, /* 150-250 MHz */ 1516 { 300, 5 }, /* 250-300 MHz */ 1517 }; 1518 int i; 1519 1520 /* convert MDIO clk to a divisor value */ 1521 if (freq < mdioclk[0].freq) 1522 return mdioclk[0].bit; 1523 for (i = 1; i < __arraycount(mdioclk); i++) { 1524 if (freq < mdioclk[i].freq) 1525 return mdioclk[i-1].bit; 1526 } 1527 return mdioclk[__arraycount(mdioclk) - 1].bit << GAR_CTL; 1528 } 1529
Indexes created Thu Sep 25 16:09:42 GMT 2025