if_scx.c revision 1.14
1 /* $NetBSD: if_scx.c,v 1.14 2020/03/25 20:19:46 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 16 or even 128. 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~16 are for supplimental MAC addresses. Independently enabled for 47 * use. Good to catch multicast. Byte-wise selective match available. 48 * Use the mask to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - 16~128 might be exact match without byte-mask. 50 * - The size of multicast hash filter store is unknown. Might be 256 bit. 51 * - Socionext/Linaro "NetSec" code makes many cut shorts. Some constants 52 * are left unexplained. The values should be handled via external 53 * controls like FDT descriptions. Fortunately, Intel/Altera CycloneV PDFs 54 * describe every detail of "such the instance of" DW EMAC IP and 55 * most of them are likely applicable to SC2A11 GbE. 56 * - DW EMAC implmentation (0x20) is 0x10.0x36 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.14 2020/03/25 20:19:46 nisimura Exp $"); 61 62 #include <sys/param.h> 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 #include <sys/device.h> 66 #include <sys/callout.h> 67 #include <sys/mbuf.h> 68 #include <sys/malloc.h> 69 #include <sys/errno.h> 70 #include <sys/rndsource.h> 71 #include <sys/kernel.h> 72 #include <sys/systm.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <net/if_dl.h> 77 #include <net/if_ether.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <net/bpf.h> 81 82 #include <dev/fdt/fdtvar.h> 83 #include <dev/acpi/acpireg.h> 84 #include <dev/acpi/acpivar.h> 85 #include <dev/acpi/acpi_intr.h> 86 87 /* SC2A11 register block */ 88 #define SWRESET 0x104 89 #define COMINIT 0x120 90 #define INTRST 0x200 91 #define IRQ_RX (1U<<1) 92 #define IRQ_TX (1U<<0) 93 #define INTREN 0x204 94 #define INTR_SET 0x234 95 #define INTR_CLR 0x238 96 #define TXINTST 0x400 97 #define TXINTEN 0x404 98 #define TXINT_SET 0x428 99 #define TXINT_CLR 0x42c 100 #define TXI_NTOWNR (1U<<17) 101 #define TXI_TR_ERR (1U<<16) 102 #define TXI_TXDONE (1U<<15) 103 #define TXI_TMREXP (1U<<14) 104 #define RXINTST 0x440 105 #define RXINTEN 0x444 106 #define RXINT_SET 0x468 107 #define RXINT_CLR 0x46c 108 #define RXI_RC_ERR (1U<<16) 109 #define RXI_PKTCNT (1U<<15) 110 #define RXI_TMREXP (1U<<14) 111 #define TXTIMER 0x41c 112 #define RXTIMER 0x45c 113 #define TXCOUNT 0x410 114 #define RXCOUNT 0x454 115 #define H2MENG 0x210 /* DMAC host2media ucode port */ 116 #define M2HENG 0x21c /* DMAC media2host ucode port */ 117 #define PKTENG 0x0d0 /* packet engine ucode port */ 118 #define HWVER0 0x22c 119 #define HWVER1 0x230 120 121 #define MACSTAT 0x1024 /* gmac status */ 122 #define MACDATA 0x11c0 /* gmac rd/wr data */ 123 #define MACCMD 0x11c4 /* gmac operation */ 124 #define CMD_IOWR (1U<<28) /* write op */ 125 #define CMD_BUSY (1U<<31) /* busy bit */ 126 #define DESCENG_INIT 0x11fc 127 #define DESCENG_SRST 0x1204 128 129 /* GMAC register block. use mac_write()/mac_read() to handle */ 130 #define GMACMCR 0x0000 /* MAC configuration */ 131 #define MCR_IBN (1U<<30) /* */ 132 #define MCR_CST (1U<<25) /* strip CRC */ 133 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 134 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 135 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 136 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 137 #define MCR_USEFDX (1U<<11) /* force full duplex */ 138 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 139 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 140 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 141 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 142 #define _MCR_FDX 0x0000280c /* XXX TBD */ 143 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 144 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 145 #define AFR_RA (1U<<31) /* receive block all on */ 146 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 147 #define AFR_SAF (1U<<9) /* source address filter */ 148 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 149 #define AFR_PCF (3U<<6) /* */ 150 #define AFR_RB (1U<<5) /* reject broadcast frame */ 151 #define AFR_AM (1U<<4) /* accept all multicast frame */ 152 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 153 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 154 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 155 #define AFR_PM (1U<<0) /* run promisc mode */ 156 #define _AFR 0x80000001 /* XXX TBD */ 157 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 158 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 159 #define GMACGAR 0x0010 /* MDIO operation */ 160 #define GAR_PHY (11) /* mii phy 15:11 */ 161 #define GAR_REG (6) /* mii reg 10:6 */ 162 #define GAR_CTL (2) /* control 5:2 */ 163 #define GAR_IOWR (1U<<1) /* MDIO write op */ 164 #define GAR_BUSY (1U) /* busy bit */ 165 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 166 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 167 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 168 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 169 #define GMACVTAG 0x001c /* VLAN tag control */ 170 #define GMACIMPL 0x0020 /* implementation number XX.YY */ 171 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 172 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 173 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */ 174 #define GMACMAL(i) ((i)*8+0x44) 175 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 176 /* 3 link up detected 177 * 2:1 resovled speed 178 * 0 2.5Mhz (10Mbps) 179 * 1 25Mhz (100bps) 180 * 2 125Mhz (1000Mbps) 181 * 1 full duplex detected */ 182 183 #define GMACMHT0 0x0500 /* multicast hash table 0 - 7 */ 184 #define GMACMHT(i) ((i)*4+0x500) 185 #define GMACVHT 0x0588 /* VLAN tag hash */ 186 #define GMACAMAH(i) ((i)*8+0x800) /* supplimental MAC addr 16-127 */ 187 #define GMACAMAL(i) ((i)*8+0x804) 188 #define GMACEVCNT(i) ((i)*4+0x114) /* event counter 0x114~284 */ 189 #define GMACEVCTL 0x0100 /* clear event counter registers */ 190 191 #define GMACBMR 0x1000 /* DMA bus mode control 192 * 24 4PBL 193 * 22:17 RPBL 194 * 16 fix burst 195 * 15:14 priority between Rx and Tx 196 * 3 rxtx ratio 41 197 * 2 rxtx ratio 31 198 * 1 rxtx ratio 21 199 * 0 rxtx ratio 11 200 * 13:8 PBL possible DMA burst len 201 * 0 reset op. self clear 202 */ 203 #define _BMR 0x00412080 /* XXX TBD */ 204 #define _BMR0 0x00020181 /* XXX TBD */ 205 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 206 #define GMACTDS 0x1004 /* write any to resume tdes */ 207 #define GMACRDS 0x1008 /* write any to resume rdes */ 208 #define GMACRDLAR 0x100c /* rdes base address 32bit paddr */ 209 #define _RDLAR 0x18000 /* XXX TBD system SRAM with CC ? */ 210 #define GMACTDLAR 0x1010 /* tdes base address 32bit paddr */ 211 #define _TDLAR 0x1c000 /* XXX TBD system SRAM with CC ? */ 212 #define GMACOMR 0x1018 /* DMA operation */ 213 #define OMR_TXE (1U<<13) /* start Tx DMA engine, 0 to stop */ 214 #define OMR_RXE (1U<<1) /* start Rx DMA engine, 0 to stop */ 215 216 /* descriptor format definition */ 217 struct tdes { 218 uint32_t t0, t1, t2, t3; 219 }; 220 221 struct rdes { 222 uint32_t r0, r1, r2, r3; 223 }; 224 225 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 226 #define T0_EOD (1U<<30) /* end of descriptor array */ 227 #define T0_DRID (24) /* 29:24 D-RID */ 228 #define T0_PT (1U<<21) /* 23:21 PT */ 229 #define T0_TRID (16) /* 20:16 T-RID */ 230 #define T0_FS (1U<<9) /* first segment of frame */ 231 #define T0_LS (1U<<8) /* last segment of frame */ 232 #define T0_CSUM (1U<<7) /* enable check sum offload */ 233 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 234 #define T0_TRS (1U<<4) /* 5:4 TRS */ 235 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 236 /* T1 segment address 63:32 */ 237 /* T2 segment address 31:0 */ 238 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 239 #define R0_OWN (1U<<31) /* desc is empty */ 240 #define R0_EOD (1U<<30) /* end of descriptor array */ 241 #define R0_SRID (24) /* 29:24 S-RID */ 242 #define R0_FR (1U<<23) /* FR */ 243 #define R0_ER (1U<<21) /* Rx error indication */ 244 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 245 #define R0_TDRID (14) /* 15:14 TD-RID */ 246 #define R0_FS (1U<<9) /* first segment of frame */ 247 #define R0_LS (1U<<8) /* last segment of frame */ 248 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 249 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 250 /* R1 frame address 63:32 */ 251 /* R2 frame address 31:0 */ 252 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 253 254 #define MD_NTXSEGS 16 /* fixed */ 255 #define MD_TXQUEUELEN 16 /* tunable */ 256 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 257 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 258 #define MD_NTXDESC (MD_TXQUEUELEN * MD_NTXSEGS) 259 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 260 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 261 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 262 263 #define MD_NRXDESC 64 /* tunable */ 264 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 265 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 266 267 #define SCX_INIT_RXDESC(sc, x) \ 268 do { \ 269 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 270 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 271 struct mbuf *__m = __rxs->rxs_mbuf; \ 272 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 273 __m->m_data = __m->m_ext.ext_buf; \ 274 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 275 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 276 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 277 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 278 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 279 } while (/*CONSTCOND*/0) 280 281 struct control_data { 282 struct tdes cd_txdescs[MD_NTXDESC]; 283 struct rdes cd_rxdescs[MD_NRXDESC]; 284 }; 285 #define SCX_CDOFF(x) offsetof(struct control_data, x) 286 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 287 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 288 289 struct scx_txsoft { 290 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 291 bus_dmamap_t txs_dmamap; /* our DMA map */ 292 int txs_firstdesc; /* first descriptor in packet */ 293 int txs_lastdesc; /* last descriptor in packet */ 294 int txs_ndesc; /* # of descriptors used */ 295 }; 296 297 struct scx_rxsoft { 298 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 299 bus_dmamap_t rxs_dmamap; /* our DMA map */ 300 }; 301 302 struct scx_softc { 303 device_t sc_dev; /* generic device information */ 304 bus_space_tag_t sc_st; /* bus space tag */ 305 bus_space_handle_t sc_sh; /* bus space handle */ 306 bus_size_t sc_sz; /* csr map size */ 307 bus_space_handle_t sc_eesh; /* eeprom section handle */ 308 bus_size_t sc_eesz; /* eeprom map size */ 309 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 310 bus_dma_tag_t sc_dmat32; 311 struct ethercom sc_ethercom; /* Ethernet common data */ 312 struct mii_data sc_mii; /* MII */ 313 callout_t sc_tick_ch; /* PHY monitor callout */ 314 bus_dma_segment_t sc_seg; /* descriptor store seg */ 315 int sc_nseg; /* descriptor store nseg */ 316 void *sc_ih; /* interrupt cookie */ 317 int sc_phy_id; /* PHY address */ 318 int sc_flowflags; /* 802.3x PAUSE flow control */ 319 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 320 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 321 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 322 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 323 int sc_phandle; /* fdt phandle */ 324 uint64_t sc_freq; 325 326 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 327 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 328 329 struct control_data *sc_control_data; 330 #define sc_txdescs sc_control_data->cd_txdescs 331 #define sc_rxdescs sc_control_data->cd_rxdescs 332 333 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 334 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 335 int sc_txfree; /* number of free Tx descriptors */ 336 int sc_txnext; /* next ready Tx descriptor */ 337 int sc_txsfree; /* number of free Tx jobs */ 338 int sc_txsnext; /* next ready Tx job */ 339 int sc_txsdirty; /* dirty Tx jobs */ 340 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 341 342 krndsource_t rnd_source; /* random source */ 343 }; 344 345 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 346 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 347 348 #define SCX_CDTXSYNC(sc, x, n, ops) \ 349 do { \ 350 int __x, __n; \ 351 \ 352 __x = (x); \ 353 __n = (n); \ 354 \ 355 /* If it will wrap around, sync to the end of the ring. */ \ 356 if ((__x + __n) > MD_NTXDESC) { \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 359 (MD_NTXDESC - __x), (ops)); \ 360 __n -= (MD_NTXDESC - __x); \ 361 __x = 0; \ 362 } \ 363 \ 364 /* Now sync whatever is left. */ \ 365 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 366 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 367 } while (/*CONSTCOND*/0) 368 369 #define SCX_CDRXSYNC(sc, x, ops) \ 370 do { \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 373 } while (/*CONSTCOND*/0) 374 375 static int scx_fdt_match(device_t, cfdata_t, void *); 376 static void scx_fdt_attach(device_t, device_t, void *); 377 static int scx_acpi_match(device_t, cfdata_t, void *); 378 static void scx_acpi_attach(device_t, device_t, void *); 379 380 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 381 scx_fdt_match, scx_fdt_attach, NULL, NULL); 382 383 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 384 scx_acpi_match, scx_acpi_attach, NULL, NULL); 385 386 static void scx_attach_i(struct scx_softc *); 387 static void scx_reset(struct scx_softc *); 388 static int scx_init(struct ifnet *); 389 static void scx_start(struct ifnet *); 390 static void scx_stop(struct ifnet *, int); 391 static void scx_watchdog(struct ifnet *); 392 static int scx_ioctl(struct ifnet *, u_long, void *); 393 static void scx_set_rcvfilt(struct scx_softc *); 394 static int scx_ifmedia_upd(struct ifnet *); 395 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 396 static void mii_statchg(struct ifnet *); 397 static void phy_tick(void *); 398 static int mii_readreg(device_t, int, int, uint16_t *); 399 static int mii_writereg(device_t, int, int, uint16_t); 400 static int scx_intr(void *); 401 static void txreap(struct scx_softc *); 402 static void rxintr(struct scx_softc *); 403 static int add_rxbuf(struct scx_softc *, int); 404 405 static int spin_waitfor(struct scx_softc *, int, int); 406 static int mac_read(struct scx_softc *, int); 407 static void mac_write(struct scx_softc *, int, int); 408 static void loaducode(struct scx_softc *); 409 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 410 static int get_mdioclk(uint32_t); 411 412 #define CSR_READ(sc,off) \ 413 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 414 #define CSR_WRITE(sc,off,val) \ 415 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 416 #define EE_READ(sc,off) \ 417 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 418 419 static int 420 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 421 { 422 static const char * compatible[] = { 423 "socionext,synquacer-netsec", 424 NULL 425 }; 426 struct fdt_attach_args * const faa = aux; 427 428 return of_match_compatible(faa->faa_phandle, compatible); 429 } 430 431 static void 432 scx_fdt_attach(device_t parent, device_t self, void *aux) 433 { 434 struct scx_softc * const sc = device_private(self); 435 struct fdt_attach_args * const faa = aux; 436 const int phandle = faa->faa_phandle; 437 bus_space_tag_t bst = faa->faa_bst; 438 bus_space_handle_t bsh; 439 bus_space_handle_t eebsh; 440 bus_addr_t addr[2]; 441 bus_size_t size[2]; 442 char intrstr[128]; 443 const char *phy_mode; 444 445 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 446 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 447 aprint_error(": unable to map device csr\n"); 448 return; 449 } 450 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 451 aprint_error(": failed to decode interrupt\n"); 452 goto fail; 453 } 454 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 455 NOT_MP_SAFE, scx_intr, sc); 456 if (sc->sc_ih == NULL) { 457 aprint_error_dev(self, "couldn't establish interrupt\n"); 458 goto fail; 459 } 460 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 461 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 462 aprint_error(": unable to map device eeprom\n"); 463 goto fail; 464 } 465 466 467 aprint_naive("\n"); 468 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 469 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 470 471 sc->sc_dev = self; 472 sc->sc_st = bst; 473 sc->sc_sh = bsh; 474 sc->sc_sz = size[0]; 475 sc->sc_eesh = eebsh; 476 sc->sc_eesz = size[1]; 477 sc->sc_dmat = faa->faa_dmat; 478 sc->sc_phandle = phandle; 479 480 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 481 if (phy_mode == NULL) 482 aprint_error(": missing 'phy-mode' property\n"); 483 sc->sc_100mii = (phy_mode != NULL && strcmp(phy_mode, "rgmii") != 0); 484 sc->sc_phy_id = 7; /* XXX */ 485 sc->sc_freq = 250 * 1000 * 1000; /* XXX */ 486 aprint_normal_dev(self, 487 "phy mode %s, phy id %d, freq %ld\n", phy_mode, sc->sc_phy_id, sc->sc_freq); 488 489 scx_attach_i(sc); 490 return; 491 fail: 492 if (sc->sc_eesz) 493 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 494 if (sc->sc_sz) 495 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 496 return; 497 } 498 499 static int 500 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 501 { 502 static const char * compatible[] = { 503 "SCX0001", 504 NULL 505 }; 506 struct acpi_attach_args *aa = aux; 507 508 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 509 return 0; 510 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 511 } 512 513 static void 514 scx_acpi_attach(device_t parent, device_t self, void *aux) 515 { 516 struct scx_softc * const sc = device_private(self); 517 struct acpi_attach_args * const aa = aux; 518 ACPI_HANDLE handle = aa->aa_node->ad_handle; 519 bus_space_tag_t bst = aa->aa_memt; 520 bus_space_handle_t bsh, eebsh; 521 struct acpi_resources res; 522 struct acpi_mem *mem; 523 struct acpi_irq *irq; 524 char *phy_mode; 525 ACPI_INTEGER acpi_phy, acpi_freq; 526 ACPI_STATUS rv; 527 528 rv = acpi_resource_parse(self, handle, "_CRS", 529 &res, &acpi_resource_parse_ops_default); 530 if (ACPI_FAILURE(rv)) 531 return; 532 mem = acpi_res_mem(&res, 0); 533 irq = acpi_res_irq(&res, 0); 534 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 535 aprint_error(": incomplete csr resources\n"); 536 return; 537 } 538 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 539 aprint_error(": couldn't map registers\n"); 540 return; 541 } 542 sc->sc_sz = mem->ar_length; 543 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 544 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 545 if (sc->sc_ih == NULL) { 546 aprint_error_dev(self, "couldn't establish interrupt\n"); 547 goto fail; 548 } 549 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 550 if (mem == NULL || mem->ar_length == 0) { 551 aprint_error(": incomplete eeprom resources\n"); 552 goto fail; 553 } 554 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 555 aprint_error(": couldn't map registers\n"); 556 goto fail; 557 } 558 sc->sc_eesz = mem->ar_length; 559 560 rv = acpi_dsd_string(handle, "phy-mode", &phy_mode); 561 if (ACPI_FAILURE(rv)) { 562 aprint_error(": missing 'phy-mode' property\n"); 563 phy_mode = NULL; 564 } 565 rv = acpi_dsd_integer(handle, "phy-channel", &acpi_phy); 566 if (ACPI_FAILURE(rv)) 567 acpi_phy = 31; 568 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 569 &acpi_freq); 570 if (ACPI_FAILURE(rv)) 571 acpi_freq = 999; 572 573 aprint_naive("\n"); 574 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 575 576 sc->sc_dev = self; 577 sc->sc_st = bst; 578 sc->sc_sh = bsh; 579 sc->sc_eesh = eebsh; 580 sc->sc_dmat = aa->aa_dmat64; 581 sc->sc_dmat32 = aa->aa_dmat; /* descriptor needs dma32 */ 582 583 aprint_normal_dev(self, 584 "phy mode %s, phy id %d, freq %ld\n", phy_mode, (int)acpi_phy, acpi_freq); 585 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 586 sc->sc_freq = acpi_freq; 587 sc->sc_phy_id = (int)acpi_phy; 588 589 scx_attach_i(sc); 590 591 acpi_resource_cleanup(&res); 592 return; 593 fail: 594 if (sc->sc_eesz > 0) 595 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 596 if (sc->sc_sz > 0) 597 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 598 acpi_resource_cleanup(&res); 599 return; 600 } 601 602 static void 603 scx_attach_i(struct scx_softc *sc) 604 { 605 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 606 struct mii_data * const mii = &sc->sc_mii; 607 struct ifmedia * const ifm = &mii->mii_media; 608 uint32_t hwver; 609 uint8_t enaddr[ETHER_ADDR_LEN]; 610 bus_dma_segment_t seg; 611 uint32_t csr; 612 int i, nseg, error = 0; 613 614 hwver = CSR_READ(sc, HWVER1); 615 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 616 enaddr[0] = csr >> 24; 617 enaddr[1] = csr >> 16; 618 enaddr[2] = csr >> 8; 619 enaddr[3] = csr; 620 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 621 enaddr[4] = csr >> 24; 622 enaddr[5] = csr >> 16; 623 csr = mac_read(sc, GMACIMPL); 624 625 aprint_normal_dev(sc->sc_dev, 626 "Socionext NetSec GbE hw %d.%d impl 0x%x\n", 627 hwver >> 16, hwver & 0xffff, csr); 628 aprint_normal_dev(sc->sc_dev, 629 "Ethernet address %s\n", ether_sprintf(enaddr)); 630 631 sc->sc_phy_id = MII_PHY_ANY; 632 sc->sc_mdclk = get_mdioclk(sc->sc_freq); /* 5:2 clk control */ 633 sc->sc_mdclk = 5; /* XXX */ 634 aprint_normal_dev(sc->sc_dev, "using %d for mdclk\n", sc->sc_mdclk); 635 sc->sc_mdclk <<= 2; 636 637 sc->sc_flowflags = 0; 638 639 if (sc->sc_ucodeloaded == 0) 640 loaducode(sc); 641 642 mii->mii_ifp = ifp; 643 mii->mii_readreg = mii_readreg; 644 mii->mii_writereg = mii_writereg; 645 mii->mii_statchg = mii_statchg; 646 647 sc->sc_ethercom.ec_mii = mii; 648 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 649 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 650 MII_OFFSET_ANY, MIIF_DOPAUSE); 651 if (LIST_FIRST(&mii->mii_phys) == NULL) { 652 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 653 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 654 } else 655 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 656 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 657 658 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 659 ifp->if_softc = sc; 660 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 661 ifp->if_ioctl = scx_ioctl; 662 ifp->if_start = scx_start; 663 ifp->if_watchdog = scx_watchdog; 664 ifp->if_init = scx_init; 665 ifp->if_stop = scx_stop; 666 IFQ_SET_READY(&ifp->if_snd); 667 668 if_attach(ifp); 669 if_deferred_start_init(ifp, NULL); 670 ether_ifattach(ifp, enaddr); 671 672 callout_init(&sc->sc_tick_ch, 0); 673 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 674 675 /* 676 * Allocate the control data structures, and create and load the 677 * DMA map for it. 678 */ 679 error = bus_dmamem_alloc(sc->sc_dmat32, 680 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 681 if (error != 0) { 682 aprint_error_dev(sc->sc_dev, 683 "unable to allocate control data, error = %d\n", error); 684 goto fail_0; 685 } 686 error = bus_dmamem_map(sc->sc_dmat32, &seg, nseg, 687 sizeof(struct control_data), (void **)&sc->sc_control_data, 688 BUS_DMA_COHERENT); 689 if (error != 0) { 690 aprint_error_dev(sc->sc_dev, 691 "unable to map control data, error = %d\n", error); 692 goto fail_1; 693 } 694 error = bus_dmamap_create(sc->sc_dmat32, 695 sizeof(struct control_data), 1, 696 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 697 if (error != 0) { 698 aprint_error_dev(sc->sc_dev, 699 "unable to create control data DMA map, " 700 "error = %d\n", error); 701 goto fail_2; 702 } 703 error = bus_dmamap_load(sc->sc_dmat32, sc->sc_cddmamap, 704 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 705 if (error != 0) { 706 aprint_error_dev(sc->sc_dev, 707 "unable to load control data DMA map, error = %d\n", 708 error); 709 goto fail_3; 710 } 711 for (i = 0; i < MD_TXQUEUELEN; i++) { 712 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 713 MD_NTXSEGS, MCLBYTES, 0, 0, 714 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 715 aprint_error_dev(sc->sc_dev, 716 "unable to create tx DMA map %d, error = %d\n", 717 i, error); 718 goto fail_4; 719 } 720 } 721 for (i = 0; i < MD_NRXDESC; i++) { 722 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 723 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 724 aprint_error_dev(sc->sc_dev, 725 "unable to create rx DMA map %d, error = %d\n", 726 i, error); 727 goto fail_5; 728 } 729 sc->sc_rxsoft[i].rxs_mbuf = NULL; 730 } 731 sc->sc_seg = seg; 732 sc->sc_nseg = nseg; 733 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 734 735 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 736 pmf_class_network_register(sc->sc_dev, ifp); 737 else 738 aprint_error_dev(sc->sc_dev, 739 "couldn't establish power handler\n"); 740 741 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 742 RND_TYPE_NET, RND_FLAG_DEFAULT); 743 744 return; 745 746 fail_5: 747 for (i = 0; i < MD_NRXDESC; i++) { 748 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 749 bus_dmamap_destroy(sc->sc_dmat, 750 sc->sc_rxsoft[i].rxs_dmamap); 751 } 752 fail_4: 753 for (i = 0; i < MD_TXQUEUELEN; i++) { 754 if (sc->sc_txsoft[i].txs_dmamap != NULL) 755 bus_dmamap_destroy(sc->sc_dmat, 756 sc->sc_txsoft[i].txs_dmamap); 757 } 758 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 759 fail_3: 760 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 761 fail_2: 762 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 763 sizeof(struct control_data)); 764 fail_1: 765 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 766 fail_0: 767 if (sc->sc_phandle) 768 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 769 else 770 acpi_intr_disestablish(sc->sc_ih); 771 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 772 return; 773 } 774 775 static void 776 scx_reset(struct scx_softc *sc) 777 { 778 779 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 780 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 781 782 CSR_WRITE(sc, DESCENG_SRST, 1); 783 CSR_WRITE(sc, DESCENG_INIT, 1); 784 mac_write(sc, GMACBMR, _BMR); 785 mac_write(sc, GMACRDLAR, _RDLAR); 786 mac_write(sc, GMACTDLAR, _TDLAR); 787 mac_write(sc, GMACAFR, _AFR); 788 mac_write(sc, GMACEVCTL, 1); 789 } 790 791 static int 792 scx_init(struct ifnet *ifp) 793 { 794 struct scx_softc *sc = ifp->if_softc; 795 const uint8_t *ea = CLLADDR(ifp->if_sadl); 796 uint32_t csr; 797 int i; 798 799 /* Cancel pending I/O. */ 800 scx_stop(ifp, 0); 801 802 /* Reset the chip to a known state. */ 803 scx_reset(sc); 804 805 /* set my address in perfect match slot 0 */ 806 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 807 mac_write(sc, GMACMAL0, csr); 808 csr = (ea[5] << 8) | ea[4]; 809 mac_write(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 810 811 /* accept multicast frame or run promisc mode */ 812 scx_set_rcvfilt(sc); 813 814 (void)scx_ifmedia_upd(ifp); 815 816 /* build sane Tx */ 817 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 818 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 819 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 820 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 821 sc->sc_txfree = MD_NTXDESC; 822 sc->sc_txnext = 0; 823 for (i = 0; i < MD_TXQUEUELEN; i++) 824 sc->sc_txsoft[i].txs_mbuf = NULL; 825 sc->sc_txsfree = MD_TXQUEUELEN; 826 sc->sc_txsnext = 0; 827 sc->sc_txsdirty = 0; 828 829 /* load Rx descriptors with fresh mbuf */ 830 for (i = 0; i < MD_NRXDESC; i++) 831 (void)add_rxbuf(sc, i); 832 sc->sc_rxptr = 0; 833 834 /* XXX 32 bit paddr XXX hand Tx/Rx rings to HW XXX */ 835 mac_write(sc, GMACTDLAR, SCX_CDTXADDR(sc, 0)); 836 mac_write(sc, GMACRDLAR, SCX_CDRXADDR(sc, 0)); 837 838 /* kick to start GMAC engine */ 839 CSR_WRITE(sc, RXINT_CLR, ~0); 840 CSR_WRITE(sc, TXINT_CLR, ~0); 841 csr = mac_read(sc, GMACOMR); 842 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 843 844 ifp->if_flags |= IFF_RUNNING; 845 ifp->if_flags &= ~IFF_OACTIVE; 846 847 /* start one second timer */ 848 callout_schedule(&sc->sc_tick_ch, hz); 849 850 return 0; 851 } 852 853 static void 854 scx_stop(struct ifnet *ifp, int disable) 855 { 856 struct scx_softc *sc = ifp->if_softc; 857 858 /* Stop the one second clock. */ 859 callout_stop(&sc->sc_tick_ch); 860 861 /* Down the MII. */ 862 mii_down(&sc->sc_mii); 863 864 /* Mark the interface down and cancel the watchdog timer. */ 865 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 866 ifp->if_timer = 0; 867 } 868 869 static void 870 scx_watchdog(struct ifnet *ifp) 871 { 872 struct scx_softc *sc = ifp->if_softc; 873 874 /* 875 * Since we're not interrupting every packet, sweep 876 * up before we report an error. 877 */ 878 txreap(sc); 879 880 if (sc->sc_txfree != MD_NTXDESC) { 881 aprint_error_dev(sc->sc_dev, 882 "device timeout (txfree %d txsfree %d txnext %d)\n", 883 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 884 if_statinc(ifp, if_oerrors); 885 886 /* Reset the interface. */ 887 scx_init(ifp); 888 } 889 890 scx_start(ifp); 891 } 892 893 static int 894 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 895 { 896 struct scx_softc *sc = ifp->if_softc; 897 struct ifreq *ifr = (struct ifreq *)data; 898 struct ifmedia *ifm; 899 int s, error; 900 901 s = splnet(); 902 903 switch (cmd) { 904 case SIOCSIFMEDIA: 905 /* Flow control requires full-duplex mode. */ 906 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 907 (ifr->ifr_media & IFM_FDX) == 0) 908 ifr->ifr_media &= ~IFM_ETH_FMASK; 909 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 910 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 911 /* We can do both TXPAUSE and RXPAUSE. */ 912 ifr->ifr_media |= 913 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 914 } 915 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 916 } 917 ifm = &sc->sc_mii.mii_media; 918 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 919 break; 920 default: 921 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 922 break; 923 924 error = 0; 925 926 if (cmd == SIOCSIFCAP) 927 error = (*ifp->if_init)(ifp); 928 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 929 ; 930 else if (ifp->if_flags & IFF_RUNNING) { 931 /* 932 * Multicast list has changed; set the hardware filter 933 * accordingly. 934 */ 935 scx_set_rcvfilt(sc); 936 } 937 break; 938 } 939 940 splx(s); 941 return error; 942 } 943 944 static void 945 scx_set_rcvfilt(struct scx_softc *sc) 946 { 947 struct ethercom * const ec = &sc->sc_ethercom; 948 struct ifnet * const ifp = &ec->ec_if; 949 struct ether_multistep step; 950 struct ether_multi *enm; 951 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 952 uint32_t csr, crc; 953 int i; 954 955 csr = mac_read(sc, GMACAFR); 956 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 957 mac_write(sc, GMACAFR, csr); 958 959 ETHER_LOCK(ec); 960 if (ifp->if_flags & IFF_PROMISC) { 961 ec->ec_flags |= ETHER_F_ALLMULTI; 962 ETHER_UNLOCK(ec); 963 goto update; 964 } 965 ec->ec_flags &= ~ETHER_F_ALLMULTI; 966 967 /* clear 15 entry supplimental perfect match filter */ 968 for (i = 1; i < 16; i++) 969 mac_write(sc, GMACMAH(i), 0); 970 /* build 256 bit multicast hash filter */ 971 memset(mchash, 0, sizeof(mchash)); 972 crc = 0; 973 974 ETHER_FIRST_MULTI(step, ec, enm); 975 i = 1; /* slot 0 is occupied */ 976 while (enm != NULL) { 977 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 978 /* 979 * We must listen to a range of multicast addresses. 980 * For now, just accept all multicasts, rather than 981 * trying to set only those filter bits needed to match 982 * the range. (At this time, the only use of address 983 * ranges is for IP multicast routing, for which the 984 * range is big enough to require all bits set.) 985 */ 986 ec->ec_flags |= ETHER_F_ALLMULTI; 987 ETHER_UNLOCK(ec); 988 goto update; 989 } 990 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 991 if (i < 16) { 992 /* use 15 entry perfect match filter */ 993 uint32_t addr; 994 uint8_t *ep = enm->enm_addrlo; 995 addr = (ep[3] << 24) | (ep[2] << 16) 996 | (ep[1] << 8) | ep[0]; 997 mac_write(sc, GMACMAL(i), addr); 998 addr = (ep[5] << 8) | ep[4]; 999 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1000 } else { 1001 /* use hash table when too many */ 1002 /* bit_reserve_32(~crc) !? */ 1003 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1004 /* 3(31:29) 5(28:24) bit sampling */ 1005 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 1006 } 1007 ETHER_NEXT_MULTI(step, enm); 1008 i++; 1009 } 1010 ETHER_UNLOCK(ec); 1011 1012 if (crc) 1013 csr |= AFR_MHTE; 1014 for (i = 0; i < __arraycount(mchash); i++) 1015 mac_write(sc, GMACMHT(i), mchash[i]); 1016 mac_write(sc, GMACAFR, csr); 1017 return; 1018 1019 update: 1020 /* With PM or AM, MHTE/MHT0-7 are never consulted. really? */ 1021 if (ifp->if_flags & IFF_PROMISC) 1022 csr |= AFR_PM; /* run promisc. mode */ 1023 else 1024 csr |= AFR_AM; /* accept all multicast */ 1025 mac_write(sc, GMACAFR, csr); 1026 return; 1027 } 1028 1029 static int 1030 scx_ifmedia_upd(struct ifnet *ifp) 1031 { 1032 struct scx_softc *sc = ifp->if_softc; 1033 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1034 1035 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 1036 ; /* restart AN */ 1037 ; /* enable AN */ 1038 ; /* advertise flow control pause */ 1039 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 1040 } else { 1041 #if 1 /* XXX not sure to belong here XXX */ 1042 uint32_t mcr = mac_read(sc, GMACMCR); 1043 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 1044 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1045 else { 1046 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX 1047 && sc->sc_100mii) 1048 mcr |= MCR_SPD100; 1049 mcr |= MCR_USEMII; 1050 } 1051 if (ifm->ifm_cur->ifm_media & IFM_FDX) 1052 mcr |= MCR_USEFDX; 1053 mcr |= MCR_CST | MCR_JE; 1054 if (sc->sc_100mii == 0) 1055 mcr |= MCR_IBN; 1056 mac_write(sc, GMACMCR, mcr); 1057 #endif 1058 } 1059 return 0; 1060 } 1061 1062 static void 1063 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1064 { 1065 struct scx_softc *sc = ifp->if_softc; 1066 struct mii_data *mii = &sc->sc_mii; 1067 1068 mii_pollstat(mii); 1069 ifmr->ifm_status = mii->mii_media_status; 1070 ifmr->ifm_active = sc->sc_flowflags | 1071 (mii->mii_media_active & ~IFM_ETH_FMASK); 1072 } 1073 1074 void 1075 mii_statchg(struct ifnet *ifp) 1076 { 1077 struct scx_softc *sc = ifp->if_softc; 1078 struct mii_data *mii = &sc->sc_mii; 1079 uint32_t fcr; 1080 #if 1 1081 /* decode MIISR register value */ 1082 uint32_t miisr = mac_read(sc, GMACMIISR); 1083 int spd = (miisr >> 1) & 03; 1084 printf("MII link status (0x%x) %s", 1085 miisr, (miisr & 8) ? "up" : "down"); 1086 if (miisr & 8) { 1087 printf(" spd%d", (spd == 2) ? 1000 : (spd == 1) ? 100 : 10); 1088 if (miisr & 1) 1089 printf(",full-duplex"); 1090 } 1091 printf("\n"); 1092 #endif 1093 /* Get flow control negotiation result. */ 1094 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1095 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1096 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1097 1098 /* Adjust PAUSE flow control. */ 1099 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1100 if (mii->mii_media_active & IFM_FDX) { 1101 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1102 fcr |= FCR_TFE; 1103 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1104 fcr |= FCR_RFE; 1105 } 1106 mac_write(sc, GMACFCR, fcr); 1107 1108 printf("%ctxfe, %crxfe\n", 1109 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1110 } 1111 1112 static void 1113 phy_tick(void *arg) 1114 { 1115 struct scx_softc *sc = arg; 1116 struct mii_data *mii = &sc->sc_mii; 1117 int s; 1118 1119 s = splnet(); 1120 mii_tick(mii); 1121 splx(s); 1122 1123 callout_schedule(&sc->sc_tick_ch, hz); 1124 } 1125 1126 static int 1127 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1128 { 1129 struct scx_softc *sc = device_private(self); 1130 uint32_t miia; 1131 int error; 1132 1133 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1134 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1135 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1136 if (error) 1137 return error; 1138 *val = mac_read(sc, GMACGDR); 1139 return 0; 1140 } 1141 1142 static int 1143 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1144 { 1145 struct scx_softc *sc = device_private(self); 1146 uint32_t miia; 1147 uint16_t dummy; 1148 int error; 1149 1150 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1151 mac_write(sc, GMACGDR, val); 1152 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1153 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1154 if (error) 1155 return error; 1156 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1157 return 0; 1158 } 1159 1160 static void 1161 scx_start(struct ifnet *ifp) 1162 { 1163 struct scx_softc *sc = ifp->if_softc; 1164 struct mbuf *m0, *m; 1165 struct scx_txsoft *txs; 1166 bus_dmamap_t dmamap; 1167 int error, nexttx, lasttx, ofree, seg; 1168 uint32_t tdes0; 1169 1170 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1171 return; 1172 1173 /* Remember the previous number of free descriptors. */ 1174 ofree = sc->sc_txfree; 1175 1176 /* 1177 * Loop through the send queue, setting up transmit descriptors 1178 * until we drain the queue, or use up all available transmit 1179 * descriptors. 1180 */ 1181 for (;;) { 1182 IFQ_POLL(&ifp->if_snd, m0); 1183 if (m0 == NULL) 1184 break; 1185 1186 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1187 txreap(sc); 1188 if (sc->sc_txsfree == 0) 1189 break; 1190 } 1191 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1192 dmamap = txs->txs_dmamap; 1193 1194 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1195 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1196 if (error) { 1197 if (error == EFBIG) { 1198 aprint_error_dev(sc->sc_dev, 1199 "Tx packet consumes too many " 1200 "DMA segments, dropping...\n"); 1201 IFQ_DEQUEUE(&ifp->if_snd, m0); 1202 m_freem(m0); 1203 continue; 1204 } 1205 /* Short on resources, just stop for now. */ 1206 break; 1207 } 1208 1209 if (dmamap->dm_nsegs > sc->sc_txfree) { 1210 /* 1211 * Not enough free descriptors to transmit this 1212 * packet. We haven't committed anything yet, 1213 * so just unload the DMA map, put the packet 1214 * back on the queue, and punt. Notify the upper 1215 * layer that there are not more slots left. 1216 */ 1217 ifp->if_flags |= IFF_OACTIVE; 1218 bus_dmamap_unload(sc->sc_dmat, dmamap); 1219 break; 1220 } 1221 1222 IFQ_DEQUEUE(&ifp->if_snd, m0); 1223 1224 /* 1225 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1226 */ 1227 1228 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1229 BUS_DMASYNC_PREWRITE); 1230 1231 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1232 lasttx = -1; 1233 for (nexttx = sc->sc_txnext, seg = 0; 1234 seg < dmamap->dm_nsegs; 1235 seg++, nexttx = MD_NEXTTX(nexttx)) { 1236 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1237 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1238 /* 1239 * If this is the first descriptor we're 1240 * enqueueing, don't set the OWN bit just 1241 * yet. That could cause a race condition. 1242 * We'll do it below. 1243 */ 1244 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1245 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1246 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1247 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1248 (15 << T0_TRID) | T0_PT | 1249 sc->sc_t0coso | T0_TRS; 1250 tdes0 = T0_OWN; /* 2nd and other segments */ 1251 lasttx = nexttx; 1252 } 1253 /* 1254 * Outgoing NFS mbuf must be unloaded when Tx completed. 1255 * Without T1_IC NFS mbuf is left unack'ed for excessive 1256 * time and NFS stops to proceed until scx_watchdog() 1257 * calls txreap() to reclaim the unack'ed mbuf. 1258 * It's painful to traverse every mbuf chain to determine 1259 * whether someone is waiting for Tx completion. 1260 */ 1261 m = m0; 1262 do { 1263 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1264 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1265 break; 1266 } 1267 } while ((m = m->m_next) != NULL); 1268 1269 /* Write deferred 1st segment T0_OWN at the final stage */ 1270 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1271 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1272 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1273 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1274 1275 /* Tell DMA start transmit */ 1276 mac_write(sc, GMACTDS, 1); 1277 1278 txs->txs_mbuf = m0; 1279 txs->txs_firstdesc = sc->sc_txnext; 1280 txs->txs_lastdesc = lasttx; 1281 txs->txs_ndesc = dmamap->dm_nsegs; 1282 1283 sc->sc_txfree -= txs->txs_ndesc; 1284 sc->sc_txnext = nexttx; 1285 sc->sc_txsfree--; 1286 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1287 /* 1288 * Pass the packet to any BPF listeners. 1289 */ 1290 bpf_mtap(ifp, m0, BPF_D_OUT); 1291 } 1292 1293 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1294 /* No more slots left; notify upper layer. */ 1295 ifp->if_flags |= IFF_OACTIVE; 1296 } 1297 if (sc->sc_txfree != ofree) { 1298 /* Set a watchdog timer in case the chip flakes out. */ 1299 ifp->if_timer = 5; 1300 } 1301 } 1302 1303 static int 1304 scx_intr(void *arg) 1305 { 1306 struct scx_softc *sc = arg; 1307 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1308 1309 (void)ifp; 1310 /* XXX decode interrupt cause to pick isr() XXX */ 1311 rxintr(sc); 1312 txreap(sc); 1313 return 1; 1314 } 1315 1316 static void 1317 txreap(struct scx_softc *sc) 1318 { 1319 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1320 struct scx_txsoft *txs; 1321 uint32_t txstat; 1322 int i; 1323 1324 ifp->if_flags &= ~IFF_OACTIVE; 1325 1326 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1327 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1328 txs = &sc->sc_txsoft[i]; 1329 1330 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1331 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1332 1333 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1334 if (txstat & T0_OWN) /* desc is still in use */ 1335 break; 1336 1337 /* There is no way to tell transmission status per frame */ 1338 1339 if_statinc(ifp, if_opackets); 1340 1341 sc->sc_txfree += txs->txs_ndesc; 1342 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1343 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1344 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1345 m_freem(txs->txs_mbuf); 1346 txs->txs_mbuf = NULL; 1347 } 1348 sc->sc_txsdirty = i; 1349 if (sc->sc_txsfree == MD_TXQUEUELEN) 1350 ifp->if_timer = 0; 1351 } 1352 1353 static void 1354 rxintr(struct scx_softc *sc) 1355 { 1356 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1357 struct scx_rxsoft *rxs; 1358 struct mbuf *m; 1359 uint32_t rxstat; 1360 int i, len; 1361 1362 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1363 rxs = &sc->sc_rxsoft[i]; 1364 1365 SCX_CDRXSYNC(sc, i, 1366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1367 1368 rxstat = sc->sc_rxdescs[i].r0; 1369 if (rxstat & R0_OWN) /* desc is left empty */ 1370 break; 1371 1372 /* R0_FS | R0_LS must have been marked for this desc */ 1373 1374 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1375 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1376 1377 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1378 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1379 m = rxs->rxs_mbuf; 1380 1381 if (add_rxbuf(sc, i) != 0) { 1382 if_statinc(ifp, if_ierrors); 1383 SCX_INIT_RXDESC(sc, i); 1384 bus_dmamap_sync(sc->sc_dmat, 1385 rxs->rxs_dmamap, 0, 1386 rxs->rxs_dmamap->dm_mapsize, 1387 BUS_DMASYNC_PREREAD); 1388 continue; 1389 } 1390 1391 m_set_rcvif(m, ifp); 1392 m->m_pkthdr.len = m->m_len = len; 1393 1394 if (rxstat & R0_CSUM) { 1395 uint32_t csum = M_CSUM_IPv4; 1396 if (rxstat & R0_CERR) 1397 csum |= M_CSUM_IPv4_BAD; 1398 m->m_pkthdr.csum_flags |= csum; 1399 } 1400 if_percpuq_enqueue(ifp->if_percpuq, m); 1401 } 1402 sc->sc_rxptr = i; 1403 } 1404 1405 static int 1406 add_rxbuf(struct scx_softc *sc, int i) 1407 { 1408 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1409 struct mbuf *m; 1410 int error; 1411 1412 MGETHDR(m, M_DONTWAIT, MT_DATA); 1413 if (m == NULL) 1414 return ENOBUFS; 1415 1416 MCLGET(m, M_DONTWAIT); 1417 if ((m->m_flags & M_EXT) == 0) { 1418 m_freem(m); 1419 return ENOBUFS; 1420 } 1421 1422 if (rxs->rxs_mbuf != NULL) 1423 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1424 1425 rxs->rxs_mbuf = m; 1426 1427 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1428 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1429 if (error) { 1430 aprint_error_dev(sc->sc_dev, 1431 "can't load rx DMA map %d, error = %d\n", i, error); 1432 panic("add_rxbuf"); 1433 } 1434 1435 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1436 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1437 SCX_INIT_RXDESC(sc, i); 1438 1439 return 0; 1440 } 1441 1442 static int 1443 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1444 { 1445 int val, loop; 1446 1447 val = CSR_READ(sc, reg); 1448 if ((val & exist) == 0) 1449 return 0; 1450 loop = 3000; 1451 do { 1452 DELAY(10); 1453 val = CSR_READ(sc, reg); 1454 } while (--loop > 0 && (val & exist)); 1455 return (loop > 0) ? 0 : ETIMEDOUT; 1456 } 1457 1458 /* GMAC register needs to use indirect rd/wr via memory mapped registers. */ 1459 1460 static int 1461 mac_read(struct scx_softc *sc, int reg) 1462 { 1463 1464 CSR_WRITE(sc, MACCMD, reg); 1465 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1466 return CSR_READ(sc, MACDATA); 1467 } 1468 1469 static void 1470 mac_write(struct scx_softc *sc, int reg, int val) 1471 { 1472 1473 CSR_WRITE(sc, MACDATA, val); 1474 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1475 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1476 } 1477 1478 /* 1479 * 3 independent uengines exist * to process host2media, media2host and 1480 * packet data flows. 1481 */ 1482 static void 1483 loaducode(struct scx_softc *sc) 1484 { 1485 uint32_t up, lo, sz; 1486 uint64_t addr; 1487 1488 sc->sc_ucodeloaded = 1; 1489 1490 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1491 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1492 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1493 sz *= 4; 1494 addr = ((uint64_t)up << 32) | lo; 1495 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1496 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1497 1498 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1499 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1500 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1501 sz *= 4; 1502 addr = ((uint64_t)up << 32) | lo; 1503 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1504 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1505 1506 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1507 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1508 sz *= 4; 1509 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1510 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1511 } 1512 1513 static void 1514 injectucode(struct scx_softc *sc, int port, 1515 bus_addr_t addr, bus_size_t size) 1516 { 1517 bus_space_handle_t bsh; 1518 bus_size_t off; 1519 uint32_t ucode; 1520 1521 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1522 aprint_error_dev(sc->sc_dev, 1523 "eeprom map failure for ucode port 0x%x\n", port); 1524 return; 1525 } 1526 for (off = 0; off < size; off += 4) { 1527 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1528 CSR_WRITE(sc, port, ucode); 1529 } 1530 bus_space_unmap(sc->sc_st, bsh, size); 1531 } 1532 1533 /* bit selection to determine MDIO speed */ 1534 1535 static int 1536 get_mdioclk(uint32_t freq) 1537 { 1538 1539 const struct { 1540 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 1541 } mdioclk[] = { 1542 { 35, 2 }, /* 25-35 MHz */ 1543 { 60, 3 }, /* 35-60 MHz */ 1544 { 100, 0 }, /* 60-100 MHz */ 1545 { 150, 1 }, /* 100-150 MHz */ 1546 { 250, 4 }, /* 150-250 MHz */ 1547 { 300, 5 }, /* 250-300 MHz */ 1548 }; 1549 int i; 1550 1551 freq /= 1000 * 1000; 1552 /* convert MDIO clk to a divisor value */ 1553 if (freq < mdioclk[0].freq) 1554 return mdioclk[0].bit; 1555 for (i = 1; i < __arraycount(mdioclk); i++) { 1556 if (freq < mdioclk[i].freq) 1557 return mdioclk[i-1].bit; 1558 } 1559 return mdioclk[__arraycount(mdioclk) - 1].bit << GAR_CTL; 1560 } 1561
Indexes created Fri Sep 26 20:09:58 GMT 2025