if_scx.c revision 1.15
1 /* $NetBSD: if_scx.c,v 1.15 2020/03/26 01:05:26 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 16 or even 128. 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~16 are for supplimental MAC addresses. Independently enabled for 47 * use. Good to catch multicast. Byte-wise selective match available. 48 * Use the mask to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - 16~128 might be exact match without byte-mask. 50 * - The size of multicast hash filter store is unknown. Might be 256 bit. 51 * - Socionext/Linaro "NetSec" code makes many cut shorts. Some constants 52 * are left unexplained. The values should be handled via external 53 * controls like FDT descriptions. Fortunately, Intel/Altera CycloneV PDFs 54 * describe every detail of "such the instance of" DW EMAC IP and 55 * most of them are likely applicable to SC2A11 GbE. 56 * - DW EMAC implmentation (0x20) is 0x10.0x36 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.15 2020/03/26 01:05:26 nisimura Exp $"); 61 62 #include <sys/param.h> 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 #include <sys/device.h> 66 #include <sys/callout.h> 67 #include <sys/mbuf.h> 68 #include <sys/malloc.h> 69 #include <sys/errno.h> 70 #include <sys/rndsource.h> 71 #include <sys/kernel.h> 72 #include <sys/systm.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <net/if_dl.h> 77 #include <net/if_ether.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <net/bpf.h> 81 82 #include <dev/fdt/fdtvar.h> 83 #include <dev/acpi/acpireg.h> 84 #include <dev/acpi/acpivar.h> 85 #include <dev/acpi/acpi_intr.h> 86 87 /* SC2A11 register block */ 88 #define SWRESET 0x104 89 #define COMINIT 0x120 90 #define INTRST 0x200 91 #define IRQ_RX (1U<<1) 92 #define IRQ_TX (1U<<0) 93 #define INTREN 0x204 94 #define INTR_SET 0x234 95 #define INTR_CLR 0x238 96 #define TXINTST 0x400 97 #define TXINTEN 0x404 98 #define TXINT_SET 0x428 99 #define TXINT_CLR 0x42c 100 #define TXI_NTOWNR (1U<<17) 101 #define TXI_TR_ERR (1U<<16) 102 #define TXI_TXDONE (1U<<15) 103 #define TXI_TMREXP (1U<<14) 104 #define RXINTST 0x440 105 #define RXINTEN 0x444 106 #define RXINT_SET 0x468 107 #define RXINT_CLR 0x46c 108 #define RXI_RC_ERR (1U<<16) 109 #define RXI_PKTCNT (1U<<15) 110 #define RXI_TMREXP (1U<<14) 111 #define TXTIMER 0x41c 112 #define RXTIMER 0x45c 113 #define TXCOUNT 0x410 114 #define RXCOUNT 0x454 115 #define H2MENG 0x210 /* DMAC host2media ucode port */ 116 #define M2HENG 0x21c /* DMAC media2host ucode port */ 117 #define PKTENG 0x0d0 /* packet engine ucode port */ 118 #define HWVER0 0x22c 119 #define HWVER1 0x230 120 121 #define MACSTAT 0x1024 /* gmac status */ 122 #define MACDATA 0x11c0 /* gmac rd/wr data */ 123 #define MACCMD 0x11c4 /* gmac operation */ 124 #define CMD_IOWR (1U<<28) /* write op */ 125 #define CMD_BUSY (1U<<31) /* busy bit */ 126 #define DESCENG_INIT 0x11fc 127 #define DESCENG_SRST 0x1204 128 129 /* GMAC register block. use mac_write()/mac_read() to handle */ 130 #define GMACMCR 0x0000 /* MAC configuration */ 131 #define MCR_IBN (1U<<30) /* */ 132 #define MCR_CST (1U<<25) /* strip CRC */ 133 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 134 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 135 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 136 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 137 #define MCR_USEFDX (1U<<11) /* force full duplex */ 138 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 139 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 140 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 141 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 142 #define _MCR_FDX 0x0000280c /* XXX TBD */ 143 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 144 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 145 #define AFR_RA (1U<<31) /* receive block all on */ 146 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 147 #define AFR_SAF (1U<<9) /* source address filter */ 148 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 149 #define AFR_PCF (3U<<6) /* */ 150 #define AFR_RB (1U<<5) /* reject broadcast frame */ 151 #define AFR_AM (1U<<4) /* accept all multicast frame */ 152 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 153 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 154 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 155 #define AFR_PM (1U<<0) /* run promisc mode */ 156 #define _AFR 0x80000001 /* XXX TBD */ 157 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 158 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 159 #define GMACGAR 0x0010 /* MDIO operation */ 160 #define GAR_PHY (11) /* mii phy 15:11 */ 161 #define GAR_REG (6) /* mii reg 10:6 */ 162 #define GAR_CTL (2) /* control 5:2 */ 163 #define GAR_IOWR (1U<<1) /* MDIO write op */ 164 #define GAR_BUSY (1U) /* busy bit */ 165 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 166 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 167 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 168 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 169 #define GMACVTAG 0x001c /* VLAN tag control */ 170 #define GMACIMPL 0x0020 /* implementation number XX.YY */ 171 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 172 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 173 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */ 174 #define GMACMAL(i) ((i)*8+0x44) 175 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 176 /* 3 link up detected 177 * 2:1 resovled speed 178 * 0 2.5Mhz (10Mbps) 179 * 1 25Mhz (100Mbps) 180 * 2 125Mhz (1000Mbps) 181 * 1 full duplex detected */ 182 183 #define GMACMHT0 0x0500 /* multicast hash table 0 - 7 */ 184 #define GMACMHT(i) ((i)*4+0x500) 185 #define GMACVHT 0x0588 /* VLAN tag hash */ 186 #define GMACAMAH(i) ((i)*8+0x800) /* supplimental MAC addr 16-127 */ 187 #define GMACAMAL(i) ((i)*8+0x804) 188 #define GMACEVCNT(i) ((i)*4+0x114) /* event counter 0x114~284 */ 189 #define GMACEVCTL 0x0100 /* clear event counter registers */ 190 191 #define GMACBMR 0x1000 /* DMA bus mode control 192 * 24 4PBL 193 * 22:17 RPBL 194 * 16 fix burst 195 * 15:14 priority between Rx and Tx 196 * 3 rxtx ratio 41 197 * 2 rxtx ratio 31 198 * 1 rxtx ratio 21 199 * 0 rxtx ratio 11 200 * 13:8 PBL possible DMA burst len 201 * 0 reset op. self clear 202 */ 203 #define _BMR 0x00412080 /* XXX TBD */ 204 #define _BMR0 0x00020181 /* XXX TBD */ 205 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 206 #define GMACTDS 0x1004 /* write any to resume tdes */ 207 #define GMACRDS 0x1008 /* write any to resume rdes */ 208 #define GMACRDLAR 0x100c /* rdes base address 32bit paddr */ 209 #define _RDLAR 0x18000 /* XXX TBD system SRAM with CC ? */ 210 #define GMACTDLAR 0x1010 /* tdes base address 32bit paddr */ 211 #define _TDLAR 0x1c000 /* XXX TBD system SRAM with CC ? */ 212 #define GMACOMR 0x1018 /* DMA operation */ 213 #define OMR_TXE (1U<<13) /* start Tx DMA engine, 0 to stop */ 214 #define OMR_RXE (1U<<1) /* start Rx DMA engine, 0 to stop */ 215 216 /* descriptor format definition */ 217 struct tdes { 218 uint32_t t0, t1, t2, t3; 219 }; 220 221 struct rdes { 222 uint32_t r0, r1, r2, r3; 223 }; 224 225 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 226 #define T0_EOD (1U<<30) /* end of descriptor array */ 227 #define T0_DRID (24) /* 29:24 D-RID */ 228 #define T0_PT (1U<<21) /* 23:21 PT */ 229 #define T0_TRID (16) /* 20:16 T-RID */ 230 #define T0_FS (1U<<9) /* first segment of frame */ 231 #define T0_LS (1U<<8) /* last segment of frame */ 232 #define T0_CSUM (1U<<7) /* enable check sum offload */ 233 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 234 #define T0_TRS (1U<<4) /* 5:4 TRS */ 235 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 236 /* T1 segment address 63:32 */ 237 /* T2 segment address 31:0 */ 238 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 239 #define R0_OWN (1U<<31) /* desc is empty */ 240 #define R0_EOD (1U<<30) /* end of descriptor array */ 241 #define R0_SRID (24) /* 29:24 S-RID */ 242 #define R0_FR (1U<<23) /* FR */ 243 #define R0_ER (1U<<21) /* Rx error indication */ 244 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 245 #define R0_TDRID (14) /* 15:14 TD-RID */ 246 #define R0_FS (1U<<9) /* first segment of frame */ 247 #define R0_LS (1U<<8) /* last segment of frame */ 248 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 249 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 250 /* R1 frame address 63:32 */ 251 /* R2 frame address 31:0 */ 252 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 253 254 #define MD_NTXSEGS 16 /* fixed */ 255 #define MD_TXQUEUELEN 16 /* tunable */ 256 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 257 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 258 #define MD_NTXDESC (MD_TXQUEUELEN * MD_NTXSEGS) 259 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 260 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 261 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 262 263 #define MD_NRXDESC 64 /* tunable */ 264 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 265 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 266 267 #define SCX_INIT_RXDESC(sc, x) \ 268 do { \ 269 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 270 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 271 struct mbuf *__m = __rxs->rxs_mbuf; \ 272 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 273 __m->m_data = __m->m_ext.ext_buf; \ 274 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 275 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 276 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 277 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 278 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 279 } while (/*CONSTCOND*/0) 280 281 struct control_data { 282 struct tdes cd_txdescs[MD_NTXDESC]; 283 struct rdes cd_rxdescs[MD_NRXDESC]; 284 }; 285 #define SCX_CDOFF(x) offsetof(struct control_data, x) 286 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 287 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 288 289 struct scx_txsoft { 290 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 291 bus_dmamap_t txs_dmamap; /* our DMA map */ 292 int txs_firstdesc; /* first descriptor in packet */ 293 int txs_lastdesc; /* last descriptor in packet */ 294 int txs_ndesc; /* # of descriptors used */ 295 }; 296 297 struct scx_rxsoft { 298 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 299 bus_dmamap_t rxs_dmamap; /* our DMA map */ 300 }; 301 302 struct scx_softc { 303 device_t sc_dev; /* generic device information */ 304 bus_space_tag_t sc_st; /* bus space tag */ 305 bus_space_handle_t sc_sh; /* bus space handle */ 306 bus_size_t sc_sz; /* csr map size */ 307 bus_space_handle_t sc_eesh; /* eeprom section handle */ 308 bus_size_t sc_eesz; /* eeprom map size */ 309 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 310 bus_dma_tag_t sc_dmat32; 311 struct ethercom sc_ethercom; /* Ethernet common data */ 312 struct mii_data sc_mii; /* MII */ 313 callout_t sc_tick_ch; /* PHY monitor callout */ 314 bus_dma_segment_t sc_seg; /* descriptor store seg */ 315 int sc_nseg; /* descriptor store nseg */ 316 void *sc_ih; /* interrupt cookie */ 317 int sc_phy_id; /* PHY address */ 318 int sc_flowflags; /* 802.3x PAUSE flow control */ 319 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 320 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 321 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 322 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 323 int sc_phandle; /* fdt phandle */ 324 uint64_t sc_freq; 325 326 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 327 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 328 329 struct control_data *sc_control_data; 330 #define sc_txdescs sc_control_data->cd_txdescs 331 #define sc_rxdescs sc_control_data->cd_rxdescs 332 333 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 334 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 335 int sc_txfree; /* number of free Tx descriptors */ 336 int sc_txnext; /* next ready Tx descriptor */ 337 int sc_txsfree; /* number of free Tx jobs */ 338 int sc_txsnext; /* next ready Tx job */ 339 int sc_txsdirty; /* dirty Tx jobs */ 340 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 341 342 krndsource_t rnd_source; /* random source */ 343 }; 344 345 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 346 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 347 348 #define SCX_CDTXSYNC(sc, x, n, ops) \ 349 do { \ 350 int __x, __n; \ 351 \ 352 __x = (x); \ 353 __n = (n); \ 354 \ 355 /* If it will wrap around, sync to the end of the ring. */ \ 356 if ((__x + __n) > MD_NTXDESC) { \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 359 (MD_NTXDESC - __x), (ops)); \ 360 __n -= (MD_NTXDESC - __x); \ 361 __x = 0; \ 362 } \ 363 \ 364 /* Now sync whatever is left. */ \ 365 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 366 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 367 } while (/*CONSTCOND*/0) 368 369 #define SCX_CDRXSYNC(sc, x, ops) \ 370 do { \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 373 } while (/*CONSTCOND*/0) 374 375 static int scx_fdt_match(device_t, cfdata_t, void *); 376 static void scx_fdt_attach(device_t, device_t, void *); 377 static int scx_acpi_match(device_t, cfdata_t, void *); 378 static void scx_acpi_attach(device_t, device_t, void *); 379 380 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 381 scx_fdt_match, scx_fdt_attach, NULL, NULL); 382 383 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 384 scx_acpi_match, scx_acpi_attach, NULL, NULL); 385 386 static void scx_attach_i(struct scx_softc *); 387 static void scx_reset(struct scx_softc *); 388 static int scx_init(struct ifnet *); 389 static void scx_start(struct ifnet *); 390 static void scx_stop(struct ifnet *, int); 391 static void scx_watchdog(struct ifnet *); 392 static int scx_ioctl(struct ifnet *, u_long, void *); 393 static void scx_set_rcvfilt(struct scx_softc *); 394 static int scx_ifmedia_upd(struct ifnet *); 395 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 396 static void mii_statchg(struct ifnet *); 397 static void phy_tick(void *); 398 static int mii_readreg(device_t, int, int, uint16_t *); 399 static int mii_writereg(device_t, int, int, uint16_t); 400 static int scx_intr(void *); 401 static void txreap(struct scx_softc *); 402 static void rxintr(struct scx_softc *); 403 static int add_rxbuf(struct scx_softc *, int); 404 405 static int spin_waitfor(struct scx_softc *, int, int); 406 static int mac_read(struct scx_softc *, int); 407 static void mac_write(struct scx_softc *, int, int); 408 static void loaducode(struct scx_softc *); 409 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 410 static int get_mdioclk(uint32_t); 411 412 #define CSR_READ(sc,off) \ 413 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 414 #define CSR_WRITE(sc,off,val) \ 415 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 416 #define EE_READ(sc,off) \ 417 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 418 419 static int 420 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 421 { 422 static const char * compatible[] = { 423 "socionext,synquacer-netsec", 424 NULL 425 }; 426 struct fdt_attach_args * const faa = aux; 427 428 return of_match_compatible(faa->faa_phandle, compatible); 429 } 430 431 static void 432 scx_fdt_attach(device_t parent, device_t self, void *aux) 433 { 434 struct scx_softc * const sc = device_private(self); 435 struct fdt_attach_args * const faa = aux; 436 const int phandle = faa->faa_phandle; 437 bus_space_tag_t bst = faa->faa_bst; 438 bus_space_handle_t bsh; 439 bus_space_handle_t eebsh; 440 bus_addr_t addr[2]; 441 bus_size_t size[2]; 442 char intrstr[128]; 443 const char *phy_mode; 444 445 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 446 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 447 aprint_error(": unable to map device csr\n"); 448 return; 449 } 450 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 451 aprint_error(": failed to decode interrupt\n"); 452 goto fail; 453 } 454 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 455 NOT_MP_SAFE, scx_intr, sc); 456 if (sc->sc_ih == NULL) { 457 aprint_error_dev(self, "couldn't establish interrupt\n"); 458 goto fail; 459 } 460 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 461 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 462 aprint_error(": unable to map device eeprom\n"); 463 goto fail; 464 } 465 466 aprint_naive("\n"); 467 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 468 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 469 470 sc->sc_dev = self; 471 sc->sc_st = bst; 472 sc->sc_sh = bsh; 473 sc->sc_sz = size[0]; 474 sc->sc_eesh = eebsh; 475 sc->sc_eesz = size[1]; 476 sc->sc_dmat = faa->faa_dmat; 477 sc->sc_dmat32 = faa->faa_dmat; /* XXX */ 478 sc->sc_phandle = phandle; 479 480 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 481 if (phy_mode == NULL) 482 aprint_error(": missing 'phy-mode' property\n"); 483 sc->sc_100mii = (phy_mode != NULL && strcmp(phy_mode, "rgmii") != 0); 484 sc->sc_phy_id = 7; /* XXX */ 485 sc->sc_freq = 250 * 1000 * 1000; /* XXX */ 486 aprint_normal_dev(self, 487 "phy mode %s, phy id %d, freq %ld\n", phy_mode, sc->sc_phy_id, sc->sc_freq); 488 489 scx_attach_i(sc); 490 return; 491 fail: 492 if (sc->sc_eesz) 493 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 494 if (sc->sc_sz) 495 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 496 return; 497 } 498 499 static int 500 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 501 { 502 static const char * compatible[] = { 503 "SCX0001", 504 NULL 505 }; 506 struct acpi_attach_args *aa = aux; 507 508 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 509 return 0; 510 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 511 } 512 513 static void 514 scx_acpi_attach(device_t parent, device_t self, void *aux) 515 { 516 struct scx_softc * const sc = device_private(self); 517 struct acpi_attach_args * const aa = aux; 518 ACPI_HANDLE handle = aa->aa_node->ad_handle; 519 bus_space_tag_t bst = aa->aa_memt; 520 bus_space_handle_t bsh, eebsh; 521 struct acpi_resources res; 522 struct acpi_mem *mem; 523 struct acpi_irq *irq; 524 char *phy_mode; 525 ACPI_INTEGER acpi_phy, acpi_freq; 526 ACPI_STATUS rv; 527 528 rv = acpi_resource_parse(self, handle, "_CRS", 529 &res, &acpi_resource_parse_ops_default); 530 if (ACPI_FAILURE(rv)) 531 return; 532 mem = acpi_res_mem(&res, 0); 533 irq = acpi_res_irq(&res, 0); 534 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 535 aprint_error(": incomplete csr resources\n"); 536 return; 537 } 538 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 539 aprint_error(": couldn't map registers\n"); 540 return; 541 } 542 sc->sc_sz = mem->ar_length; 543 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 544 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 545 if (sc->sc_ih == NULL) { 546 aprint_error_dev(self, "couldn't establish interrupt\n"); 547 goto fail; 548 } 549 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 550 if (mem == NULL || mem->ar_length == 0) { 551 aprint_error(": incomplete eeprom resources\n"); 552 goto fail; 553 } 554 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 555 aprint_error(": couldn't map registers\n"); 556 goto fail; 557 } 558 sc->sc_eesz = mem->ar_length; 559 560 rv = acpi_dsd_string(handle, "phy-mode", &phy_mode); 561 if (ACPI_FAILURE(rv)) { 562 aprint_error(": missing 'phy-mode' property\n"); 563 phy_mode = NULL; 564 } 565 rv = acpi_dsd_integer(handle, "phy-channel", &acpi_phy); 566 if (ACPI_FAILURE(rv)) 567 acpi_phy = 31; 568 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 569 &acpi_freq); 570 if (ACPI_FAILURE(rv)) 571 acpi_freq = 999; 572 573 aprint_naive("\n"); 574 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 575 576 sc->sc_dev = self; 577 sc->sc_st = bst; 578 sc->sc_sh = bsh; 579 sc->sc_eesh = eebsh; 580 sc->sc_dmat = aa->aa_dmat64; 581 sc->sc_dmat32 = aa->aa_dmat; /* descriptor needs dma32 */ 582 583 aprint_normal_dev(self, 584 "phy mode %s, phy id %d, freq %ld\n", phy_mode, (int)acpi_phy, acpi_freq); 585 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 586 sc->sc_phy_id = (int)acpi_phy; 587 sc->sc_freq = acpi_freq; 588 589 scx_attach_i(sc); 590 591 acpi_resource_cleanup(&res); 592 return; 593 fail: 594 if (sc->sc_eesz > 0) 595 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 596 if (sc->sc_sz > 0) 597 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 598 acpi_resource_cleanup(&res); 599 return; 600 } 601 602 static void 603 scx_attach_i(struct scx_softc *sc) 604 { 605 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 606 struct mii_data * const mii = &sc->sc_mii; 607 struct ifmedia * const ifm = &mii->mii_media; 608 uint32_t hwver, dwimp; 609 uint8_t enaddr[ETHER_ADDR_LEN]; 610 bus_dma_segment_t seg; 611 uint32_t csr; 612 int i, nseg, error = 0; 613 614 hwver = CSR_READ(sc, HWVER1); /* Socionext HW */ 615 /* stored in big endian order */ 616 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 617 enaddr[0] = csr >> 24; 618 enaddr[1] = csr >> 16; 619 enaddr[2] = csr >> 8; 620 enaddr[3] = csr; 621 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 622 enaddr[4] = csr >> 24; 623 enaddr[5] = csr >> 16; 624 dwimp = mac_read(sc, GMACIMPL); /* DW EMAC XX.YY */ 625 626 aprint_normal_dev(sc->sc_dev, 627 "Socionext NetSec GbE hw %d.%d impl 0x%x\n", 628 hwver >> 16, hwver & 0xffff, dwimp); 629 aprint_normal_dev(sc->sc_dev, 630 "Ethernet address %s\n", ether_sprintf(enaddr)); 631 632 sc->sc_phy_id = MII_PHY_ANY; 633 sc->sc_mdclk = get_mdioclk(sc->sc_freq); /* 5:2 clk control */ 634 sc->sc_mdclk = 5; /* XXX */ 635 aprint_normal_dev(sc->sc_dev, "using %d for mdclk\n", sc->sc_mdclk); 636 sc->sc_mdclk <<= 2; 637 638 sc->sc_flowflags = 0; 639 640 if (sc->sc_ucodeloaded == 0) 641 loaducode(sc); 642 643 mii->mii_ifp = ifp; 644 mii->mii_readreg = mii_readreg; 645 mii->mii_writereg = mii_writereg; 646 mii->mii_statchg = mii_statchg; 647 648 sc->sc_ethercom.ec_mii = mii; 649 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 650 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 651 MII_OFFSET_ANY, MIIF_DOPAUSE); 652 if (LIST_FIRST(&mii->mii_phys) == NULL) { 653 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 654 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 655 } else 656 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 657 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 658 659 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 660 ifp->if_softc = sc; 661 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 662 ifp->if_ioctl = scx_ioctl; 663 ifp->if_start = scx_start; 664 ifp->if_watchdog = scx_watchdog; 665 ifp->if_init = scx_init; 666 ifp->if_stop = scx_stop; 667 IFQ_SET_READY(&ifp->if_snd); 668 669 if_attach(ifp); 670 if_deferred_start_init(ifp, NULL); 671 ether_ifattach(ifp, enaddr); 672 673 callout_init(&sc->sc_tick_ch, 0); 674 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 675 676 /* 677 * Allocate the control data structures, and create and load the 678 * DMA map for it. 679 */ 680 error = bus_dmamem_alloc(sc->sc_dmat32, 681 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 682 if (error != 0) { 683 aprint_error_dev(sc->sc_dev, 684 "unable to allocate control data, error = %d\n", error); 685 goto fail_0; 686 } 687 error = bus_dmamem_map(sc->sc_dmat32, &seg, nseg, 688 sizeof(struct control_data), (void **)&sc->sc_control_data, 689 BUS_DMA_COHERENT); 690 if (error != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "unable to map control data, error = %d\n", error); 693 goto fail_1; 694 } 695 error = bus_dmamap_create(sc->sc_dmat32, 696 sizeof(struct control_data), 1, 697 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 698 if (error != 0) { 699 aprint_error_dev(sc->sc_dev, 700 "unable to create control data DMA map, " 701 "error = %d\n", error); 702 goto fail_2; 703 } 704 error = bus_dmamap_load(sc->sc_dmat32, sc->sc_cddmamap, 705 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 706 if (error != 0) { 707 aprint_error_dev(sc->sc_dev, 708 "unable to load control data DMA map, error = %d\n", 709 error); 710 goto fail_3; 711 } 712 for (i = 0; i < MD_TXQUEUELEN; i++) { 713 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 714 MD_NTXSEGS, MCLBYTES, 0, 0, 715 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 716 aprint_error_dev(sc->sc_dev, 717 "unable to create tx DMA map %d, error = %d\n", 718 i, error); 719 goto fail_4; 720 } 721 } 722 for (i = 0; i < MD_NRXDESC; i++) { 723 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 724 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 725 aprint_error_dev(sc->sc_dev, 726 "unable to create rx DMA map %d, error = %d\n", 727 i, error); 728 goto fail_5; 729 } 730 sc->sc_rxsoft[i].rxs_mbuf = NULL; 731 } 732 sc->sc_seg = seg; 733 sc->sc_nseg = nseg; 734 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 735 736 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 737 pmf_class_network_register(sc->sc_dev, ifp); 738 else 739 aprint_error_dev(sc->sc_dev, 740 "couldn't establish power handler\n"); 741 742 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 743 RND_TYPE_NET, RND_FLAG_DEFAULT); 744 745 return; 746 747 fail_5: 748 for (i = 0; i < MD_NRXDESC; i++) { 749 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 750 bus_dmamap_destroy(sc->sc_dmat, 751 sc->sc_rxsoft[i].rxs_dmamap); 752 } 753 fail_4: 754 for (i = 0; i < MD_TXQUEUELEN; i++) { 755 if (sc->sc_txsoft[i].txs_dmamap != NULL) 756 bus_dmamap_destroy(sc->sc_dmat, 757 sc->sc_txsoft[i].txs_dmamap); 758 } 759 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 760 fail_3: 761 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 762 fail_2: 763 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 764 sizeof(struct control_data)); 765 fail_1: 766 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 767 fail_0: 768 if (sc->sc_phandle) 769 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 770 else 771 acpi_intr_disestablish(sc->sc_ih); 772 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 773 return; 774 } 775 776 static void 777 scx_reset(struct scx_softc *sc) 778 { 779 780 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 781 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 782 783 CSR_WRITE(sc, DESCENG_SRST, 1); 784 CSR_WRITE(sc, DESCENG_INIT, 1); 785 mac_write(sc, GMACBMR, _BMR); 786 mac_write(sc, GMACRDLAR, _RDLAR); 787 mac_write(sc, GMACTDLAR, _TDLAR); 788 mac_write(sc, GMACAFR, _AFR); 789 mac_write(sc, GMACEVCTL, 1); 790 } 791 792 static int 793 scx_init(struct ifnet *ifp) 794 { 795 struct scx_softc *sc = ifp->if_softc; 796 const uint8_t *ea = CLLADDR(ifp->if_sadl); 797 uint32_t csr; 798 int i; 799 800 /* Cancel pending I/O. */ 801 scx_stop(ifp, 0); 802 803 /* Reset the chip to a known state. */ 804 scx_reset(sc); 805 806 /* set my address in perfect match slot 0. little endin order */ 807 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 808 mac_write(sc, GMACMAL0, csr); 809 csr = (ea[5] << 8) | ea[4]; 810 mac_write(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 811 812 /* accept multicast frame or run promisc mode */ 813 scx_set_rcvfilt(sc); 814 815 (void)scx_ifmedia_upd(ifp); 816 817 /* build sane Tx */ 818 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 819 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 820 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 821 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 822 sc->sc_txfree = MD_NTXDESC; 823 sc->sc_txnext = 0; 824 for (i = 0; i < MD_TXQUEUELEN; i++) 825 sc->sc_txsoft[i].txs_mbuf = NULL; 826 sc->sc_txsfree = MD_TXQUEUELEN; 827 sc->sc_txsnext = 0; 828 sc->sc_txsdirty = 0; 829 830 /* load Rx descriptors with fresh mbuf */ 831 for (i = 0; i < MD_NRXDESC; i++) 832 (void)add_rxbuf(sc, i); 833 sc->sc_rxptr = 0; 834 835 /* XXX 32 bit paddr XXX hand Tx/Rx rings to HW XXX */ 836 mac_write(sc, GMACTDLAR, SCX_CDTXADDR(sc, 0)); 837 mac_write(sc, GMACRDLAR, SCX_CDRXADDR(sc, 0)); 838 839 /* kick to start GMAC engine */ 840 CSR_WRITE(sc, RXINT_CLR, ~0); 841 CSR_WRITE(sc, TXINT_CLR, ~0); 842 csr = mac_read(sc, GMACOMR); 843 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 844 845 ifp->if_flags |= IFF_RUNNING; 846 ifp->if_flags &= ~IFF_OACTIVE; 847 848 /* start one second timer */ 849 callout_schedule(&sc->sc_tick_ch, hz); 850 851 return 0; 852 } 853 854 static void 855 scx_stop(struct ifnet *ifp, int disable) 856 { 857 struct scx_softc *sc = ifp->if_softc; 858 859 /* Stop the one second clock. */ 860 callout_stop(&sc->sc_tick_ch); 861 862 /* Down the MII. */ 863 mii_down(&sc->sc_mii); 864 865 /* Mark the interface down and cancel the watchdog timer. */ 866 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 867 ifp->if_timer = 0; 868 } 869 870 static void 871 scx_watchdog(struct ifnet *ifp) 872 { 873 struct scx_softc *sc = ifp->if_softc; 874 875 /* 876 * Since we're not interrupting every packet, sweep 877 * up before we report an error. 878 */ 879 txreap(sc); 880 881 if (sc->sc_txfree != MD_NTXDESC) { 882 aprint_error_dev(sc->sc_dev, 883 "device timeout (txfree %d txsfree %d txnext %d)\n", 884 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 885 if_statinc(ifp, if_oerrors); 886 887 /* Reset the interface. */ 888 scx_init(ifp); 889 } 890 891 scx_start(ifp); 892 } 893 894 static int 895 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 896 { 897 struct scx_softc *sc = ifp->if_softc; 898 struct ifreq *ifr = (struct ifreq *)data; 899 struct ifmedia *ifm; 900 int s, error; 901 902 s = splnet(); 903 904 switch (cmd) { 905 case SIOCSIFMEDIA: 906 /* Flow control requires full-duplex mode. */ 907 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 908 (ifr->ifr_media & IFM_FDX) == 0) 909 ifr->ifr_media &= ~IFM_ETH_FMASK; 910 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 911 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 912 /* We can do both TXPAUSE and RXPAUSE. */ 913 ifr->ifr_media |= 914 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 915 } 916 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 917 } 918 ifm = &sc->sc_mii.mii_media; 919 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 920 break; 921 default: 922 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 923 break; 924 925 error = 0; 926 927 if (cmd == SIOCSIFCAP) 928 error = (*ifp->if_init)(ifp); 929 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 930 ; 931 else if (ifp->if_flags & IFF_RUNNING) { 932 /* 933 * Multicast list has changed; set the hardware filter 934 * accordingly. 935 */ 936 scx_set_rcvfilt(sc); 937 } 938 break; 939 } 940 941 splx(s); 942 return error; 943 } 944 945 static void 946 scx_set_rcvfilt(struct scx_softc *sc) 947 { 948 struct ethercom * const ec = &sc->sc_ethercom; 949 struct ifnet * const ifp = &ec->ec_if; 950 struct ether_multistep step; 951 struct ether_multi *enm; 952 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 953 uint32_t csr, crc; 954 int i; 955 956 csr = mac_read(sc, GMACAFR); 957 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 958 mac_write(sc, GMACAFR, csr); 959 960 ETHER_LOCK(ec); 961 if (ifp->if_flags & IFF_PROMISC) { 962 ec->ec_flags |= ETHER_F_ALLMULTI; 963 ETHER_UNLOCK(ec); 964 goto update; 965 } 966 ec->ec_flags &= ~ETHER_F_ALLMULTI; 967 968 /* clear 15 entry supplimental perfect match filter */ 969 for (i = 1; i < 16; i++) 970 mac_write(sc, GMACMAH(i), 0); 971 /* build 256 bit multicast hash filter */ 972 memset(mchash, 0, sizeof(mchash)); 973 crc = 0; 974 975 ETHER_FIRST_MULTI(step, ec, enm); 976 i = 1; /* slot 0 is occupied */ 977 while (enm != NULL) { 978 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 979 /* 980 * We must listen to a range of multicast addresses. 981 * For now, just accept all multicasts, rather than 982 * trying to set only those filter bits needed to match 983 * the range. (At this time, the only use of address 984 * ranges is for IP multicast routing, for which the 985 * range is big enough to require all bits set.) 986 */ 987 ec->ec_flags |= ETHER_F_ALLMULTI; 988 ETHER_UNLOCK(ec); 989 goto update; 990 } 991 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 992 if (i < 16) { 993 /* use 15 entry perfect match filter */ 994 uint32_t addr; 995 uint8_t *ep = enm->enm_addrlo; 996 addr = (ep[3] << 24) | (ep[2] << 16) 997 | (ep[1] << 8) | ep[0]; 998 mac_write(sc, GMACMAL(i), addr); 999 addr = (ep[5] << 8) | ep[4]; 1000 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1001 } else { 1002 /* use hash table when too many */ 1003 /* bit_reserve_32(~crc) !? */ 1004 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1005 /* 3(31:29) 5(28:24) bit sampling */ 1006 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 1007 } 1008 ETHER_NEXT_MULTI(step, enm); 1009 i++; 1010 } 1011 ETHER_UNLOCK(ec); 1012 1013 if (crc) 1014 csr |= AFR_MHTE; 1015 for (i = 0; i < __arraycount(mchash); i++) 1016 mac_write(sc, GMACMHT(i), mchash[i]); 1017 mac_write(sc, GMACAFR, csr); 1018 return; 1019 1020 update: 1021 /* With PM or AM, MHTE/MHT0-7 are never consulted. really? */ 1022 if (ifp->if_flags & IFF_PROMISC) 1023 csr |= AFR_PM; /* run promisc. mode */ 1024 else 1025 csr |= AFR_AM; /* accept all multicast */ 1026 mac_write(sc, GMACAFR, csr); 1027 return; 1028 } 1029 1030 static int 1031 scx_ifmedia_upd(struct ifnet *ifp) 1032 { 1033 struct scx_softc *sc = ifp->if_softc; 1034 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1035 1036 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 1037 ; /* restart AN */ 1038 ; /* enable AN */ 1039 ; /* advertise flow control pause */ 1040 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 1041 } else { 1042 #if 1 /* XXX not sure to belong here XXX */ 1043 uint32_t mcr = mac_read(sc, GMACMCR); 1044 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 1045 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1046 else { 1047 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX 1048 && sc->sc_100mii) 1049 mcr |= MCR_SPD100; 1050 mcr |= MCR_USEMII; 1051 } 1052 if (ifm->ifm_cur->ifm_media & IFM_FDX) 1053 mcr |= MCR_USEFDX; 1054 mcr |= MCR_CST | MCR_JE; 1055 if (sc->sc_100mii == 0) 1056 mcr |= MCR_IBN; 1057 mac_write(sc, GMACMCR, mcr); 1058 #endif 1059 } 1060 return 0; 1061 } 1062 1063 static void 1064 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1065 { 1066 struct scx_softc *sc = ifp->if_softc; 1067 struct mii_data *mii = &sc->sc_mii; 1068 1069 mii_pollstat(mii); 1070 ifmr->ifm_status = mii->mii_media_status; 1071 ifmr->ifm_active = sc->sc_flowflags | 1072 (mii->mii_media_active & ~IFM_ETH_FMASK); 1073 } 1074 1075 void 1076 mii_statchg(struct ifnet *ifp) 1077 { 1078 struct scx_softc *sc = ifp->if_softc; 1079 struct mii_data *mii = &sc->sc_mii; 1080 uint32_t fcr; 1081 1082 #if 1 1083 /* decode MIISR register value */ 1084 uint32_t miisr = mac_read(sc, GMACMIISR); 1085 int spd = (miisr >> 1) & 03; 1086 printf("MII link status (0x%x) %s", 1087 miisr, (miisr & 8) ? "up" : "down"); 1088 if (miisr & 8) { 1089 printf(" spd%d", (spd == 2) ? 1000 : (spd == 1) ? 100 : 10); 1090 if (miisr & 1) 1091 printf(",full-duplex"); 1092 } 1093 printf("\n"); 1094 #endif 1095 /* Get flow control negotiation result. */ 1096 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1097 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1098 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1099 1100 /* Adjust PAUSE flow control. */ 1101 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1102 if (mii->mii_media_active & IFM_FDX) { 1103 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1104 fcr |= FCR_TFE; 1105 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1106 fcr |= FCR_RFE; 1107 } 1108 mac_write(sc, GMACFCR, fcr); 1109 1110 printf("%ctxfe, %crxfe\n", 1111 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1112 } 1113 1114 static void 1115 phy_tick(void *arg) 1116 { 1117 struct scx_softc *sc = arg; 1118 struct mii_data *mii = &sc->sc_mii; 1119 int s; 1120 1121 s = splnet(); 1122 mii_tick(mii); 1123 splx(s); 1124 1125 callout_schedule(&sc->sc_tick_ch, hz); 1126 } 1127 1128 static int 1129 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1130 { 1131 struct scx_softc *sc = device_private(self); 1132 uint32_t miia; 1133 int error; 1134 1135 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1136 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1137 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1138 if (error) 1139 return error; 1140 *val = mac_read(sc, GMACGDR); 1141 return 0; 1142 } 1143 1144 static int 1145 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1146 { 1147 struct scx_softc *sc = device_private(self); 1148 uint32_t miia; 1149 uint16_t dummy; 1150 int error; 1151 1152 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1153 mac_write(sc, GMACGDR, val); 1154 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1155 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1156 if (error) 1157 return error; 1158 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1159 return 0; 1160 } 1161 1162 static void 1163 scx_start(struct ifnet *ifp) 1164 { 1165 struct scx_softc *sc = ifp->if_softc; 1166 struct mbuf *m0, *m; 1167 struct scx_txsoft *txs; 1168 bus_dmamap_t dmamap; 1169 int error, nexttx, lasttx, ofree, seg; 1170 uint32_t tdes0; 1171 1172 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1173 return; 1174 1175 /* Remember the previous number of free descriptors. */ 1176 ofree = sc->sc_txfree; 1177 1178 /* 1179 * Loop through the send queue, setting up transmit descriptors 1180 * until we drain the queue, or use up all available transmit 1181 * descriptors. 1182 */ 1183 for (;;) { 1184 IFQ_POLL(&ifp->if_snd, m0); 1185 if (m0 == NULL) 1186 break; 1187 1188 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1189 txreap(sc); 1190 if (sc->sc_txsfree == 0) 1191 break; 1192 } 1193 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1194 dmamap = txs->txs_dmamap; 1195 1196 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1197 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1198 if (error) { 1199 if (error == EFBIG) { 1200 aprint_error_dev(sc->sc_dev, 1201 "Tx packet consumes too many " 1202 "DMA segments, dropping...\n"); 1203 IFQ_DEQUEUE(&ifp->if_snd, m0); 1204 m_freem(m0); 1205 continue; 1206 } 1207 /* Short on resources, just stop for now. */ 1208 break; 1209 } 1210 1211 if (dmamap->dm_nsegs > sc->sc_txfree) { 1212 /* 1213 * Not enough free descriptors to transmit this 1214 * packet. We haven't committed anything yet, 1215 * so just unload the DMA map, put the packet 1216 * back on the queue, and punt. Notify the upper 1217 * layer that there are not more slots left. 1218 */ 1219 ifp->if_flags |= IFF_OACTIVE; 1220 bus_dmamap_unload(sc->sc_dmat, dmamap); 1221 break; 1222 } 1223 1224 IFQ_DEQUEUE(&ifp->if_snd, m0); 1225 1226 /* 1227 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1228 */ 1229 1230 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1231 BUS_DMASYNC_PREWRITE); 1232 1233 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1234 lasttx = -1; 1235 for (nexttx = sc->sc_txnext, seg = 0; 1236 seg < dmamap->dm_nsegs; 1237 seg++, nexttx = MD_NEXTTX(nexttx)) { 1238 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1239 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1240 /* 1241 * If this is the first descriptor we're 1242 * enqueueing, don't set the OWN bit just 1243 * yet. That could cause a race condition. 1244 * We'll do it below. 1245 */ 1246 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1247 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1248 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1249 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1250 (15 << T0_TRID) | T0_PT | 1251 sc->sc_t0coso | T0_TRS; 1252 tdes0 = T0_OWN; /* 2nd and other segments */ 1253 lasttx = nexttx; 1254 } 1255 /* 1256 * Outgoing NFS mbuf must be unloaded when Tx completed. 1257 * Without T1_IC NFS mbuf is left unack'ed for excessive 1258 * time and NFS stops to proceed until scx_watchdog() 1259 * calls txreap() to reclaim the unack'ed mbuf. 1260 * It's painful to traverse every mbuf chain to determine 1261 * whether someone is waiting for Tx completion. 1262 */ 1263 m = m0; 1264 do { 1265 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1266 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1267 break; 1268 } 1269 } while ((m = m->m_next) != NULL); 1270 1271 /* Write deferred 1st segment T0_OWN at the final stage */ 1272 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1273 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1274 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1275 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1276 1277 /* Tell DMA start transmit */ 1278 mac_write(sc, GMACTDS, 1); 1279 1280 txs->txs_mbuf = m0; 1281 txs->txs_firstdesc = sc->sc_txnext; 1282 txs->txs_lastdesc = lasttx; 1283 txs->txs_ndesc = dmamap->dm_nsegs; 1284 1285 sc->sc_txfree -= txs->txs_ndesc; 1286 sc->sc_txnext = nexttx; 1287 sc->sc_txsfree--; 1288 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1289 /* 1290 * Pass the packet to any BPF listeners. 1291 */ 1292 bpf_mtap(ifp, m0, BPF_D_OUT); 1293 } 1294 1295 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1296 /* No more slots left; notify upper layer. */ 1297 ifp->if_flags |= IFF_OACTIVE; 1298 } 1299 if (sc->sc_txfree != ofree) { 1300 /* Set a watchdog timer in case the chip flakes out. */ 1301 ifp->if_timer = 5; 1302 } 1303 } 1304 1305 static int 1306 scx_intr(void *arg) 1307 { 1308 struct scx_softc *sc = arg; 1309 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1310 1311 (void)ifp; 1312 /* XXX decode interrupt cause to pick isr() XXX */ 1313 rxintr(sc); 1314 txreap(sc); 1315 return 1; 1316 } 1317 1318 static void 1319 txreap(struct scx_softc *sc) 1320 { 1321 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1322 struct scx_txsoft *txs; 1323 uint32_t txstat; 1324 int i; 1325 1326 ifp->if_flags &= ~IFF_OACTIVE; 1327 1328 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1329 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1330 txs = &sc->sc_txsoft[i]; 1331 1332 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1333 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1334 1335 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1336 if (txstat & T0_OWN) /* desc is still in use */ 1337 break; 1338 1339 /* There is no way to tell transmission status per frame */ 1340 1341 if_statinc(ifp, if_opackets); 1342 1343 sc->sc_txfree += txs->txs_ndesc; 1344 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1345 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1346 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1347 m_freem(txs->txs_mbuf); 1348 txs->txs_mbuf = NULL; 1349 } 1350 sc->sc_txsdirty = i; 1351 if (sc->sc_txsfree == MD_TXQUEUELEN) 1352 ifp->if_timer = 0; 1353 } 1354 1355 static void 1356 rxintr(struct scx_softc *sc) 1357 { 1358 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1359 struct scx_rxsoft *rxs; 1360 struct mbuf *m; 1361 uint32_t rxstat; 1362 int i, len; 1363 1364 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1365 rxs = &sc->sc_rxsoft[i]; 1366 1367 SCX_CDRXSYNC(sc, i, 1368 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1369 1370 rxstat = sc->sc_rxdescs[i].r0; 1371 if (rxstat & R0_OWN) /* desc is left empty */ 1372 break; 1373 1374 /* R0_FS | R0_LS must have been marked for this desc */ 1375 1376 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1377 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1378 1379 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1380 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1381 m = rxs->rxs_mbuf; 1382 1383 if (add_rxbuf(sc, i) != 0) { 1384 if_statinc(ifp, if_ierrors); 1385 SCX_INIT_RXDESC(sc, i); 1386 bus_dmamap_sync(sc->sc_dmat, 1387 rxs->rxs_dmamap, 0, 1388 rxs->rxs_dmamap->dm_mapsize, 1389 BUS_DMASYNC_PREREAD); 1390 continue; 1391 } 1392 1393 m_set_rcvif(m, ifp); 1394 m->m_pkthdr.len = m->m_len = len; 1395 1396 if (rxstat & R0_CSUM) { 1397 uint32_t csum = M_CSUM_IPv4; 1398 if (rxstat & R0_CERR) 1399 csum |= M_CSUM_IPv4_BAD; 1400 m->m_pkthdr.csum_flags |= csum; 1401 } 1402 if_percpuq_enqueue(ifp->if_percpuq, m); 1403 } 1404 sc->sc_rxptr = i; 1405 } 1406 1407 static int 1408 add_rxbuf(struct scx_softc *sc, int i) 1409 { 1410 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1411 struct mbuf *m; 1412 int error; 1413 1414 MGETHDR(m, M_DONTWAIT, MT_DATA); 1415 if (m == NULL) 1416 return ENOBUFS; 1417 1418 MCLGET(m, M_DONTWAIT); 1419 if ((m->m_flags & M_EXT) == 0) { 1420 m_freem(m); 1421 return ENOBUFS; 1422 } 1423 1424 if (rxs->rxs_mbuf != NULL) 1425 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1426 1427 rxs->rxs_mbuf = m; 1428 1429 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1430 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1431 if (error) { 1432 aprint_error_dev(sc->sc_dev, 1433 "can't load rx DMA map %d, error = %d\n", i, error); 1434 panic("add_rxbuf"); 1435 } 1436 1437 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1438 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1439 SCX_INIT_RXDESC(sc, i); 1440 1441 return 0; 1442 } 1443 1444 static int 1445 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1446 { 1447 int val, loop; 1448 1449 val = CSR_READ(sc, reg); 1450 if ((val & exist) == 0) 1451 return 0; 1452 loop = 3000; 1453 do { 1454 DELAY(10); 1455 val = CSR_READ(sc, reg); 1456 } while (--loop > 0 && (val & exist)); 1457 return (loop > 0) ? 0 : ETIMEDOUT; 1458 } 1459 1460 /* GMAC register needs to use indirect rd/wr via memory mapped registers. */ 1461 1462 static int 1463 mac_read(struct scx_softc *sc, int reg) 1464 { 1465 1466 CSR_WRITE(sc, MACCMD, reg); 1467 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1468 return CSR_READ(sc, MACDATA); 1469 } 1470 1471 static void 1472 mac_write(struct scx_softc *sc, int reg, int val) 1473 { 1474 1475 CSR_WRITE(sc, MACDATA, val); 1476 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1477 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1478 } 1479 1480 /* 1481 * 3 independent uengines exist * to process host2media, media2host and 1482 * packet data flows. 1483 */ 1484 static void 1485 loaducode(struct scx_softc *sc) 1486 { 1487 uint32_t up, lo, sz; 1488 uint64_t addr; 1489 1490 sc->sc_ucodeloaded = 1; 1491 1492 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1493 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1494 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1495 sz *= 4; 1496 addr = ((uint64_t)up << 32) | lo; 1497 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1498 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1499 1500 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1501 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1502 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1503 sz *= 4; 1504 addr = ((uint64_t)up << 32) | lo; 1505 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1506 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1507 1508 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1509 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1510 sz *= 4; 1511 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1512 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1513 } 1514 1515 static void 1516 injectucode(struct scx_softc *sc, int port, 1517 bus_addr_t addr, bus_size_t size) 1518 { 1519 bus_space_handle_t bsh; 1520 bus_size_t off; 1521 uint32_t ucode; 1522 1523 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1524 aprint_error_dev(sc->sc_dev, 1525 "eeprom map failure for ucode port 0x%x\n", port); 1526 return; 1527 } 1528 for (off = 0; off < size; off += 4) { 1529 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1530 CSR_WRITE(sc, port, ucode); 1531 } 1532 bus_space_unmap(sc->sc_st, bsh, size); 1533 } 1534 1535 /* bit selection to determine MDIO speed */ 1536 1537 static int 1538 get_mdioclk(uint32_t freq) 1539 { 1540 1541 const struct { 1542 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 1543 } mdioclk[] = { 1544 { 35, 2 }, /* 25-35 MHz */ 1545 { 60, 3 }, /* 35-60 MHz */ 1546 { 100, 0 }, /* 60-100 MHz */ 1547 { 150, 1 }, /* 100-150 MHz */ 1548 { 250, 4 }, /* 150-250 MHz */ 1549 { 300, 5 }, /* 250-300 MHz */ 1550 }; 1551 int i; 1552 1553 freq /= 1000 * 1000; 1554 /* convert MDIO clk to a divisor value */ 1555 if (freq < mdioclk[0].freq) 1556 return mdioclk[0].bit; 1557 for (i = 1; i < __arraycount(mdioclk); i++) { 1558 if (freq < mdioclk[i].freq) 1559 return mdioclk[i-1].bit; 1560 } 1561 return mdioclk[__arraycount(mdioclk) - 1].bit << GAR_CTL; 1562 } 1563
Indexes created Sun Sep 28 16:09:52 GMT 2025