if_scx.c revision 1.23
1 /* $NetBSD: if_scx.c,v 1.23 2020/10/10 03:29:48 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 /* 34 * Socionext SC2A11 SynQuacer NetSec GbE driver 35 * 36 * Multiple Tx and Rx queues exist inside and dedicated descriptor 37 * fields specifies which queue is to use. Three internal micro-processors 38 * to handle incoming frames, outgoing frames and packet data crypto 39 * processing. uP programs are stored in an external flash memory and 40 * have to be loaded by device driver. 41 * NetSec uses Synopsys DesignWare Core EMAC. DWC implmentation 42 * regiter (0x20) is known to have 0x10.36 and feature register (0x1058) 43 * to report XX.XX. 44 */ 45 46 #define NOT_MP_SAFE 0 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.23 2020/10/10 03:29:48 nisimura Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/bus.h> 53 #include <sys/intr.h> 54 #include <sys/device.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/errno.h> 59 #include <sys/rndsource.h> 60 #include <sys/kernel.h> 61 #include <sys/systm.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_dl.h> 66 #include <net/if_ether.h> 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <net/bpf.h> 70 71 #include <dev/fdt/fdtvar.h> 72 #include <dev/acpi/acpireg.h> 73 #include <dev/acpi/acpivar.h> 74 #include <dev/acpi/acpi_intr.h> 75 76 /* Socionext SC2A11 descriptor format */ 77 struct tdes { 78 uint32_t t0, t1, t2, t3; 79 }; 80 81 struct rdes { 82 uint32_t r0, r1, r2, r3; 83 }; 84 85 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 86 #define T0_EOD (1U<<30) /* end of descriptor array */ 87 #define T0_DRID (24) /* 29:24 D-RID */ 88 #define T0_PT (1U<<21) /* 23:21 PT */ 89 #define T0_TRID (16) /* 20:16 T-RID */ 90 #define T0_FS (1U<<9) /* first segment of frame */ 91 #define T0_LS (1U<<8) /* last segment of frame */ 92 #define T0_CSUM (1U<<7) /* enable check sum offload */ 93 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 94 #define T0_TRS (1U<<4) /* 5:4 TRS */ 95 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 96 /* T1 segment address 63:32 */ 97 /* T2 segment address 31:0 */ 98 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 99 100 #define R0_OWN (1U<<31) /* desc is empty */ 101 #define R0_EOD (1U<<30) /* end of descriptor array */ 102 #define R0_SRID (24) /* 29:24 S-RID */ 103 #define R0_FR (1U<<23) /* FR */ 104 #define R0_ER (1U<<21) /* Rx error indication */ 105 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 106 #define R0_TDRID (14) /* 15:14 TD-RID */ 107 #define R0_FS (1U<<9) /* first segment of frame */ 108 #define R0_LS (1U<<8) /* last segment of frame */ 109 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 110 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 111 /* R1 frame address 63:32 */ 112 /* R2 frame address 31:0 */ 113 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 114 115 /* 116 * SC2A11 NetSec registers. 0x100 - 1204 117 */ 118 #define SWRESET 0x104 119 #define COMINIT 0x120 120 #define xINTSR 0x200 /* aggregated interrupt status report */ 121 #define IRQ_RX (1U<<1) /* top level Rx interrupt */ 122 #define IRQ_TX (1U<<0) /* top level Rx interrupt */ 123 #define xINTAEN 0x204 /* INT_A enable */ 124 #define xINTA_SET 0x234 /* bit to set */ 125 #define xINTA_CLR 0x238 /* bit to clr */ 126 #define xINTBEN 0x23c /* INT_B enable */ 127 #define xINTB_SET 0x240 /* bit to set */ 128 #define xINTB_CLR 0x244 /* bit to clr */ 129 /* 0x00c - 048 */ /* pkt,tls,s0,s1 SR/IE/SET/CLR */ 130 #define TXISR 0x400 131 #define TXIEN 0x404 132 #define TXI_SET 0x428 133 #define TXI_CLR 0x42c 134 #define TXI_NTOWNR (1U<<17) 135 #define TXI_TR_ERR (1U<<16) 136 #define TXI_TXDONE (1U<<15) 137 #define TXI_TMREXP (1U<<14) 138 #define RXISR 0x440 139 #define RXIEN 0x444 140 #define RXI_SET 0x468 141 #define RXI_CLR 0x46c 142 #define RXI_RC_ERR (1U<<16) 143 #define RXI_PKTCNT (1U<<15) 144 #define RXI_TMREXP (1U<<14) 145 #define TXTIMER 0x41c 146 #define RXTIMER 0x45c 147 #define TXCOUNT 0x410 148 #define RXCOUNT 0x454 149 #define H2MENG 0x210 /* DMAC host2media ucode port */ 150 #define M2HENG 0x21c /* DMAC media2host ucode port */ 151 #define PKTENG 0x0d0 /* packet engine ucode port */ 152 #define CLKEN 0x100 /* clock distribution enable */ 153 #define CLK_G (1U<<5) 154 #define CLK_ALL 0x13 /* 0x24 ??? */ 155 #define MACADRH 0x10c /* ??? */ 156 #define MACADRL 0x110 /* ??? */ 157 #define MCVER 0x22c /* micro controller version */ 158 #define HWVER 0x230 /* hardware version */ 159 160 /* 0x800 */ /* dec Tx SR/EN/SET/CLR */ 161 /* 0x840 */ /* enc Rx SR/EN/SET/CLR */ 162 /* 0x880 */ /* enc TLS Tx SR/IE/SET/CLR */ 163 /* 0x8c0 */ /* dec TLS Tx SR/IE/SET/CLR */ 164 /* 0x900 */ /* enc TLS Rx SR/IE/SET/CLR */ 165 /* 0x940 */ /* dec TLS Rx SR/IE/SET/CLR */ 166 /* 0x980 */ /* enc RAW Tx SR/IE/SET/CLR */ 167 /* 0x9c0 */ /* dec RAW Tx SR/IE/SET/CLR */ 168 /* 0xA00 */ /* enc RAW Rx SR/IE/SET/CLR */ 169 /* 0xA40 */ /* dec RAW Rx SR/IE/SET/CLR */ 170 171 /* indirect GMAC registers. accessed thru MACCMD/MACDATA operation */ 172 #define MACCMD 0x11c4 /* gmac operation */ 173 #define CMD_IOWR (1U<<28) /* write op */ 174 #define CMD_BUSY (1U<<31) /* busy bit */ 175 #define MACSTAT 0x1024 /* gmac status */ 176 #define MACDATA 0x11c0 /* gmac rd/wr data */ 177 #define MACINTE 0x1028 /* interrupt enable */ 178 #define DESC_INIT 0x11fc /* desc engine init */ 179 #define DESC_SRST 0x1204 /* desc engine sw reset */ 180 181 /* 182 * GMAC registers. not memory mapped, but handled by indirect access. 183 * Mostly identical to Synopsys DesignWare Core Ethernet. 184 */ 185 #define GMACMCR 0x0000 /* MAC configuration */ 186 #define MCR_IBN (1U<<30) /* ??? */ 187 #define MCR_CST (1U<<25) /* strip CRC */ 188 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 189 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 190 #define MCR_IFG (7U<<17) /* 19:17 IFG value 0~7 */ 191 #define MCR_DRCS (1U<<16) /* ignore (G)MII HDX Tx error */ 192 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII (_PS) */ 193 #define MCR_SPD100 (1U<<14) /* force speed 100 (_FES) */ 194 #define MCR_DO (1U<<13) /* */ 195 #define MCR_LOOP (1U<<12) /* */ 196 #define MCR_USEFDX (1U<<11) /* force full duplex */ 197 #define MCR_IPCEN (1U<<10) /* handle checksum */ 198 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 199 #define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */ 200 #define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */ 201 #define MCR_PREA (3U) /* 1:0 preamble len. 0~2 */ 202 #define _MCR_FDX 0x0000280c /* XXX TBD */ 203 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 204 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 205 #define AFR_RA (1U<<31) /* accept all irrecspective of filt. */ 206 #define AFR_HPF (1U<<10) /* hash+perfect filter, or hash only */ 207 #define AFR_SAF (1U<<9) /* source address filter */ 208 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 209 #define AFR_PCF (2U<<6) /* */ 210 #define AFR_DBF (1U<<5) /* reject broadcast frame */ 211 #define AFR_PM (1U<<4) /* accept all multicast frame */ 212 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 213 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 214 #define AFR_UHTE (1U<<1) /* use hash table for unicast */ 215 #define AFR_PR (1U<<0) /* run promisc mode */ 216 #define GMACGAR 0x0010 /* MDIO operation */ 217 #define GAR_PHY (11) /* mii phy 15:11 */ 218 #define GAR_REG (6) /* mii reg 10:6 */ 219 #define GAR_CTL (2) /* control 5:2 */ 220 #define GAR_IOWR (1U<<1) /* MDIO write op */ 221 #define GAR_BUSY (1U) /* busy bit */ 222 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 223 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 224 /* 31:16 pause timer value, 5:4 pause timer threthold */ 225 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 226 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 227 #define GMACVTAG 0x001c /* VLAN tag control */ 228 #define GMACIMPL 0x0020 /* implementation number XX.YY */ 229 #define GMACLPIS 0x0030 /* AXI LPI control */ 230 #define GMACLPIC 0x0034 /* AXI LPI control */ 231 #define GMACISR 0x0038 /* interrupt status, clear when read */ 232 #define GMACIMR 0x003c /* interrupt enable */ 233 #define ISR_TS (1U<<9) /* time stamp operation detected */ 234 #define ISR_CO (1U<<7) /* Rx checksum offload completed */ 235 #define ISR_TX (1U<<6) /* Tx completed */ 236 #define ISR_RX (1U<<5) /* Rx completed */ 237 #define ISR_ANY (1U<<4) /* any of above 5-7 report */ 238 #define ISR_LC (1U<<0) /* link status change detected */ 239 #define GMACMAH0 0x0040 /* my own MAC address 47:32 */ 240 #define GMACMAL0 0x0044 /* my own MAC address 31:0 */ 241 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1-15 */ 242 #define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */ 243 /* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */ 244 #define GMACAMAH(i) ((i)*8+0x800) /* supplimental MAC addr 16-31 */ 245 #define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */ 246 /* MAH bit-31: slot in use, no other bit is effective */ 247 #define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */ 248 #define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */ 249 #define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */ 250 #define GMACVHT 0x0588 /* 16-bit VLAN tag hash */ 251 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 252 /* 3: link up detected, 2:1 resovled speed (0/1/2), 1: fdx detected */ 253 254 /* 0x0700 - 0734 ??? */ 255 256 #define GMACBMR 0x1000 /* DMA bus mode control */ 257 /* 24 4PBL 8??? 258 * 23 USP 259 * 22:17 RPBL 260 * 16 fixed burst, or undefined b. 261 * 15:14 priority between Rx and Tx 262 * 3 rxtx ratio 41 263 * 2 rxtx ratio 31 264 * 1 rxtx ratio 21 265 * 0 rxtx ratio 11 266 * 13:8 PBL packet burst len 267 * 7 alternative des8 268 * 0 reset op. (SC) 269 */ 270 #define _BMR 0x00412080 /* XXX TBD */ 271 #define _BMR0 0x00020181 /* XXX TBD */ 272 #define BMR_RST (1) /* reset op. self clear when done */ 273 #define GMACTPD 0x1004 /* write any to resume tdes */ 274 #define GMACRPD 0x1008 /* write any to resume rdes */ 275 #define GMACRDLA 0x100c /* rdes base address 32bit paddr */ 276 #define GMACTDLA 0x1010 /* tdes base address 32bit paddr */ 277 #define _RDLA 0x18000 /* XXX TBD system SRAM ? */ 278 #define _TDLA 0x1c000 /* XXX TBD system SRAM ? */ 279 #define GMACDSR 0x1014 /* DMA status detail report; W1C */ 280 #define GMACOMR 0x1018 /* DMA operation */ 281 #define OMR_TSF (1U<<25) /* 1: Tx store&forword, 0: immed. */ 282 #define OMR_RSF (1U<<21) /* 1: Rx store&forward, 0: immed. */ 283 #define OMR_ST (1U<<13) /* run Tx DMA engine, 0 to stop */ 284 #define OMR_EFC (1U<<8) /* transmit PAUSE to throttle Rx lvl. */ 285 #define OMR_FEF (1U<<7) /* allow to receive error frames */ 286 #define OMR_RS (1U<<1) /* run Rx DMA engine, 0 to stop */ 287 #define GMACIE 0x101c /* interrupt enable */ 288 #define GMACEVCS 0x1020 /* missed frame or ovf detected */ 289 #define GMACRWDT 0x1024 /* receive watchdog timer count */ 290 #define GMACAXIB 0x1028 /* AXI bus mode control */ 291 #define GMACAXIS 0x102c /* AXI status report */ 292 /* 0x1048 - 1054 */ /* descriptor and buffer cur. address */ 293 #define HWFEA 0x1058 /* feature report */ 294 295 #define GMACEVCTL 0x0100 /* event counter control */ 296 #define GMACEVCNT(i) ((i)*4+0x114) /* event counter 0x114 - 0x284 */ 297 298 /* memory mapped CSR register */ 299 #define CSR_READ(sc,off) \ 300 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 301 #define CSR_WRITE(sc,off,val) \ 302 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 303 304 /* flash memory access */ 305 #define EE_READ(sc,off) \ 306 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 307 308 /* 309 * flash memory layout 310 * 0x00 - 07 48-bit MAC station address. 4 byte wise in BE order. 311 * 0x08 - 0b H->MAC xfer uengine program start addr 63:32. 312 * 0x0c - 0f H2M program addr 31:0 (these are absolute addr, not relative) 313 * 0x10 - 13 H2M program length in 4 byte count. 314 * 0x14 - 0b M->HOST xfer uengine program start addr 63:32. 315 * 0x18 - 0f M2H program addr 31:0 (absolute, not relative) 316 * 0x1c - 13 M2H program length in 4 byte count. 317 * 0x20 - 23 packet uengine program addr 31:0, (absolute, not relative) 318 * 0x24 - 27 packet program length in 4 byte count. 319 * 320 * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0. 321 */ 322 323 /* 324 * all below are software constraction. 325 */ 326 #define MD_NTXSEGS 16 /* fixed */ 327 #define MD_TXQUEUELEN 8 /* tunable */ 328 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 329 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 330 #define MD_NTXDESC 128 331 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 332 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 333 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 334 335 #define MD_NRXDESC 64 /* tunable */ 336 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 337 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 338 339 struct control_data { 340 struct tdes cd_txdescs[MD_NTXDESC]; 341 struct rdes cd_rxdescs[MD_NRXDESC]; 342 }; 343 #define SCX_CDOFF(x) offsetof(struct control_data, x) 344 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 345 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 346 347 struct scx_txsoft { 348 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 349 bus_dmamap_t txs_dmamap; /* our DMA map */ 350 int txs_firstdesc; /* first descriptor in packet */ 351 int txs_lastdesc; /* last descriptor in packet */ 352 int txs_ndesc; /* # of descriptors used */ 353 }; 354 355 struct scx_rxsoft { 356 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 357 bus_dmamap_t rxs_dmamap; /* our DMA map */ 358 }; 359 360 struct scx_softc { 361 device_t sc_dev; /* generic device information */ 362 bus_space_tag_t sc_st; /* bus space tag */ 363 bus_space_handle_t sc_sh; /* bus space handle */ 364 bus_size_t sc_sz; /* csr map size */ 365 bus_space_handle_t sc_eesh; /* eeprom section handle */ 366 bus_size_t sc_eesz; /* eeprom map size */ 367 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 368 bus_dma_tag_t sc_dmat32; 369 struct ethercom sc_ethercom; /* Ethernet common data */ 370 struct mii_data sc_mii; /* MII */ 371 callout_t sc_callout; /* PHY monitor callout */ 372 bus_dma_segment_t sc_seg; /* descriptor store seg */ 373 int sc_nseg; /* descriptor store nseg */ 374 void *sc_ih; /* interrupt cookie */ 375 int sc_phy_id; /* PHY address */ 376 int sc_flowflags; /* 802.3x PAUSE flow control */ 377 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 378 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 379 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 380 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 381 int sc_phandle; /* fdt phandle */ 382 uint64_t sc_freq; 383 384 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 385 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 386 387 struct control_data *sc_control_data; 388 #define sc_txdescs sc_control_data->cd_txdescs 389 #define sc_rxdescs sc_control_data->cd_rxdescs 390 391 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 392 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 393 int sc_txfree; /* number of free Tx descriptors */ 394 int sc_txnext; /* next ready Tx descriptor */ 395 int sc_txsfree; /* number of free Tx jobs */ 396 int sc_txsnext; /* next ready Tx job */ 397 int sc_txsdirty; /* dirty Tx jobs */ 398 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 399 400 krndsource_t rnd_source; /* random source */ 401 }; 402 403 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 404 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 405 406 #define SCX_CDTXSYNC(sc, x, n, ops) \ 407 do { \ 408 int __x, __n; \ 409 \ 410 __x = (x); \ 411 __n = (n); \ 412 \ 413 /* If it will wrap around, sync to the end of the ring. */ \ 414 if ((__x + __n) > MD_NTXDESC) { \ 415 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 416 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 417 (MD_NTXDESC - __x), (ops)); \ 418 __n -= (MD_NTXDESC - __x); \ 419 __x = 0; \ 420 } \ 421 \ 422 /* Now sync whatever is left. */ \ 423 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 424 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 425 } while (/*CONSTCOND*/0) 426 427 #define SCX_CDRXSYNC(sc, x, ops) \ 428 do { \ 429 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 430 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 431 } while (/*CONSTCOND*/0) 432 433 #define SCX_INIT_RXDESC(sc, x) \ 434 do { \ 435 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 436 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 437 struct mbuf *__m = __rxs->rxs_mbuf; \ 438 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 439 __m->m_data = __m->m_ext.ext_buf; \ 440 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 441 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 442 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 443 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 444 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 445 } while (/*CONSTCOND*/0) 446 447 static int scx_fdt_match(device_t, cfdata_t, void *); 448 static void scx_fdt_attach(device_t, device_t, void *); 449 static int scx_acpi_match(device_t, cfdata_t, void *); 450 static void scx_acpi_attach(device_t, device_t, void *); 451 452 const CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 453 scx_fdt_match, scx_fdt_attach, NULL, NULL); 454 455 const CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 456 scx_acpi_match, scx_acpi_attach, NULL, NULL); 457 458 static void scx_attach_i(struct scx_softc *); 459 static void scx_reset(struct scx_softc *); 460 static int scx_init(struct ifnet *); 461 static void scx_stop(struct ifnet *, int); 462 static int scx_ioctl(struct ifnet *, u_long, void *); 463 static void scx_set_rcvfilt(struct scx_softc *); 464 static void scx_start(struct ifnet *); 465 static void scx_watchdog(struct ifnet *); 466 static int scx_intr(void *); 467 static void txreap(struct scx_softc *); 468 static void rxintr(struct scx_softc *); 469 static int add_rxbuf(struct scx_softc *, int); 470 static void rxdrain(struct scx_softc *sc); 471 static void mii_statchg(struct ifnet *); 472 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 473 static int mii_readreg(device_t, int, int, uint16_t *); 474 static int mii_writereg(device_t, int, int, uint16_t); 475 static void phy_tick(void *); 476 477 static void loaducode(struct scx_softc *); 478 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 479 480 static int get_mdioclk(uint32_t); 481 482 #define WAIT_FOR_SET(sc, reg, set, fail) \ 483 wait_for_bits(sc, reg, set, ~0, fail) 484 #define WAIT_FOR_CLR(sc, reg, clr, fail) \ 485 wait_for_bits(sc, reg, 0, clr, fail) 486 487 static int 488 wait_for_bits(struct scx_softc *sc, int reg, 489 uint32_t set, uint32_t clr, uint32_t fail) 490 { 491 uint32_t val; 492 int ntries; 493 494 for (ntries = 0; ntries < 1000; ntries++) { 495 val = CSR_READ(sc, reg); 496 if ((val & set) || !(val & clr)) 497 return 0; 498 if (val & fail) 499 return 1; 500 DELAY(1); 501 } 502 return 1; 503 } 504 505 /* GMAC register indirect access */ 506 static int 507 mac_read(struct scx_softc *sc, int reg) 508 { 509 510 CSR_WRITE(sc, MACCMD, reg); 511 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 512 return CSR_READ(sc, MACDATA); 513 } 514 515 static void 516 mac_write(struct scx_softc *sc, int reg, int val) 517 { 518 519 CSR_WRITE(sc, MACDATA, val); 520 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 521 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 522 } 523 524 static int 525 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 526 { 527 static const char * compatible[] = { 528 "socionext,synquacer-netsec", 529 NULL 530 }; 531 struct fdt_attach_args * const faa = aux; 532 533 return of_match_compatible(faa->faa_phandle, compatible); 534 } 535 536 static void 537 scx_fdt_attach(device_t parent, device_t self, void *aux) 538 { 539 struct scx_softc * const sc = device_private(self); 540 struct fdt_attach_args * const faa = aux; 541 const int phandle = faa->faa_phandle; 542 bus_space_tag_t bst = faa->faa_bst; 543 bus_space_handle_t bsh; 544 bus_space_handle_t eebsh; 545 bus_addr_t addr[2]; 546 bus_size_t size[2]; 547 char intrstr[128]; 548 const char *phy_mode; 549 550 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 551 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 552 aprint_error(": unable to map device csr\n"); 553 return; 554 } 555 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 556 aprint_error(": failed to decode interrupt\n"); 557 goto fail; 558 } 559 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 560 NOT_MP_SAFE, scx_intr, sc); 561 if (sc->sc_ih == NULL) { 562 aprint_error_dev(self, "couldn't establish interrupt\n"); 563 goto fail; 564 } 565 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 566 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 567 aprint_error(": unable to map device eeprom\n"); 568 goto fail; 569 } 570 571 aprint_naive("\n"); 572 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 573 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 574 575 sc->sc_dev = self; 576 sc->sc_st = bst; 577 sc->sc_sh = bsh; 578 sc->sc_sz = size[0]; 579 sc->sc_eesh = eebsh; 580 sc->sc_eesz = size[1]; 581 sc->sc_dmat = faa->faa_dmat; 582 sc->sc_dmat32 = faa->faa_dmat; /* XXX */ 583 sc->sc_phandle = phandle; 584 585 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 586 if (phy_mode == NULL) 587 aprint_error(": missing 'phy-mode' property\n"); 588 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 589 590 scx_attach_i(sc); 591 return; 592 fail: 593 if (sc->sc_eesz) 594 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 595 if (sc->sc_sz) 596 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 597 return; 598 } 599 600 static int 601 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 602 { 603 static const char * compatible[] = { 604 "SCX0001", 605 NULL 606 }; 607 struct acpi_attach_args *aa = aux; 608 609 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 610 return 0; 611 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 612 } 613 614 static void 615 scx_acpi_attach(device_t parent, device_t self, void *aux) 616 { 617 struct scx_softc * const sc = device_private(self); 618 struct acpi_attach_args * const aa = aux; 619 ACPI_HANDLE handle = aa->aa_node->ad_handle; 620 bus_space_tag_t bst = aa->aa_memt; 621 bus_space_handle_t bsh, eebsh; 622 struct acpi_resources res; 623 struct acpi_mem *mem; 624 struct acpi_irq *irq; 625 char *phy_mode; 626 ACPI_INTEGER acpi_phy, acpi_freq; 627 ACPI_STATUS rv; 628 629 rv = acpi_resource_parse(self, handle, "_CRS", 630 &res, &acpi_resource_parse_ops_default); 631 if (ACPI_FAILURE(rv)) 632 return; 633 mem = acpi_res_mem(&res, 0); 634 irq = acpi_res_irq(&res, 0); 635 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 636 aprint_error(": incomplete csr resources\n"); 637 return; 638 } 639 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 640 aprint_error(": couldn't map registers\n"); 641 return; 642 } 643 sc->sc_sz = mem->ar_length; 644 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 645 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 646 if (sc->sc_ih == NULL) { 647 aprint_error_dev(self, "couldn't establish interrupt\n"); 648 goto fail; 649 } 650 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 651 if (mem == NULL || mem->ar_length == 0) { 652 aprint_error(": incomplete eeprom resources\n"); 653 goto fail; 654 } 655 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 656 aprint_error(": couldn't map registers\n"); 657 goto fail; 658 } 659 sc->sc_eesz = mem->ar_length; 660 661 rv = acpi_dsd_string(handle, "phy-mode", &phy_mode); 662 if (ACPI_FAILURE(rv)) { 663 aprint_error(": missing 'phy-mode' property\n"); 664 phy_mode = NULL; 665 } 666 rv = acpi_dsd_integer(handle, "phy-channel", &acpi_phy); 667 if (ACPI_FAILURE(rv)) 668 acpi_phy = 31; 669 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 670 &acpi_freq); 671 if (ACPI_FAILURE(rv)) 672 acpi_freq = 999; 673 674 aprint_naive("\n"); 675 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 676 677 sc->sc_dev = self; 678 sc->sc_st = bst; 679 sc->sc_sh = bsh; 680 sc->sc_eesh = eebsh; 681 sc->sc_dmat = aa->aa_dmat64; 682 sc->sc_dmat32 = aa->aa_dmat; /* descriptor needs dma32 */ 683 684 aprint_normal_dev(self, 685 "phy mode %s, phy id %d, freq %ld\n", phy_mode, (int)acpi_phy, acpi_freq); 686 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 687 sc->sc_phy_id = (int)acpi_phy; 688 sc->sc_freq = acpi_freq; 689 aprint_normal_dev(self, 690 "GMACGAR %08x\n", mac_read(sc, GMACGAR)); 691 692 scx_attach_i(sc); 693 694 acpi_resource_cleanup(&res); 695 return; 696 fail: 697 if (sc->sc_eesz > 0) 698 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 699 if (sc->sc_sz > 0) 700 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 701 acpi_resource_cleanup(&res); 702 return; 703 } 704 705 static void 706 scx_attach_i(struct scx_softc *sc) 707 { 708 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 709 struct mii_data * const mii = &sc->sc_mii; 710 struct ifmedia * const ifm = &mii->mii_media; 711 uint32_t hwver, dwimp, dwfea; 712 uint8_t enaddr[ETHER_ADDR_LEN]; 713 bus_dma_segment_t seg; 714 uint32_t csr; 715 int i, nseg, error = 0; 716 717 hwver = CSR_READ(sc, HWVER); /* Socionext version */ 718 dwimp = mac_read(sc, GMACIMPL); /* DW EMAC XX.YY */ 719 dwfea = mac_read(sc, HWFEA); /* DW feature */ 720 aprint_normal_dev(sc->sc_dev, 721 "Socionext NetSec GbE %d.%d (impl 0x%x, feature 0x%x)\n", 722 hwver >> 16, hwver & 0xffff, 723 dwimp, dwfea); 724 725 /* fetch MAC address in flash. stored in big endian order */ 726 csr = EE_READ(sc, 0x00); 727 enaddr[0] = csr >> 24; 728 enaddr[1] = csr >> 16; 729 enaddr[2] = csr >> 8; 730 enaddr[3] = csr; 731 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 732 csr = EE_READ(sc, 0x04); 733 enaddr[4] = csr >> 24; 734 enaddr[5] = csr >> 16; 735 aprint_normal_dev(sc->sc_dev, 736 "Ethernet address %s\n", ether_sprintf(enaddr)); 737 738 sc->sc_mdclk = get_mdioclk(sc->sc_freq); /* 5:2 clk control */ 739 740 if (sc->sc_ucodeloaded == 0) 741 loaducode(sc); 742 743 mii->mii_ifp = ifp; 744 mii->mii_readreg = mii_readreg; 745 mii->mii_writereg = mii_writereg; 746 mii->mii_statchg = mii_statchg; 747 748 sc->sc_ethercom.ec_mii = mii; 749 ifmedia_init(ifm, 0, ether_mediachange, scx_ifmedia_sts); 750 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 751 MII_OFFSET_ANY, MIIF_DOPAUSE); 752 if (LIST_FIRST(&mii->mii_phys) == NULL) { 753 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 754 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 755 } else 756 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 757 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 758 759 /* 760 * Allocate the control data structures, and create and load the 761 * DMA map for it. 762 */ 763 error = bus_dmamem_alloc(sc->sc_dmat32, 764 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 765 if (error != 0) { 766 aprint_error_dev(sc->sc_dev, 767 "unable to allocate control data, error = %d\n", error); 768 goto fail_0; 769 } 770 error = bus_dmamem_map(sc->sc_dmat32, &seg, nseg, 771 sizeof(struct control_data), (void **)&sc->sc_control_data, 772 BUS_DMA_COHERENT); 773 if (error != 0) { 774 aprint_error_dev(sc->sc_dev, 775 "unable to map control data, error = %d\n", error); 776 goto fail_1; 777 } 778 error = bus_dmamap_create(sc->sc_dmat32, 779 sizeof(struct control_data), 1, 780 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 781 if (error != 0) { 782 aprint_error_dev(sc->sc_dev, 783 "unable to create control data DMA map, " 784 "error = %d\n", error); 785 goto fail_2; 786 } 787 error = bus_dmamap_load(sc->sc_dmat32, sc->sc_cddmamap, 788 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 789 if (error != 0) { 790 aprint_error_dev(sc->sc_dev, 791 "unable to load control data DMA map, error = %d\n", 792 error); 793 goto fail_3; 794 } 795 for (i = 0; i < MD_TXQUEUELEN; i++) { 796 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 797 MD_NTXSEGS, MCLBYTES, 0, 0, 798 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 799 aprint_error_dev(sc->sc_dev, 800 "unable to create tx DMA map %d, error = %d\n", 801 i, error); 802 goto fail_4; 803 } 804 } 805 for (i = 0; i < MD_NRXDESC; i++) { 806 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 807 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 808 aprint_error_dev(sc->sc_dev, 809 "unable to create rx DMA map %d, error = %d\n", 810 i, error); 811 goto fail_5; 812 } 813 sc->sc_rxsoft[i].rxs_mbuf = NULL; 814 } 815 sc->sc_seg = seg; 816 sc->sc_nseg = nseg; 817 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 818 819 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 820 ifp->if_softc = sc; 821 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 822 ifp->if_ioctl = scx_ioctl; 823 ifp->if_start = scx_start; 824 ifp->if_watchdog = scx_watchdog; 825 ifp->if_init = scx_init; 826 ifp->if_stop = scx_stop; 827 IFQ_SET_READY(&ifp->if_snd); 828 829 sc->sc_flowflags = 0; 830 831 if_attach(ifp); 832 if_deferred_start_init(ifp, NULL); 833 ether_ifattach(ifp, enaddr); 834 835 callout_init(&sc->sc_callout, 0); 836 callout_setfunc(&sc->sc_callout, phy_tick, sc); 837 838 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 839 RND_TYPE_NET, RND_FLAG_DEFAULT); 840 841 return; 842 843 fail_5: 844 for (i = 0; i < MD_NRXDESC; i++) { 845 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 846 bus_dmamap_destroy(sc->sc_dmat, 847 sc->sc_rxsoft[i].rxs_dmamap); 848 } 849 fail_4: 850 for (i = 0; i < MD_TXQUEUELEN; i++) { 851 if (sc->sc_txsoft[i].txs_dmamap != NULL) 852 bus_dmamap_destroy(sc->sc_dmat, 853 sc->sc_txsoft[i].txs_dmamap); 854 } 855 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 856 fail_3: 857 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 858 fail_2: 859 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 860 sizeof(struct control_data)); 861 fail_1: 862 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 863 fail_0: 864 if (sc->sc_phandle) 865 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 866 else 867 acpi_intr_disestablish(sc->sc_ih); 868 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 869 return; 870 } 871 872 static void 873 scx_reset(struct scx_softc *sc) 874 { 875 int loop = 0, busy; 876 877 mac_write(sc, GMACOMR, 0); 878 mac_write(sc, GMACBMR, BMR_RST); 879 do { 880 DELAY(1); 881 busy = mac_read(sc, GMACBMR) & BMR_RST; 882 } while (++loop < 3000 && busy); 883 mac_write(sc, GMACBMR, _BMR); 884 mac_write(sc, GMACAFR, 0); 885 886 CSR_WRITE(sc, CLKEN, CLK_ALL); /* distribute clock sources */ 887 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 888 CSR_WRITE(sc, SWRESET, 1U<<31); /* manifest run */ 889 CSR_WRITE(sc, COMINIT, 3); /* DB|CLS */ 890 891 mac_write(sc, GMACEVCTL, 1); 892 } 893 894 static int 895 scx_init(struct ifnet *ifp) 896 { 897 struct scx_softc *sc = ifp->if_softc; 898 const uint8_t *ea = CLLADDR(ifp->if_sadl); 899 uint32_t csr; 900 int i, error; 901 902 /* Cancel pending I/O. */ 903 scx_stop(ifp, 0); 904 905 /* Reset the chip to a known state. */ 906 scx_reset(sc); 907 908 /* build sane Tx */ 909 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 910 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 911 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 912 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 913 sc->sc_txfree = MD_NTXDESC; 914 sc->sc_txnext = 0; 915 for (i = 0; i < MD_TXQUEUELEN; i++) 916 sc->sc_txsoft[i].txs_mbuf = NULL; 917 sc->sc_txsfree = MD_TXQUEUELEN; 918 sc->sc_txsnext = 0; 919 sc->sc_txsdirty = 0; 920 921 /* load Rx descriptors with fresh mbuf */ 922 for (i = 0; i < MD_NRXDESC; i++) { 923 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 924 if ((error = add_rxbuf(sc, i)) != 0) { 925 aprint_error_dev(sc->sc_dev, 926 "unable to allocate or map rx " 927 "buffer %d, error = %d\n", 928 i, error); 929 rxdrain(sc); 930 goto out; 931 } 932 } 933 else 934 SCX_INIT_RXDESC(sc, i); 935 } 936 sc->sc_rxdescs[MD_NRXDESC - 1].r0 = R0_EOD; 937 sc->sc_rxptr = 0; 938 sc->sc_rxptr = 0; 939 940 /* set my address in perfect match slot 0. little endin order */ 941 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 942 mac_write(sc, GMACMAL0, csr); 943 csr = (ea[5] << 8) | ea[4]; 944 mac_write(sc, GMACMAH0, csr); 945 946 /* accept multicast frame or run promisc mode */ 947 scx_set_rcvfilt(sc); 948 949 /* set current media */ 950 if ((error = ether_mediachange(ifp)) != 0) 951 goto out; 952 953 /* XXX 32 bit paddr XXX hand Tx/Rx rings to HW XXX */ 954 mac_write(sc, GMACTDLA, SCX_CDTXADDR(sc, 0)); 955 mac_write(sc, GMACRDLA, SCX_CDRXADDR(sc, 0)); 956 957 /* kick to start GMAC engine */ 958 CSR_WRITE(sc, RXI_CLR, ~0); 959 CSR_WRITE(sc, TXI_CLR, ~0); 960 csr = mac_read(sc, GMACOMR); 961 mac_write(sc, GMACOMR, csr | OMR_RS | OMR_ST); 962 963 ifp->if_flags |= IFF_RUNNING; 964 ifp->if_flags &= ~IFF_OACTIVE; 965 966 /* start one second timer */ 967 callout_schedule(&sc->sc_callout, hz); 968 out: 969 return error; 970 } 971 972 static void 973 scx_stop(struct ifnet *ifp, int disable) 974 { 975 struct scx_softc *sc = ifp->if_softc; 976 977 /* Stop the one second clock. */ 978 callout_stop(&sc->sc_callout); 979 980 /* Down the MII. */ 981 mii_down(&sc->sc_mii); 982 983 /* Mark the interface down and cancel the watchdog timer. */ 984 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 985 ifp->if_timer = 0; 986 } 987 988 static int 989 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 990 { 991 struct scx_softc *sc = ifp->if_softc; 992 struct ifreq *ifr = (struct ifreq *)data; 993 struct ifmedia *ifm = &sc->sc_mii.mii_media; 994 int s, error; 995 996 s = splnet(); 997 998 switch (cmd) { 999 case SIOCSIFMEDIA: 1000 /* Flow control requires full-duplex mode. */ 1001 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1002 (ifr->ifr_media & IFM_FDX) == 0) 1003 ifr->ifr_media &= ~IFM_ETH_FMASK; 1004 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1005 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1006 /* We can do both TXPAUSE and RXPAUSE. */ 1007 ifr->ifr_media |= 1008 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1009 } 1010 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1011 } 1012 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 1013 break; 1014 default: 1015 error = ether_ioctl(ifp, cmd, data); 1016 if (error != ENETRESET) 1017 break; 1018 error = 0; 1019 if (cmd == SIOCSIFCAP) 1020 error = (*ifp->if_init)(ifp); 1021 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1022 ; 1023 else if (ifp->if_flags & IFF_RUNNING) { 1024 /* 1025 * Multicast list has changed; set the hardware filter 1026 * accordingly. 1027 */ 1028 scx_set_rcvfilt(sc); 1029 } 1030 break; 1031 } 1032 1033 splx(s); 1034 return error; 1035 } 1036 1037 static void 1038 scx_set_rcvfilt(struct scx_softc *sc) 1039 { 1040 struct ethercom * const ec = &sc->sc_ethercom; 1041 struct ifnet * const ifp = &ec->ec_if; 1042 struct ether_multistep step; 1043 struct ether_multi *enm; 1044 uint32_t mchash[2]; /* 2x 32 = 64 bit */ 1045 uint32_t csr, crc; 1046 int i; 1047 1048 csr = mac_read(sc, GMACAFR); 1049 csr &= ~(AFR_PR | AFR_PM | AFR_MHTE | AFR_HPF); 1050 mac_write(sc, GMACAFR, csr); 1051 1052 /* clear 15 entry supplimental perfect match filter */ 1053 for (i = 1; i < 16; i++) 1054 mac_write(sc, GMACMAH(i), 0); 1055 /* build 64 bit multicast hash filter */ 1056 crc = mchash[1] = mchash[0] = 0; 1057 1058 ETHER_LOCK(ec); 1059 if (ifp->if_flags & IFF_PROMISC) { 1060 ec->ec_flags |= ETHER_F_ALLMULTI; 1061 ETHER_UNLOCK(ec); 1062 /* run promisc. mode */ 1063 csr |= AFR_PR; 1064 goto update; 1065 } 1066 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1067 ETHER_FIRST_MULTI(step, ec, enm); 1068 i = 1; /* slot 0 is occupied */ 1069 while (enm != NULL) { 1070 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1071 /* 1072 * We must listen to a range of multicast addresses. 1073 * For now, just accept all multicasts, rather than 1074 * trying to set only those filter bits needed to match 1075 * the range. (At this time, the only use of address 1076 * ranges is for IP multicast routing, for which the 1077 * range is big enough to require all bits set.) 1078 */ 1079 ec->ec_flags |= ETHER_F_ALLMULTI; 1080 ETHER_UNLOCK(ec); 1081 /* accept all multi */ 1082 csr |= AFR_PM; 1083 goto update; 1084 } 1085 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 1086 if (i < 16) { 1087 /* use 15 entry perfect match filter */ 1088 uint32_t addr; 1089 uint8_t *ep = enm->enm_addrlo; 1090 addr = (ep[3] << 24) | (ep[2] << 16) 1091 | (ep[1] << 8) | ep[0]; 1092 mac_write(sc, GMACMAL(i), addr); 1093 addr = (ep[5] << 8) | ep[4]; 1094 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1095 } else { 1096 /* use hash table when too many */ 1097 /* bit_reserve_32(~crc) !? */ 1098 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1099 /* 1(31) 5(30:26) bit sampling */ 1100 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 1101 } 1102 ETHER_NEXT_MULTI(step, enm); 1103 i++; 1104 } 1105 ETHER_UNLOCK(ec); 1106 if (crc) 1107 csr |= AFR_MHTE; 1108 csr |= AFR_HPF; /* use hash+perfect */ 1109 mac_write(sc, GMACMHTH, mchash[1]); 1110 mac_write(sc, GMACMHTL, mchash[0]); 1111 update: 1112 /* With PR or PM, MHTE/MHTL/MHTH are never consulted. really? */ 1113 mac_write(sc, GMACAFR, csr); 1114 return; 1115 } 1116 1117 static void 1118 scx_start(struct ifnet *ifp) 1119 { 1120 struct scx_softc *sc = ifp->if_softc; 1121 struct mbuf *m0, *m; 1122 struct scx_txsoft *txs; 1123 bus_dmamap_t dmamap; 1124 int error, nexttx, lasttx, ofree, seg; 1125 uint32_t tdes0; 1126 1127 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1128 return; 1129 1130 /* Remember the previous number of free descriptors. */ 1131 ofree = sc->sc_txfree; 1132 1133 /* 1134 * Loop through the send queue, setting up transmit descriptors 1135 * until we drain the queue, or use up all available transmit 1136 * descriptors. 1137 */ 1138 for (;;) { 1139 IFQ_POLL(&ifp->if_snd, m0); 1140 if (m0 == NULL) 1141 break; 1142 1143 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1144 txreap(sc); 1145 if (sc->sc_txsfree == 0) 1146 break; 1147 } 1148 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1149 dmamap = txs->txs_dmamap; 1150 1151 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1152 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1153 if (error) { 1154 if (error == EFBIG) { 1155 aprint_error_dev(sc->sc_dev, 1156 "Tx packet consumes too many " 1157 "DMA segments, dropping...\n"); 1158 IFQ_DEQUEUE(&ifp->if_snd, m0); 1159 m_freem(m0); 1160 continue; 1161 } 1162 /* Short on resources, just stop for now. */ 1163 break; 1164 } 1165 1166 if (dmamap->dm_nsegs > sc->sc_txfree) { 1167 /* 1168 * Not enough free descriptors to transmit this 1169 * packet. We haven't committed anything yet, 1170 * so just unload the DMA map, put the packet 1171 * back on the queue, and punt. Notify the upper 1172 * layer that there are not more slots left. 1173 */ 1174 ifp->if_flags |= IFF_OACTIVE; 1175 bus_dmamap_unload(sc->sc_dmat, dmamap); 1176 break; 1177 } 1178 1179 IFQ_DEQUEUE(&ifp->if_snd, m0); 1180 1181 /* 1182 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1183 */ 1184 1185 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1186 BUS_DMASYNC_PREWRITE); 1187 1188 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1189 lasttx = -1; 1190 for (nexttx = sc->sc_txnext, seg = 0; 1191 seg < dmamap->dm_nsegs; 1192 seg++, nexttx = MD_NEXTTX(nexttx)) { 1193 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1194 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1195 /* 1196 * If this is the first descriptor we're 1197 * enqueueing, don't set the OWN bit just 1198 * yet. That could cause a race condition. 1199 * We'll do it below. 1200 */ 1201 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1202 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1203 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1204 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1205 (15 << T0_TRID) | T0_PT | 1206 sc->sc_t0coso | T0_TRS; 1207 tdes0 = T0_OWN; /* 2nd and other segments */ 1208 lasttx = nexttx; 1209 } 1210 /* 1211 * Outgoing NFS mbuf must be unloaded when Tx completed. 1212 * Without T1_IC NFS mbuf is left unack'ed for excessive 1213 * time and NFS stops to proceed until scx_watchdog() 1214 * calls txreap() to reclaim the unack'ed mbuf. 1215 * It's painful to traverse every mbuf chain to determine 1216 * whether someone is waiting for Tx completion. 1217 */ 1218 m = m0; 1219 do { 1220 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1221 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1222 break; 1223 } 1224 } while ((m = m->m_next) != NULL); 1225 1226 /* Write deferred 1st segment T0_OWN at the final stage */ 1227 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1228 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1229 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1230 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1231 1232 /* Tell DMA start transmit */ 1233 mac_write(sc, GMACTPD, 1); 1234 1235 txs->txs_mbuf = m0; 1236 txs->txs_firstdesc = sc->sc_txnext; 1237 txs->txs_lastdesc = lasttx; 1238 txs->txs_ndesc = dmamap->dm_nsegs; 1239 1240 sc->sc_txfree -= txs->txs_ndesc; 1241 sc->sc_txnext = nexttx; 1242 sc->sc_txsfree--; 1243 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1244 /* 1245 * Pass the packet to any BPF listeners. 1246 */ 1247 bpf_mtap(ifp, m0, BPF_D_OUT); 1248 } 1249 1250 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1251 /* No more slots left; notify upper layer. */ 1252 ifp->if_flags |= IFF_OACTIVE; 1253 } 1254 if (sc->sc_txfree != ofree) { 1255 /* Set a watchdog timer in case the chip flakes out. */ 1256 ifp->if_timer = 5; 1257 } 1258 } 1259 1260 static void 1261 scx_watchdog(struct ifnet *ifp) 1262 { 1263 struct scx_softc *sc = ifp->if_softc; 1264 1265 /* 1266 * Since we're not interrupting every packet, sweep 1267 * up before we report an error. 1268 */ 1269 txreap(sc); 1270 1271 if (sc->sc_txfree != MD_NTXDESC) { 1272 aprint_error_dev(sc->sc_dev, 1273 "device timeout (txfree %d txsfree %d txnext %d)\n", 1274 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1275 if_statinc(ifp, if_oerrors); 1276 1277 /* Reset the interface. */ 1278 scx_init(ifp); 1279 } 1280 1281 scx_start(ifp); 1282 } 1283 1284 static int 1285 scx_intr(void *arg) 1286 { 1287 struct scx_softc *sc = arg; 1288 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1289 1290 (void)ifp; 1291 /* XXX decode interrupt cause to pick isr() XXX */ 1292 rxintr(sc); 1293 txreap(sc); 1294 return 1; 1295 } 1296 1297 static void 1298 txreap(struct scx_softc *sc) 1299 { 1300 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1301 struct scx_txsoft *txs; 1302 uint32_t txstat; 1303 int i; 1304 1305 ifp->if_flags &= ~IFF_OACTIVE; 1306 1307 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1308 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1309 txs = &sc->sc_txsoft[i]; 1310 1311 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1312 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1313 1314 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1315 if (txstat & T0_OWN) /* desc is still in use */ 1316 break; 1317 1318 /* There is no way to tell transmission status per frame */ 1319 1320 if_statinc(ifp, if_opackets); 1321 1322 sc->sc_txfree += txs->txs_ndesc; 1323 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1324 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1325 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1326 m_freem(txs->txs_mbuf); 1327 txs->txs_mbuf = NULL; 1328 } 1329 sc->sc_txsdirty = i; 1330 if (sc->sc_txsfree == MD_TXQUEUELEN) 1331 ifp->if_timer = 0; 1332 } 1333 1334 static void 1335 rxintr(struct scx_softc *sc) 1336 { 1337 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1338 struct scx_rxsoft *rxs; 1339 struct mbuf *m; 1340 uint32_t rxstat; 1341 int i, len; 1342 1343 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1344 rxs = &sc->sc_rxsoft[i]; 1345 1346 SCX_CDRXSYNC(sc, i, 1347 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1348 1349 rxstat = sc->sc_rxdescs[i].r0; 1350 if (rxstat & R0_OWN) /* desc is left empty */ 1351 break; 1352 1353 /* R0_FS | R0_LS must have been marked for this desc */ 1354 1355 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1356 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1357 1358 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1359 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1360 m = rxs->rxs_mbuf; 1361 1362 if (add_rxbuf(sc, i) != 0) { 1363 if_statinc(ifp, if_ierrors); 1364 SCX_INIT_RXDESC(sc, i); 1365 bus_dmamap_sync(sc->sc_dmat, 1366 rxs->rxs_dmamap, 0, 1367 rxs->rxs_dmamap->dm_mapsize, 1368 BUS_DMASYNC_PREREAD); 1369 continue; 1370 } 1371 1372 m_set_rcvif(m, ifp); 1373 m->m_pkthdr.len = m->m_len = len; 1374 1375 if (rxstat & R0_CSUM) { 1376 uint32_t csum = M_CSUM_IPv4; 1377 if (rxstat & R0_CERR) 1378 csum |= M_CSUM_IPv4_BAD; 1379 m->m_pkthdr.csum_flags |= csum; 1380 } 1381 if_percpuq_enqueue(ifp->if_percpuq, m); 1382 } 1383 sc->sc_rxptr = i; 1384 } 1385 1386 static int 1387 add_rxbuf(struct scx_softc *sc, int i) 1388 { 1389 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1390 struct mbuf *m; 1391 int error; 1392 1393 MGETHDR(m, M_DONTWAIT, MT_DATA); 1394 if (m == NULL) 1395 return ENOBUFS; 1396 1397 MCLGET(m, M_DONTWAIT); 1398 if ((m->m_flags & M_EXT) == 0) { 1399 m_freem(m); 1400 return ENOBUFS; 1401 } 1402 1403 if (rxs->rxs_mbuf != NULL) 1404 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1405 1406 rxs->rxs_mbuf = m; 1407 1408 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1409 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1410 if (error) { 1411 aprint_error_dev(sc->sc_dev, 1412 "can't load rx DMA map %d, error = %d\n", i, error); 1413 panic("add_rxbuf"); 1414 } 1415 1416 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1417 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1418 SCX_INIT_RXDESC(sc, i); 1419 1420 return 0; 1421 } 1422 1423 static void 1424 rxdrain(struct scx_softc *sc) 1425 { 1426 struct scx_rxsoft *rxs; 1427 int i; 1428 1429 for (i = 0; i < MD_NRXDESC; i++) { 1430 rxs = &sc->sc_rxsoft[i]; 1431 if (rxs->rxs_mbuf != NULL) { 1432 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1433 m_freem(rxs->rxs_mbuf); 1434 rxs->rxs_mbuf = NULL; 1435 } 1436 } 1437 } 1438 1439 void 1440 mii_statchg(struct ifnet *ifp) 1441 { 1442 struct scx_softc *sc = ifp->if_softc; 1443 struct mii_data *mii = &sc->sc_mii; 1444 const int Mbps[4] = { 10, 100, 1000, 0 }; 1445 uint32_t miisr, mcr, fcr; 1446 int spd; 1447 1448 /* decode MIISR register value */ 1449 miisr = mac_read(sc, GMACMIISR); 1450 spd = Mbps[(miisr >> 1) & 03]; 1451 #if 1 1452 printf("MII link status (0x%x) %s", 1453 miisr, (miisr & 8) ? "up" : "down"); 1454 if (miisr & 8) { 1455 printf(" spd%d", spd); 1456 if (miisr & 01) 1457 printf(",full-duplex"); 1458 } 1459 printf("\n"); 1460 #endif 1461 /* Get flow control negotiation result. */ 1462 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1463 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1464 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1465 1466 /* Adjust speed 1000/100/10. */ 1467 mcr = mac_read(sc, GMACMCR); 1468 if (spd == 1000) 1469 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1470 else { 1471 if (spd == 100 && sc->sc_100mii) 1472 mcr |= MCR_SPD100; 1473 mcr |= MCR_USEMII; 1474 } 1475 mcr |= MCR_CST | MCR_JE; 1476 if (sc->sc_100mii == 0) 1477 mcr |= MCR_IBN; 1478 1479 /* Adjust duplexity and PAUSE flow control. */ 1480 mcr &= ~MCR_USEFDX; 1481 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1482 if (miisr & 01) { 1483 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1484 fcr |= FCR_TFE; 1485 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1486 fcr |= FCR_RFE; 1487 mcr |= MCR_USEFDX; 1488 } 1489 mac_write(sc, GMACMCR, mcr); 1490 mac_write(sc, GMACFCR, fcr); 1491 1492 printf("%ctxfe, %crxfe\n", 1493 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1494 } 1495 1496 static void 1497 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1498 { 1499 struct scx_softc *sc = ifp->if_softc; 1500 struct mii_data *mii = &sc->sc_mii; 1501 1502 mii_pollstat(mii); 1503 ifmr->ifm_status = mii->mii_media_status; 1504 ifmr->ifm_active = sc->sc_flowflags | 1505 (mii->mii_media_active & ~IFM_ETH_FMASK); 1506 } 1507 1508 static int 1509 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1510 { 1511 struct scx_softc *sc = device_private(self); 1512 uint32_t miia; 1513 int ntries; 1514 1515 #define CLK_150_250M (1<<2) 1516 uint32_t clk = CSR_READ(sc, CLKEN); 1517 CSR_WRITE(sc, CLKEN, clk | CLK_G); 1518 1519 miia = (phy << GAR_PHY) | (reg << GAR_REG) | CLK_150_250M; 1520 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1521 for (ntries = 0; ntries < 1000; ntries++) { 1522 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1523 goto unbusy; 1524 DELAY(1); 1525 } 1526 return ETIMEDOUT; 1527 unbusy: 1528 *val = mac_read(sc, GMACGDR); 1529 return 0; 1530 } 1531 1532 static int 1533 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1534 { 1535 struct scx_softc *sc = device_private(self); 1536 uint32_t miia; 1537 uint16_t dummy; 1538 int ntries; 1539 1540 uint32_t clk = CSR_READ(sc, CLKEN); 1541 CSR_WRITE(sc, CLKEN, clk | CLK_G); 1542 1543 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1544 mac_write(sc, GMACGDR, val); 1545 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1546 for (ntries = 0; ntries < 1000; ntries++) { 1547 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1548 goto unbusy; 1549 DELAY(1); 1550 } 1551 return ETIMEDOUT; 1552 unbusy: 1553 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1554 return 0; 1555 } 1556 1557 static void 1558 phy_tick(void *arg) 1559 { 1560 struct scx_softc *sc = arg; 1561 struct mii_data *mii = &sc->sc_mii; 1562 int s; 1563 1564 s = splnet(); 1565 mii_tick(mii); 1566 splx(s); 1567 #ifdef SCX_EVENT_COUNTERS /* if tally counter details are made clear */ 1568 #endif 1569 callout_schedule(&sc->sc_callout, hz); 1570 } 1571 1572 /* 1573 * 3 independent uengines exist to process host2media, media2host and 1574 * packet data flows. 1575 */ 1576 static void 1577 loaducode(struct scx_softc *sc) 1578 { 1579 uint32_t up, lo, sz; 1580 uint64_t addr; 1581 1582 sc->sc_ucodeloaded = 1; 1583 1584 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1585 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1586 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1587 sz *= 4; 1588 addr = ((uint64_t)up << 32) | lo; 1589 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1590 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1591 1592 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1593 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1594 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1595 sz *= 4; 1596 addr = ((uint64_t)up << 32) | lo; 1597 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1598 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1599 1600 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1601 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1602 sz *= 4; 1603 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1604 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1605 } 1606 1607 static void 1608 injectucode(struct scx_softc *sc, int port, 1609 bus_addr_t addr, bus_size_t size) 1610 { 1611 bus_space_handle_t bsh; 1612 bus_size_t off; 1613 uint32_t ucode; 1614 1615 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1616 aprint_error_dev(sc->sc_dev, 1617 "eeprom map failure for ucode port 0x%x\n", port); 1618 return; 1619 } 1620 for (off = 0; off < size; off += 4) { 1621 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1622 CSR_WRITE(sc, port, ucode); 1623 } 1624 bus_space_unmap(sc->sc_st, bsh, size); 1625 } 1626 1627 /* bit selection to determine MDIO speed */ 1628 1629 static int 1630 get_mdioclk(uint32_t freq) 1631 { 1632 1633 const struct { 1634 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 1635 } mdioclk[] = { 1636 { 35, 2 }, /* 25-35 MHz */ 1637 { 60, 3 }, /* 35-60 MHz */ 1638 { 100, 0 }, /* 60-100 MHz */ 1639 { 150, 1 }, /* 100-150 MHz */ 1640 { 250, 4 }, /* 150-250 MHz */ 1641 { 300, 5 }, /* 250-300 MHz */ 1642 }; 1643 int i; 1644 1645 freq /= 1000 * 1000; 1646 /* convert MDIO clk to a divisor value */ 1647 if (freq < mdioclk[0].freq) 1648 return mdioclk[0].bit; 1649 for (i = 1; i < __arraycount(mdioclk); i++) { 1650 if (freq < mdioclk[i].freq) 1651 return mdioclk[i-1].bit; 1652 } 1653 return mdioclk[__arraycount(mdioclk) - 1].bit << GAR_CTL; 1654 } 1655
Indexes created Sat Sep 27 14:09:57 GMT 2025