if_scx.c revision 1.27
1 /* $NetBSD: if_scx.c,v 1.27 2021/12/16 11:36:25 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 /* 34 * Socionext SC2A11 SynQuacer NetSec GbE driver 35 * 36 * Multiple Tx and Rx queues exist inside and dedicated descriptor 37 * fields specifies which queue is to use. Three internal micro-processors 38 * to handle incoming frames, outgoing frames and packet data crypto 39 * processing. uP programs are stored in an external flash memory and 40 * have to be loaded by device driver. 41 * NetSec uses Synopsys DesignWare Core EMAC. DWC implementation 42 * register (0x20) is known to have 0x10.36 and feature register (0x1058) 43 * to report XX.XX. 44 */ 45 46 #define NOT_MP_SAFE 0 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.27 2021/12/16 11:36:25 nisimura Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/bus.h> 53 #include <sys/intr.h> 54 #include <sys/device.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/errno.h> 59 #include <sys/rndsource.h> 60 #include <sys/kernel.h> 61 #include <sys/systm.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_dl.h> 66 #include <net/if_ether.h> 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <net/bpf.h> 70 71 #include <dev/fdt/fdtvar.h> 72 #include <dev/acpi/acpireg.h> 73 #include <dev/acpi/acpivar.h> 74 #include <dev/acpi/acpi_intr.h> 75 76 /* SC2A11 GbE 64-bit paddr descriptor */ 77 struct tdes { 78 uint32_t t0, t1, t2, t3; 79 }; 80 81 struct rdes { 82 uint32_t r0, r1, r2, r3; 83 }; 84 85 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 86 #define T0_EOD (1U<<30) /* end of descriptor array */ 87 #define T0_DRID (24) /* 29:24 desc ring id */ 88 #define T0_PT (1U<<21) /* 23:21 "pass-through" */ 89 #define T0_TDRID (16) /* 20:16 target desc ring id: GMAC=15 */ 90 #define T0_FS (1U<<9) /* first segment of frame */ 91 #define T0_LS (1U<<8) /* last segment of frame */ 92 #define T0_CSUM (1U<<7) /* enable check sum offload */ 93 #define T0_TSO (1U<<6) /* enable TCP segment offload */ 94 #define T0_TRS (1U<<4) /* 5:4 "TRS" */ 95 /* T1 frame segment address 63:32 */ 96 /* T2 frame segment address 31:0 */ 97 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */ 98 99 #define R0_OWN (1U<<31) /* desc is empty */ 100 #define R0_EOD (1U<<30) /* end of descriptor array */ 101 #define R0_SDRID (24) /* 29:24 source desc ring id */ 102 #define R0_FR (1U<<23) /* found fragmented */ 103 #define R0_ER (1U<<21) /* Rx error indication */ 104 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 105 #define R0_TDRID (12) /* 15:12 target desc ring id */ 106 #define R0_FS (1U<<9) /* first segment of frame */ 107 #define R0_LS (1U<<8) /* last segment of frame */ 108 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 109 #define R0_CERR (2U<<6) /* 0: undone, 1: found ok, 2: bad */ 110 /* R1 frame address 63:32 */ 111 /* R2 frame address 31:0 */ 112 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 113 114 /* 115 * SC2A11 registers. 0x100 - 1204 116 */ 117 #define SWRESET 0x104 118 #define SRST_RUN (1U<<31) /* instruct start, 0 to stop */ 119 #define COMINIT 0x120 120 #define INIT_DB (1U<<2) /* ???; self clear when done */ 121 #define INIT_CLS (1U<<1) /* ???; self clear when done */ 122 #define PKTCTRL 0x140 /* pkt engine control */ 123 #define MODENRM (1U<<28) /* change mode to normal */ 124 #define ENJUMBO (1U<<27) /* allow jumbo frame */ 125 #define RPTCSUMERR (1U<<3) /* log Rx checksum error */ 126 #define RPTHDCOMP (1U<<2) /* log HD imcomplete condition */ 127 #define RPTHDERR (1U<<1) /* log HD error */ 128 #define DROPNOMATCH (1U<<0) /* drop no match frames */ 129 #define xINTSR 0x200 /* aggregated interrupt status report */ 130 #define IRQ_RX (1U<<1) /* top level Rx interrupt */ 131 #define IRQ_TX (1U<<0) /* top level Rx interrupt */ 132 #define IRQ_UCODE (1U<<20) /* ucode load completed */ 133 #define xINTAEN 0x204 /* INT_A enable */ 134 #define xINTAE_SET 0x234 /* bit to set */ 135 #define xINTAE_CLR 0x238 /* bit to clr */ 136 #define xINTBEN 0x23c /* INT_B enable */ 137 #define xINTBE_SET 0x240 /* bit to set */ 138 #define xINTBE_CLR 0x244 /* bit to clr */ 139 #define TXISR 0x400 /* transmit status */ 140 #define TXIEN 0x404 /* tx interrupt enable */ 141 #define TXIE_SET 0x428 /* bit to set */ 142 #define TXIE_CLR 0x42c /* bit to clr */ 143 #define TXI_NTOWNR (1U<<17) /* ready desc got empty */ 144 #define TXI_TR_ERR (1U<<16) /* tx error */ 145 #define TXI_TXDONE (1U<<15) /* tx completed */ 146 #define TXI_TMREXP (1U<<14) /* coalesce timer expired */ 147 #define RXISR 0x440 /* receipt status */ 148 #define RXIEN 0x444 /* rx interrupt enable */ 149 #define RXIE_SET 0x468 /* bit to set */ 150 #define RXIE_CLR 0x46c /* bit to clr */ 151 #define RXI_RC_ERR (1U<<16) /* rx error */ 152 #define RXI_PKTCNT (1U<<15) /* rx counter has new value report */ 153 #define RXI_TMREXP (1U<<14) /* coalesce timer expired */ 154 #define TDBA_LO 0x408 /* tdes array base addr 31:0 */ 155 #define TDBA_HI 0x434 /* tdes array base addr 63:32 */ 156 #define RDBA_LO 0x448 /* rdes array base addr 31:0 */ 157 #define RDBA_HI 0x474 /* rdes array base addr 63:32 */ 158 /* 13 pairs of special purpose desc array address registers exit */ 159 #define TXCONF 0x430 160 #define RXCONF 0x470 161 #define DESCNF_UP (1U<<31) /* up-and-running */ 162 #define DESCNF_CHRST (1U<<30) /* channel reset */ 163 #define DESCNF_TMR (1U<<4) /* coalesce timer mode select */ 164 #define DESCNF_LE (1) /* little endian desc format */ 165 #define TXCOLMAX 0x410 /* tx intr coalesce upper bound */ 166 #define RXCOLMAX 0x454 /* rx intr coalesce upper bound */ 167 #define TXITIMER 0x420 /* coalesce timer usec, MSB to use */ 168 #define RXITIMER 0x460 /* coalesce timer usec, MSB to use */ 169 #define TXDONECNT 0x424 /* tx completion report, auto-clear */ 170 #define RXDONECNT 0x458 /* rx completion report, auto-clear */ 171 #define UCODE_H2M 0x210 /* host2media engine ucode port */ 172 #define UCODE_M2H 0x21c /* media2host engine ucode port */ 173 #define CORESTAT 0x218 /* engine run state */ 174 #define PKTSTOP (1U<<2) 175 #define M2HSTOP (1U<<1) 176 #define H2MSTOP (1U<<0) 177 #define DMACTL_H2M 0x214 /* host2media engine control */ 178 #define DMACTL_M2H 0x220 /* media2host engine control */ 179 #define DMACTL_STOP (1U<<0) /* instruct stop; self-clear */ 180 #define UCODE_PKT 0x0d0 /* packet engine ucode port */ 181 #define CLKEN 0x100 /* clock distribution enable */ 182 #define CLK_G (1U<<5) /* feed clk domain E */ 183 #define CLK_C (1U<<1) /* feed clk domain C */ 184 #define CLK_D (1U<<0) /* feed clk domain D */ 185 #define CLK_ALL 0x23 /* all above; 0x24 ??? 0x3f ??? */ 186 187 /* GMAC register indirect access. thru MACCMD/MACDATA operation */ 188 #define MACDATA 0x11c0 /* gmac register rd/wr data */ 189 #define MACCMD 0x11c4 /* gmac register operation */ 190 #define CMD_IOWR (1U<<28) /* write op */ 191 #define CMD_BUSY (1U<<31) /* busy bit */ 192 #define MACSTAT 0x1024 /* gmac status; ??? */ 193 #define MACINTE 0x1028 /* interrupt enable; ??? */ 194 195 #define FLOWTHR 0x11cc /* flow control threshold */ 196 /* 31:16 pause threshold, 15:0 resume threshold */ 197 #define INTF_SEL 0x11d4 /* ??? */ 198 199 #define DESC_INIT 0x11fc /* write 1 for desc init, SC */ 200 #define DESC_SRST 0x1204 /* write 1 for desc sw reset, SC */ 201 #define MODE_TRANS 0x500 /* mode change completion status */ 202 #define N2T_DONE (1U<<20) /* normal->taiki change completed */ 203 #define T2N_DONE (1U<<19) /* taiki->normal change completed */ 204 #define MACADRH 0x10c /* ??? */ 205 #define MACADRL 0x110 /* ??? */ 206 #define MCVER 0x22c /* micro controller version */ 207 #define HWVER 0x230 /* hardware version */ 208 209 /* 210 * GMAC registers are mostly identical to Synopsys DesignWare Core 211 * Ethernet. These must be handled by indirect access. 212 */ 213 #define GMACMCR 0x0000 /* MAC configuration */ 214 #define MCR_IBN (1U<<30) /* ??? */ 215 #define MCR_CST (1U<<25) /* strip CRC */ 216 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 217 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 218 #define MCR_IFG (7U<<17) /* 19:17 IFG value 0~7 */ 219 #define MCR_DRCS (1U<<16) /* ignore (G)MII HDX Tx error */ 220 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII (_PS) */ 221 #define MCR_SPD100 (1U<<14) /* force speed 100 (_FES) */ 222 #define MCR_DO (1U<<13) /* ??? don't receive my own Tx frames */ 223 #define MCR_LOOP (1U<<12) /* run loop back */ 224 #define MCR_USEFDX (1U<<11) /* force full duplex */ 225 #define MCR_IPCEN (1U<<10) /* handle checksum */ 226 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 227 #define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */ 228 #define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */ 229 #define MCR_PREA (3U) /* 1:0 preamble len. 0~2 */ 230 #define _MCR_FDX 0x0000280c /* XXX TBD */ 231 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 232 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 233 #define AFR_RA (1U<<31) /* accept all irrespective of filt. */ 234 #define AFR_HPF (1U<<10) /* hash+perfect filter, or hash only */ 235 #define AFR_SAF (1U<<9) /* source address filter */ 236 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 237 #define AFR_PCF (2U<<6) /* ??? */ 238 #define AFR_DBF (1U<<5) /* reject broadcast frame */ 239 #define AFR_PM (1U<<4) /* accept all multicast frame */ 240 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 241 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 242 #define AFR_UHTE (1U<<1) /* use hash table for unicast */ 243 #define AFR_PR (1U<<0) /* run promisc mode */ 244 #define GMACGAR 0x0010 /* MDIO operation */ 245 #define GAR_PHY (11) /* 15:11 mii phy */ 246 #define GAR_REG (6) /* 10:6 mii reg */ 247 #define GAR_CLK (2) /* 5:2 mdio clock tick ratio */ 248 #define GAR_IOWR (1U<<1) /* MDIO write op */ 249 #define GAR_BUSY (1U<<0) /* busy bit */ 250 #define GAR_MDIO_25_35MHZ 2 251 #define GAR_MDIO_35_60MHZ 3 252 #define GAR_MDIO_60_100MHZ 0 253 #define GAR_MDIO_100_150MHZ 1 254 #define GAR_MDIO_150_250MHZ 4 255 #define GAR_MDIO_250_300MHZ 5 256 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 257 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 258 /* 31:16 pause timer value, 5:4 pause timer threshold */ 259 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 260 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 261 #define GMACVTAG 0x001c /* VLAN tag control */ 262 #define GMACIMPL 0x0020 /* implementation number XX.YY */ 263 #define GMACLPIS 0x0030 /* ??? AXI LPI control */ 264 #define GMACLPIC 0x0034 /* ??? AXI LPI control */ 265 #define GMACISR 0x0038 /* interrupt status, clear when read */ 266 #define GMACIMR 0x003c /* interrupt enable */ 267 #define ISR_TS (1U<<9) /* time stamp operation detected */ 268 #define ISR_CO (1U<<7) /* Rx checksum offload completed */ 269 #define ISR_TX (1U<<6) /* Tx completed */ 270 #define ISR_RX (1U<<5) /* Rx completed */ 271 #define ISR_ANY (1U<<4) /* any of above 5-7 report */ 272 #define ISR_LC (1U<<0) /* link status change detected */ 273 #define GMACMAH0 0x0040 /* my own MAC address 47:32 */ 274 #define GMACMAL0 0x0044 /* my own MAC address 31:0 */ 275 #define GMACMAH(i) ((i)*8+0x40) /* supplemental MAC addr 1-15 */ 276 #define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */ 277 /* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */ 278 #define GMACAMAH(i) ((i)*8+0x800) /* supplemental MAC addr 16-31 */ 279 #define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */ 280 /* MAH bit-31: slot in use, no other bit is effective */ 281 #define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */ 282 #define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */ 283 #define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */ 284 #define GMACVHT 0x0588 /* 16-bit VLAN tag hash */ 285 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 286 /* 3: link up detected, 2:1 resolved speed (0/1/2), 1: fdx detected */ 287 288 /* 0x0700 - 0734 ??? */ 289 290 #define GMACBMR 0x1000 /* DMA bus mode control */ 291 /* 24 4PBL 8??? 292 * 23 USP 293 * 22:17 RPBL 294 * 16 fixed burst 295 * 15:14 priority between Rx and Tx 296 * 3 rxtx ratio 41 297 * 2 rxtx ratio 31 298 * 1 rxtx ratio 21 299 * 0 rxtx ratio 11 300 * 13:8 PBL possible DMA burst length 301 * 7 alternative des8 302 * 0 GMAC reset op. self-clear 303 */ 304 #define _BMR 0x00412080 /* XXX TBD */ 305 #define _BMR0 0x00020181 /* XXX TBD */ 306 #define BMR_RST (1) /* reset op. self clear when done */ 307 #define GMACTPD 0x1004 /* write any to resume tdes */ 308 #define GMACRPD 0x1008 /* write any to resume rdes */ 309 #define GMACRDLA 0x100c /* rdes base address 32bit paddr */ 310 #define GMACTDLA 0x1010 /* tdes base address 32bit paddr */ 311 #define _RDLA 0x18000 /* system RAM for GMAC rdes */ 312 #define _TDLA 0x1c000 /* system RAM for GMAC tdes */ 313 #define GMACDSR 0x1014 /* DMA status detail report; W1C */ 314 #define GMACOMR 0x1018 /* DMA operation mode */ 315 #define OMR_TSF (1U<<25) /* 1: Tx store&forword, 0: immed. */ 316 #define OMR_RSF (1U<<21) /* 1: Rx store&forward, 0: immed. */ 317 #define OMR_ST (1U<<13) /* run Tx DMA engine, 0 to stop */ 318 #define OMR_EFC (1U<<8) /* transmit PAUSE to throttle Rx lvl. */ 319 #define OMR_FEF (1U<<7) /* allow to receive error frames */ 320 #define OMR_SR (1U<<1) /* run Rx DMA engine, 0 to stop */ 321 #define GMACIE 0x101c /* interrupt enable */ 322 #define GMACEVCS 0x1020 /* missed frame or ovf detected */ 323 #define GMACRWDT 0x1024 /* receive watchdog timer count */ 324 #define GMACAXIB 0x1028 /* AXI bus mode control */ 325 #define GMACAXIS 0x102c /* AXI status report */ 326 /* 0x1048 current tx desc address */ 327 /* 0x104c current rx desc address */ 328 /* 0x1050 current tx buffer address */ 329 /* 0x1054 current rx buffer address */ 330 #define HWFEA 0x1058 /* DWC feature report */ 331 332 #define GMACEVCTL 0x0100 /* event counter control */ 333 #define EVC_FHP (1U<<5) /* full-half preset */ 334 #define EVC_CP (1U<<4) /* counters preset */ 335 #define EVC_MCF (1U<<3) /* MMC counter freeze */ 336 #define EVC_ROR (1U<<2) /* auto-zero on counter read */ 337 #define EVC_CSR (1U<<1) /* counter stop rollover */ 338 #define EVC_CR (1U<<0) /* reset counters */ 339 #define GMACEVCNT(i) ((i)*4+0x114) /* 80 event counters 0x114 - 0x284 */ 340 341 /* 342 * flash memory layout 343 * 0x00 - 07 48-bit MAC station address. 4 byte wise in BE order. 344 * 0x08 - 0b H->MAC xfer engine program start addr 63:32. 345 * 0x0c - 0f H2M program addr 31:0 (these are absolute addr, not offset) 346 * 0x10 - 13 H2M program length in 4 byte count. 347 * 0x14 - 0b M->HOST xfer engine program start addr 63:32. 348 * 0x18 - 0f M2H program addr 31:0 (absolute addr, not relative) 349 * 0x1c - 13 M2H program length in 4 byte count. 350 * 0x20 - 23 packet engine program addr 31:0, (absolute addr, not offset) 351 * 0x24 - 27 packet program length in 4 byte count. 352 * 353 * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0. 354 */ 355 356 /* 357 * all below are software constraction. 358 */ 359 #define MD_NTXSEGS 16 /* fixed */ 360 #define MD_TXQUEUELEN 8 /* tunable */ 361 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 362 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 363 #define MD_NTXDESC 128 364 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 365 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 366 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 367 368 #define MD_NRXDESC 64 /* tunable */ 369 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 370 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 371 372 struct control_data { 373 struct tdes cd_txdescs[MD_NTXDESC]; 374 struct rdes cd_rxdescs[MD_NRXDESC]; 375 }; 376 #define SCX_CDOFF(x) offsetof(struct control_data, x) 377 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 378 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 379 380 struct scx_txsoft { 381 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 382 bus_dmamap_t txs_dmamap; /* our DMA map */ 383 int txs_firstdesc; /* first descriptor in packet */ 384 int txs_lastdesc; /* last descriptor in packet */ 385 int txs_ndesc; /* # of descriptors used */ 386 }; 387 388 struct scx_rxsoft { 389 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 390 bus_dmamap_t rxs_dmamap; /* our DMA map */ 391 }; 392 393 struct scx_softc { 394 device_t sc_dev; /* generic device information */ 395 bus_space_tag_t sc_st; /* bus space tag */ 396 bus_space_handle_t sc_sh; /* bus space handle */ 397 bus_size_t sc_sz; /* csr map size */ 398 bus_space_handle_t sc_eesh; /* eeprom section handle */ 399 bus_size_t sc_eesz; /* eeprom map size */ 400 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 401 bus_dma_tag_t sc_dmat32; 402 struct ethercom sc_ethercom; /* Ethernet common data */ 403 struct mii_data sc_mii; /* MII */ 404 callout_t sc_callout; /* PHY monitor callout */ 405 bus_dma_segment_t sc_seg; /* descriptor store seg */ 406 int sc_nseg; /* descriptor store nseg */ 407 void *sc_ih; /* interrupt cookie */ 408 int sc_phy_id; /* PHY address */ 409 int sc_flowflags; /* 802.3x PAUSE flow control */ 410 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 411 uint32_t sc_t0cotso; /* T0_CSUM | T0_TSO to run */ 412 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 413 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 414 int sc_phandle; /* fdt phandle */ 415 uint64_t sc_freq; 416 417 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 418 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 419 420 struct control_data *sc_control_data; 421 #define sc_txdescs sc_control_data->cd_txdescs 422 #define sc_rxdescs sc_control_data->cd_rxdescs 423 424 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 425 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 426 int sc_txfree; /* number of free Tx descriptors */ 427 int sc_txnext; /* next ready Tx descriptor */ 428 int sc_txsfree; /* number of free Tx jobs */ 429 int sc_txsnext; /* next ready Tx job */ 430 int sc_txsdirty; /* dirty Tx jobs */ 431 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 432 433 krndsource_t rnd_source; /* random source */ 434 #ifdef GMAC_EVENT_COUNTER 435 /* 80 event counter exist */ 436 #endif 437 }; 438 439 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 440 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 441 442 #define SCX_CDTXSYNC(sc, x, n, ops) \ 443 do { \ 444 int __x, __n; \ 445 \ 446 __x = (x); \ 447 __n = (n); \ 448 \ 449 /* If it will wrap around, sync to the end of the ring. */ \ 450 if ((__x + __n) > MD_NTXDESC) { \ 451 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 452 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 453 (MD_NTXDESC - __x), (ops)); \ 454 __n -= (MD_NTXDESC - __x); \ 455 __x = 0; \ 456 } \ 457 \ 458 /* Now sync whatever is left. */ \ 459 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 460 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 461 } while (/*CONSTCOND*/0) 462 463 #define SCX_CDRXSYNC(sc, x, ops) \ 464 do { \ 465 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 466 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 467 } while (/*CONSTCOND*/0) 468 469 #define SCX_INIT_RXDESC(sc, x) \ 470 do { \ 471 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 472 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 473 struct mbuf *__m = __rxs->rxs_mbuf; \ 474 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 475 __m->m_data = __m->m_ext.ext_buf; \ 476 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 477 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 478 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 479 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 480 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 481 } while (/*CONSTCOND*/0) 482 483 /* memory mapped CSR register access */ 484 #define CSR_READ(sc,off) \ 485 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 486 #define CSR_WRITE(sc,off,val) \ 487 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 488 489 /* flash memory access */ 490 #define EE_READ(sc,off) \ 491 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 492 493 static int scx_fdt_match(device_t, cfdata_t, void *); 494 static void scx_fdt_attach(device_t, device_t, void *); 495 static int scx_acpi_match(device_t, cfdata_t, void *); 496 static void scx_acpi_attach(device_t, device_t, void *); 497 498 const CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 499 scx_fdt_match, scx_fdt_attach, NULL, NULL); 500 501 const CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 502 scx_acpi_match, scx_acpi_attach, NULL, NULL); 503 504 static void scx_attach_i(struct scx_softc *); 505 static void scx_reset(struct scx_softc *); 506 static int scx_init(struct ifnet *); 507 static void scx_stop(struct ifnet *, int); 508 static int scx_ioctl(struct ifnet *, u_long, void *); 509 static void scx_set_rcvfilt(struct scx_softc *); 510 static void scx_start(struct ifnet *); 511 static void scx_watchdog(struct ifnet *); 512 static int scx_intr(void *); 513 static void txreap(struct scx_softc *); 514 static void rxintr(struct scx_softc *); 515 static int add_rxbuf(struct scx_softc *, int); 516 static void rxdrain(struct scx_softc *sc); 517 static void mii_statchg(struct ifnet *); 518 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 519 static int mii_readreg(device_t, int, int, uint16_t *); 520 static int mii_writereg(device_t, int, int, uint16_t); 521 static void phy_tick(void *); 522 523 static void loaducode(struct scx_softc *); 524 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 525 526 static int get_mdioclk(uint32_t); 527 528 #define WAIT_FOR_SET(sc, reg, set, fail) \ 529 wait_for_bits(sc, reg, set, ~0, fail) 530 #define WAIT_FOR_CLR(sc, reg, clr, fail) \ 531 wait_for_bits(sc, reg, 0, clr, fail) 532 533 static int 534 wait_for_bits(struct scx_softc *sc, int reg, 535 uint32_t set, uint32_t clr, uint32_t fail) 536 { 537 uint32_t val; 538 int ntries; 539 540 for (ntries = 0; ntries < 1000; ntries++) { 541 val = CSR_READ(sc, reg); 542 if ((val & set) || !(val & clr)) 543 return 0; 544 if (val & fail) 545 return 1; 546 DELAY(1); 547 } 548 return 1; 549 } 550 551 /* GMAC register indirect access */ 552 static int 553 mac_read(struct scx_softc *sc, int reg) 554 { 555 556 CSR_WRITE(sc, MACCMD, reg); 557 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 558 return CSR_READ(sc, MACDATA); 559 } 560 561 static void 562 mac_write(struct scx_softc *sc, int reg, int val) 563 { 564 565 CSR_WRITE(sc, MACDATA, val); 566 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 567 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 568 } 569 570 static const struct device_compatible_entry compat_data[] = { 571 { .compat = "socionext,synquacer-netsec" }, 572 DEVICE_COMPAT_EOL 573 }; 574 static const struct device_compatible_entry compatible[] = { 575 { .compat = "SCX0001" }, 576 DEVICE_COMPAT_EOL 577 }; 578 579 static int 580 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 581 { 582 struct fdt_attach_args * const faa = aux; 583 584 return of_compatible_match(faa->faa_phandle, compat_data); 585 } 586 587 static void 588 scx_fdt_attach(device_t parent, device_t self, void *aux) 589 { 590 struct scx_softc * const sc = device_private(self); 591 struct fdt_attach_args * const faa = aux; 592 const int phandle = faa->faa_phandle; 593 bus_space_tag_t bst = faa->faa_bst; 594 bus_space_handle_t bsh; 595 bus_space_handle_t eebsh; 596 bus_addr_t addr[2]; 597 bus_size_t size[2]; 598 char intrstr[128]; 599 const char *phy_mode; 600 601 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 602 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 603 aprint_error(": unable to map device csr\n"); 604 return; 605 } 606 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 607 aprint_error(": failed to decode interrupt\n"); 608 goto fail; 609 } 610 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 611 NOT_MP_SAFE, scx_intr, sc); 612 if (sc->sc_ih == NULL) { 613 aprint_error_dev(self, "couldn't establish interrupt\n"); 614 goto fail; 615 } 616 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 617 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 618 aprint_error(": unable to map device eeprom\n"); 619 goto fail; 620 } 621 622 aprint_naive("\n"); 623 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 624 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 625 626 sc->sc_dev = self; 627 sc->sc_st = bst; 628 sc->sc_sh = bsh; 629 sc->sc_sz = size[0]; 630 sc->sc_eesh = eebsh; 631 sc->sc_eesz = size[1]; 632 sc->sc_dmat = faa->faa_dmat; 633 sc->sc_dmat32 = faa->faa_dmat; /* XXX */ 634 sc->sc_phandle = phandle; 635 636 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 637 if (phy_mode == NULL) 638 aprint_error(": missing 'phy-mode' property\n"); 639 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 640 641 scx_attach_i(sc); 642 return; 643 fail: 644 if (sc->sc_eesz) 645 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 646 if (sc->sc_sz) 647 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 648 return; 649 } 650 651 static int 652 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 653 { 654 struct acpi_attach_args *aa = aux; 655 656 return acpi_compatible_match(aa, compatible); 657 } 658 659 static void 660 scx_acpi_attach(device_t parent, device_t self, void *aux) 661 { 662 struct scx_softc * const sc = device_private(self); 663 struct acpi_attach_args * const aa = aux; 664 ACPI_HANDLE handle = aa->aa_node->ad_handle; 665 bus_space_tag_t bst = aa->aa_memt; 666 bus_space_handle_t bsh, eebsh; 667 struct acpi_resources res; 668 struct acpi_mem *mem; 669 struct acpi_irq *irq; 670 char *phy_mode; 671 ACPI_INTEGER acpi_phy, acpi_freq; 672 ACPI_STATUS rv; 673 674 aprint_normal(": Gigabit Ethernet Controller\n"); 675 rv = acpi_resource_parse(self, handle, "_CRS", 676 &res, &acpi_resource_parse_ops_default); 677 if (ACPI_FAILURE(rv)) 678 return; 679 mem = acpi_res_mem(&res, 0); 680 irq = acpi_res_irq(&res, 0); 681 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 682 aprint_error(": incomplete csr resources\n"); 683 return; 684 } 685 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 686 aprint_error(": couldn't map registers\n"); 687 return; 688 } 689 sc->sc_sz = mem->ar_length; 690 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 691 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 692 if (sc->sc_ih == NULL) { 693 aprint_error_dev(self, "couldn't establish interrupt\n"); 694 goto fail; 695 } 696 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 697 if (mem == NULL || mem->ar_length == 0) { 698 aprint_error(": incomplete eeprom resources\n"); 699 goto fail; 700 } 701 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 702 aprint_error(": couldn't map registers\n"); 703 goto fail; 704 } 705 sc->sc_eesz = mem->ar_length; 706 707 rv = acpi_dsd_string(handle, "phy-mode", &phy_mode); 708 if (ACPI_FAILURE(rv)) { 709 aprint_error(": missing 'phy-mode' property\n"); 710 phy_mode = NULL; 711 } 712 rv = acpi_dsd_integer(handle, "phy-channel", &acpi_phy); 713 if (ACPI_FAILURE(rv)) 714 acpi_phy = 31; 715 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 716 &acpi_freq); 717 if (ACPI_FAILURE(rv)) 718 acpi_freq = 999; 719 720 aprint_naive("\n"); 721 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 722 723 sc->sc_dev = self; 724 sc->sc_st = bst; 725 sc->sc_sh = bsh; 726 sc->sc_eesh = eebsh; 727 sc->sc_dmat = aa->aa_dmat64; 728 sc->sc_dmat32 = aa->aa_dmat; 729 730 aprint_normal_dev(self, 731 "phy mode %s, phy id %d, freq %ld\n", phy_mode, (int)acpi_phy, acpi_freq); 732 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 733 sc->sc_phy_id = (int)acpi_phy; 734 sc->sc_freq = acpi_freq; 735 aprint_normal_dev(self, 736 "GMACGAR %08x\n", mac_read(sc, GMACGAR)); 737 738 scx_attach_i(sc); 739 740 acpi_resource_cleanup(&res); 741 return; 742 fail: 743 if (sc->sc_eesz > 0) 744 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 745 if (sc->sc_sz > 0) 746 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 747 acpi_resource_cleanup(&res); 748 return; 749 } 750 751 static void 752 scx_attach_i(struct scx_softc *sc) 753 { 754 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 755 struct mii_data * const mii = &sc->sc_mii; 756 struct ifmedia * const ifm = &mii->mii_media; 757 uint32_t which, dwimp, dwfea; 758 uint8_t enaddr[ETHER_ADDR_LEN]; 759 bus_dma_segment_t seg; 760 uint32_t csr; 761 int i, nseg, error = 0; 762 763 which = CSR_READ(sc, HWVER); /* Socionext version 5.00xx */ 764 dwimp = mac_read(sc, GMACIMPL); /* DWC EMAC XX.YY */ 765 dwfea = mac_read(sc, HWFEA); /* DWC feature */ 766 aprint_normal_dev(sc->sc_dev, 767 "Socionext NetSec GbE %x.%x" 768 " (impl 0x%x, feature 0x%x)\n", 769 which >> 16, which & 0xffff, 770 dwimp, dwfea); 771 772 /* fetch MAC address in flash. stored in big endian order */ 773 csr = EE_READ(sc, 0x00); 774 enaddr[0] = csr >> 24; 775 enaddr[1] = csr >> 16; 776 enaddr[2] = csr >> 8; 777 enaddr[3] = csr; 778 csr = EE_READ(sc, 0x04); 779 enaddr[4] = csr >> 24; 780 enaddr[5] = csr >> 16; 781 aprint_normal_dev(sc->sc_dev, 782 "Ethernet address %s\n", ether_sprintf(enaddr)); 783 784 sc->sc_mdclk = get_mdioclk(sc->sc_freq) << GAR_CLK; /* 5:2 clk ratio */ 785 786 if (sc->sc_ucodeloaded == 0) 787 loaducode(sc); 788 789 mii->mii_ifp = ifp; 790 mii->mii_readreg = mii_readreg; 791 mii->mii_writereg = mii_writereg; 792 mii->mii_statchg = mii_statchg; 793 794 sc->sc_ethercom.ec_mii = mii; 795 ifmedia_init(ifm, 0, ether_mediachange, scx_ifmedia_sts); 796 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 797 MII_OFFSET_ANY, MIIF_DOPAUSE); 798 if (LIST_FIRST(&mii->mii_phys) == NULL) { 799 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 800 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 801 } else 802 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 803 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 804 805 /* 806 * Allocate the control data structures, and create and load the 807 * DMA map for it. 808 */ 809 error = bus_dmamem_alloc(sc->sc_dmat32, 810 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 811 if (error != 0) { 812 aprint_error_dev(sc->sc_dev, 813 "unable to allocate control data, error = %d\n", error); 814 goto fail_0; 815 } 816 error = bus_dmamem_map(sc->sc_dmat32, &seg, nseg, 817 sizeof(struct control_data), (void **)&sc->sc_control_data, 818 BUS_DMA_COHERENT); 819 if (error != 0) { 820 aprint_error_dev(sc->sc_dev, 821 "unable to map control data, error = %d\n", error); 822 goto fail_1; 823 } 824 error = bus_dmamap_create(sc->sc_dmat32, 825 sizeof(struct control_data), 1, 826 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 827 if (error != 0) { 828 aprint_error_dev(sc->sc_dev, 829 "unable to create control data DMA map, " 830 "error = %d\n", error); 831 goto fail_2; 832 } 833 error = bus_dmamap_load(sc->sc_dmat32, sc->sc_cddmamap, 834 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 835 if (error != 0) { 836 aprint_error_dev(sc->sc_dev, 837 "unable to load control data DMA map, error = %d\n", 838 error); 839 goto fail_3; 840 } 841 for (i = 0; i < MD_TXQUEUELEN; i++) { 842 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 843 MD_NTXSEGS, MCLBYTES, 0, 0, 844 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 845 aprint_error_dev(sc->sc_dev, 846 "unable to create tx DMA map %d, error = %d\n", 847 i, error); 848 goto fail_4; 849 } 850 } 851 for (i = 0; i < MD_NRXDESC; i++) { 852 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 853 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 854 aprint_error_dev(sc->sc_dev, 855 "unable to create rx DMA map %d, error = %d\n", 856 i, error); 857 goto fail_5; 858 } 859 sc->sc_rxsoft[i].rxs_mbuf = NULL; 860 } 861 sc->sc_seg = seg; 862 sc->sc_nseg = nseg; 863 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 864 865 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 866 ifp->if_softc = sc; 867 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 868 ifp->if_ioctl = scx_ioctl; 869 ifp->if_start = scx_start; 870 ifp->if_watchdog = scx_watchdog; 871 ifp->if_init = scx_init; 872 ifp->if_stop = scx_stop; 873 IFQ_SET_READY(&ifp->if_snd); 874 875 sc->sc_flowflags = 0; 876 877 if_attach(ifp); 878 if_deferred_start_init(ifp, NULL); 879 ether_ifattach(ifp, enaddr); 880 881 callout_init(&sc->sc_callout, 0); 882 callout_setfunc(&sc->sc_callout, phy_tick, sc); 883 884 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 885 RND_TYPE_NET, RND_FLAG_DEFAULT); 886 887 return; 888 889 fail_5: 890 for (i = 0; i < MD_NRXDESC; i++) { 891 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 892 bus_dmamap_destroy(sc->sc_dmat, 893 sc->sc_rxsoft[i].rxs_dmamap); 894 } 895 fail_4: 896 for (i = 0; i < MD_TXQUEUELEN; i++) { 897 if (sc->sc_txsoft[i].txs_dmamap != NULL) 898 bus_dmamap_destroy(sc->sc_dmat, 899 sc->sc_txsoft[i].txs_dmamap); 900 } 901 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 902 fail_3: 903 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 904 fail_2: 905 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 906 sizeof(struct control_data)); 907 fail_1: 908 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 909 fail_0: 910 if (sc->sc_phandle) 911 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 912 else 913 acpi_intr_disestablish(sc->sc_ih); 914 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 915 return; 916 } 917 918 static void 919 scx_reset(struct scx_softc *sc) 920 { 921 int loop = 0, busy; 922 923 mac_write(sc, GMACOMR, 0); 924 mac_write(sc, GMACBMR, BMR_RST); 925 do { 926 DELAY(1); 927 busy = mac_read(sc, GMACBMR) & BMR_RST; 928 } while (++loop < 3000 && busy); 929 mac_write(sc, GMACBMR, _BMR); 930 mac_write(sc, GMACAFR, 0); 931 932 CSR_WRITE(sc, CLKEN, CLK_ALL); /* distribute clock sources */ 933 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 934 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */ 935 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS); 936 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0); 937 938 mac_write(sc, GMACEVCTL, 1); 939 } 940 941 static int 942 scx_init(struct ifnet *ifp) 943 { 944 struct scx_softc *sc = ifp->if_softc; 945 const uint8_t *ea = CLLADDR(ifp->if_sadl); 946 paddr_t paddr; 947 uint32_t csr; 948 int i, error; 949 950 /* Cancel pending I/O. */ 951 scx_stop(ifp, 0); 952 953 /* Reset the chip to a known state. */ 954 scx_reset(sc); 955 956 /* build sane Tx */ 957 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 958 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 959 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 961 sc->sc_txfree = MD_NTXDESC; 962 sc->sc_txnext = 0; 963 for (i = 0; i < MD_TXQUEUELEN; i++) 964 sc->sc_txsoft[i].txs_mbuf = NULL; 965 sc->sc_txsfree = MD_TXQUEUELEN; 966 sc->sc_txsnext = 0; 967 sc->sc_txsdirty = 0; 968 969 /* load Rx descriptors with fresh mbuf */ 970 for (i = 0; i < MD_NRXDESC; i++) { 971 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 972 if ((error = add_rxbuf(sc, i)) != 0) { 973 aprint_error_dev(sc->sc_dev, 974 "unable to allocate or map rx " 975 "buffer %d, error = %d\n", 976 i, error); 977 rxdrain(sc); 978 goto out; 979 } 980 } 981 else 982 SCX_INIT_RXDESC(sc, i); 983 } 984 sc->sc_rxdescs[MD_NRXDESC - 1].r0 = R0_EOD; 985 sc->sc_rxptr = 0; 986 sc->sc_rxptr = 0; 987 988 /* set my address in perfect match slot 0. little endian order */ 989 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 990 mac_write(sc, GMACMAL0, csr); 991 csr = (ea[5] << 8) | ea[4]; 992 mac_write(sc, GMACMAH0, csr); 993 994 /* accept multicast frame or run promisc mode */ 995 scx_set_rcvfilt(sc); 996 997 /* set current media */ 998 if ((error = ether_mediachange(ifp)) != 0) 999 goto out; 1000 1001 paddr = SCX_CDTXADDR(sc, 0); 1002 mac_write(sc, TDBA_HI, BUS_ADDR_HI32(paddr)); 1003 mac_write(sc, TDBA_LO, BUS_ADDR_LO32(paddr)); 1004 paddr = SCX_CDRXADDR(sc, 0); 1005 mac_write(sc, RDBA_HI, BUS_ADDR_HI32(paddr)); 1006 mac_write(sc, RDBA_LO, BUS_ADDR_LO32(paddr)); 1007 1008 CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */ 1009 CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian */ 1010 1011 CSR_WRITE(sc, DESC_SRST, 01); 1012 WAIT_FOR_CLR(sc, DESC_SRST, 01, 0); 1013 1014 CSR_WRITE(sc, DESC_INIT, 01); 1015 WAIT_FOR_CLR(sc, DESC_INIT, 01, 0); 1016 1017 CSR_WRITE(sc, GMACRDLA, _RDLA); 1018 CSR_WRITE(sc, GMACTDLA, _TDLA); 1019 1020 CSR_WRITE(sc, FLOWTHR, (48<<16) | 36); /* pause|resume threshold */ 1021 mac_write(sc, GMACFCR, 256 << 16); /* 31:16 pause value */ 1022 1023 CSR_WRITE(sc, RXIE_CLR, ~0); 1024 CSR_WRITE(sc, TXIE_CLR, ~0); 1025 1026 /* kick to start GMAC engine */ 1027 csr = mac_read(sc, GMACOMR); 1028 mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST); 1029 1030 ifp->if_flags |= IFF_RUNNING; 1031 ifp->if_flags &= ~IFF_OACTIVE; 1032 1033 /* start one second timer */ 1034 callout_schedule(&sc->sc_callout, hz); 1035 out: 1036 return error; 1037 } 1038 1039 static void 1040 scx_stop(struct ifnet *ifp, int disable) 1041 { 1042 struct scx_softc *sc = ifp->if_softc; 1043 1044 /* Stop the one second clock. */ 1045 callout_stop(&sc->sc_callout); 1046 1047 /* Down the MII. */ 1048 mii_down(&sc->sc_mii); 1049 1050 /* Mark the interface down and cancel the watchdog timer. */ 1051 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1052 ifp->if_timer = 0; 1053 1054 if (CSR_READ(sc, CORESTAT) != 0) { 1055 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP); 1056 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP); 1057 1058 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP, 0); 1059 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP, 0); 1060 } 1061 } 1062 1063 static int 1064 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1065 { 1066 struct scx_softc *sc = ifp->if_softc; 1067 struct ifreq *ifr = (struct ifreq *)data; 1068 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1069 int s, error; 1070 1071 s = splnet(); 1072 1073 switch (cmd) { 1074 case SIOCSIFMEDIA: 1075 /* Flow control requires full-duplex mode. */ 1076 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1077 (ifr->ifr_media & IFM_FDX) == 0) 1078 ifr->ifr_media &= ~IFM_ETH_FMASK; 1079 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1080 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1081 /* We can do both TXPAUSE and RXPAUSE. */ 1082 ifr->ifr_media |= 1083 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1084 } 1085 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1086 } 1087 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 1088 break; 1089 default: 1090 error = ether_ioctl(ifp, cmd, data); 1091 if (error != ENETRESET) 1092 break; 1093 error = 0; 1094 if (cmd == SIOCSIFCAP) 1095 error = (*ifp->if_init)(ifp); 1096 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1097 ; 1098 else if (ifp->if_flags & IFF_RUNNING) { 1099 /* 1100 * Multicast list has changed; set the hardware filter 1101 * accordingly. 1102 */ 1103 scx_set_rcvfilt(sc); 1104 } 1105 break; 1106 } 1107 1108 splx(s); 1109 return error; 1110 } 1111 1112 static uint32_t 1113 bit_reverse_32(uint32_t x) 1114 { 1115 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 1116 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 1117 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 1118 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 1119 return (x >> 16) | (x << 16); 1120 } 1121 1122 static void 1123 scx_set_rcvfilt(struct scx_softc *sc) 1124 { 1125 struct ethercom * const ec = &sc->sc_ethercom; 1126 struct ifnet * const ifp = &ec->ec_if; 1127 struct ether_multistep step; 1128 struct ether_multi *enm; 1129 uint32_t mchash[2]; /* 2x 32 = 64 bit */ 1130 uint32_t csr, crc; 1131 int i; 1132 1133 csr = mac_read(sc, GMACAFR); 1134 csr &= ~(AFR_PR | AFR_PM | AFR_MHTE | AFR_HPF); 1135 mac_write(sc, GMACAFR, csr); 1136 1137 /* clear 15 entry supplemental perfect match filter */ 1138 for (i = 1; i < 16; i++) 1139 mac_write(sc, GMACMAH(i), 0); 1140 /* build 64 bit multicast hash filter */ 1141 crc = mchash[1] = mchash[0] = 0; 1142 1143 ETHER_LOCK(ec); 1144 if (ifp->if_flags & IFF_PROMISC) { 1145 ec->ec_flags |= ETHER_F_ALLMULTI; 1146 ETHER_UNLOCK(ec); 1147 /* run promisc. mode */ 1148 csr |= AFR_PR; 1149 goto update; 1150 } 1151 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1152 ETHER_FIRST_MULTI(step, ec, enm); 1153 i = 1; /* slot 0 is occupied */ 1154 while (enm != NULL) { 1155 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1156 /* 1157 * We must listen to a range of multicast addresses. 1158 * For now, just accept all multicasts, rather than 1159 * trying to set only those filter bits needed to match 1160 * the range. (At this time, the only use of address 1161 * ranges is for IP multicast routing, for which the 1162 * range is big enough to require all bits set.) 1163 */ 1164 ec->ec_flags |= ETHER_F_ALLMULTI; 1165 ETHER_UNLOCK(ec); 1166 /* accept all multi */ 1167 csr |= AFR_PM; 1168 goto update; 1169 } 1170 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 1171 if (i < 16) { 1172 /* use 15 entry perfect match filter */ 1173 uint32_t addr; 1174 uint8_t *ep = enm->enm_addrlo; 1175 addr = (ep[3] << 24) | (ep[2] << 16) 1176 | (ep[1] << 8) | ep[0]; 1177 mac_write(sc, GMACMAL(i), addr); 1178 addr = (ep[5] << 8) | ep[4]; 1179 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1180 } else { 1181 /* use hash table when too many */ 1182 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1183 crc = bit_reverse_32(~crc); 1184 /* 1(31) 5(30:26) bit sampling */ 1185 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 1186 } 1187 ETHER_NEXT_MULTI(step, enm); 1188 i++; 1189 } 1190 ETHER_UNLOCK(ec); 1191 if (crc) 1192 csr |= AFR_MHTE; 1193 csr |= AFR_HPF; /* use hash+perfect */ 1194 mac_write(sc, GMACMHTH, mchash[1]); 1195 mac_write(sc, GMACMHTL, mchash[0]); 1196 update: 1197 /* With PR or PM, MHTE/MHTL/MHTH are never consulted. really? */ 1198 mac_write(sc, GMACAFR, csr); 1199 return; 1200 } 1201 1202 static void 1203 scx_start(struct ifnet *ifp) 1204 { 1205 struct scx_softc *sc = ifp->if_softc; 1206 struct mbuf *m0; 1207 struct scx_txsoft *txs; 1208 bus_dmamap_t dmamap; 1209 int error, nexttx, lasttx, ofree, seg; 1210 uint32_t tdes0; 1211 1212 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1213 return; 1214 1215 /* Remember the previous number of free descriptors. */ 1216 ofree = sc->sc_txfree; 1217 1218 /* 1219 * Loop through the send queue, setting up transmit descriptors 1220 * until we drain the queue, or use up all available transmit 1221 * descriptors. 1222 */ 1223 for (;;) { 1224 IFQ_POLL(&ifp->if_snd, m0); 1225 if (m0 == NULL) 1226 break; 1227 1228 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1229 txreap(sc); 1230 if (sc->sc_txsfree == 0) 1231 break; 1232 } 1233 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1234 dmamap = txs->txs_dmamap; 1235 1236 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1237 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1238 if (error) { 1239 if (error == EFBIG) { 1240 aprint_error_dev(sc->sc_dev, 1241 "Tx packet consumes too many " 1242 "DMA segments, dropping...\n"); 1243 IFQ_DEQUEUE(&ifp->if_snd, m0); 1244 m_freem(m0); 1245 continue; 1246 } 1247 /* Short on resources, just stop for now. */ 1248 break; 1249 } 1250 1251 if (dmamap->dm_nsegs > sc->sc_txfree) { 1252 /* 1253 * Not enough free descriptors to transmit this 1254 * packet. We haven't committed anything yet, 1255 * so just unload the DMA map, put the packet 1256 * back on the queue, and punt. Notify the upper 1257 * layer that there are not more slots left. 1258 */ 1259 ifp->if_flags |= IFF_OACTIVE; 1260 bus_dmamap_unload(sc->sc_dmat, dmamap); 1261 break; 1262 } 1263 1264 IFQ_DEQUEUE(&ifp->if_snd, m0); 1265 1266 /* 1267 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1268 */ 1269 1270 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1271 BUS_DMASYNC_PREWRITE); 1272 1273 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1274 lasttx = -1; 1275 for (nexttx = sc->sc_txnext, seg = 0; 1276 seg < dmamap->dm_nsegs; 1277 seg++, nexttx = MD_NEXTTX(nexttx)) { 1278 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1279 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1280 /* 1281 * If this is the first descriptor we're 1282 * enqueueing, don't set the OWN bit just 1283 * yet. That could cause a race condition. 1284 * We'll do it below. 1285 */ 1286 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1287 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1288 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1289 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1290 (15 << T0_TDRID) | T0_PT | 1291 sc->sc_t0cotso | T0_TRS; 1292 tdes0 = T0_OWN; /* 2nd and other segments */ 1293 /* NB; t0 DRID field contains zero */ 1294 lasttx = nexttx; 1295 } 1296 1297 /* Write deferred 1st segment T0_OWN at the final stage */ 1298 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1299 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1300 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1301 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1302 1303 /* Tell DMA start transmit */ 1304 mac_write(sc, GMACTPD, 1); 1305 1306 txs->txs_mbuf = m0; 1307 txs->txs_firstdesc = sc->sc_txnext; 1308 txs->txs_lastdesc = lasttx; 1309 txs->txs_ndesc = dmamap->dm_nsegs; 1310 1311 sc->sc_txfree -= txs->txs_ndesc; 1312 sc->sc_txnext = nexttx; 1313 sc->sc_txsfree--; 1314 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1315 /* 1316 * Pass the packet to any BPF listeners. 1317 */ 1318 bpf_mtap(ifp, m0, BPF_D_OUT); 1319 } 1320 1321 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1322 /* No more slots left; notify upper layer. */ 1323 ifp->if_flags |= IFF_OACTIVE; 1324 } 1325 if (sc->sc_txfree != ofree) { 1326 /* Set a watchdog timer in case the chip flakes out. */ 1327 ifp->if_timer = 5; 1328 } 1329 } 1330 1331 static void 1332 scx_watchdog(struct ifnet *ifp) 1333 { 1334 struct scx_softc *sc = ifp->if_softc; 1335 1336 /* 1337 * Since we're not interrupting every packet, sweep 1338 * up before we report an error. 1339 */ 1340 txreap(sc); 1341 1342 if (sc->sc_txfree != MD_NTXDESC) { 1343 aprint_error_dev(sc->sc_dev, 1344 "device timeout (txfree %d txsfree %d txnext %d)\n", 1345 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1346 if_statinc(ifp, if_oerrors); 1347 1348 /* Reset the interface. */ 1349 scx_init(ifp); 1350 } 1351 1352 scx_start(ifp); 1353 } 1354 1355 static int 1356 scx_intr(void *arg) 1357 { 1358 struct scx_softc *sc = arg; 1359 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1360 1361 (void)ifp; 1362 /* XXX decode interrupt cause to pick isr() XXX */ 1363 rxintr(sc); 1364 txreap(sc); 1365 return 1; 1366 } 1367 1368 static void 1369 txreap(struct scx_softc *sc) 1370 { 1371 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1372 struct scx_txsoft *txs; 1373 uint32_t txstat; 1374 int i; 1375 1376 ifp->if_flags &= ~IFF_OACTIVE; 1377 1378 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1379 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1380 txs = &sc->sc_txsoft[i]; 1381 1382 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1383 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1384 1385 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1386 if (txstat & T0_OWN) /* desc is still in use */ 1387 break; 1388 1389 /* There is no way to tell transmission status per frame */ 1390 1391 if_statinc(ifp, if_opackets); 1392 1393 sc->sc_txfree += txs->txs_ndesc; 1394 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1395 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1396 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1397 m_freem(txs->txs_mbuf); 1398 txs->txs_mbuf = NULL; 1399 } 1400 sc->sc_txsdirty = i; 1401 if (sc->sc_txsfree == MD_TXQUEUELEN) 1402 ifp->if_timer = 0; 1403 } 1404 1405 static void 1406 rxintr(struct scx_softc *sc) 1407 { 1408 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1409 struct scx_rxsoft *rxs; 1410 struct mbuf *m; 1411 uint32_t rxstat; 1412 int i, len; 1413 1414 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1415 rxs = &sc->sc_rxsoft[i]; 1416 1417 SCX_CDRXSYNC(sc, i, 1418 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1419 1420 rxstat = sc->sc_rxdescs[i].r0; 1421 if (rxstat & R0_OWN) /* desc is left empty */ 1422 break; 1423 1424 /* R0_FS | R0_LS must have been marked for this desc */ 1425 1426 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1427 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1428 1429 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1430 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1431 m = rxs->rxs_mbuf; 1432 1433 if (add_rxbuf(sc, i) != 0) { 1434 if_statinc(ifp, if_ierrors); 1435 SCX_INIT_RXDESC(sc, i); 1436 bus_dmamap_sync(sc->sc_dmat, 1437 rxs->rxs_dmamap, 0, 1438 rxs->rxs_dmamap->dm_mapsize, 1439 BUS_DMASYNC_PREREAD); 1440 continue; 1441 } 1442 1443 m_set_rcvif(m, ifp); 1444 m->m_pkthdr.len = m->m_len = len; 1445 1446 if (rxstat & R0_CSUM) { 1447 uint32_t csum = M_CSUM_IPv4; 1448 if (rxstat & R0_CERR) 1449 csum |= M_CSUM_IPv4_BAD; 1450 m->m_pkthdr.csum_flags |= csum; 1451 } 1452 if_percpuq_enqueue(ifp->if_percpuq, m); 1453 } 1454 sc->sc_rxptr = i; 1455 } 1456 1457 static int 1458 add_rxbuf(struct scx_softc *sc, int i) 1459 { 1460 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1461 struct mbuf *m; 1462 int error; 1463 1464 MGETHDR(m, M_DONTWAIT, MT_DATA); 1465 if (m == NULL) 1466 return ENOBUFS; 1467 1468 MCLGET(m, M_DONTWAIT); 1469 if ((m->m_flags & M_EXT) == 0) { 1470 m_freem(m); 1471 return ENOBUFS; 1472 } 1473 1474 if (rxs->rxs_mbuf != NULL) 1475 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1476 1477 rxs->rxs_mbuf = m; 1478 1479 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1480 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1481 if (error) { 1482 aprint_error_dev(sc->sc_dev, 1483 "can't load rx DMA map %d, error = %d\n", i, error); 1484 panic("add_rxbuf"); 1485 } 1486 1487 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1488 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1489 SCX_INIT_RXDESC(sc, i); 1490 1491 return 0; 1492 } 1493 1494 static void 1495 rxdrain(struct scx_softc *sc) 1496 { 1497 struct scx_rxsoft *rxs; 1498 int i; 1499 1500 for (i = 0; i < MD_NRXDESC; i++) { 1501 rxs = &sc->sc_rxsoft[i]; 1502 if (rxs->rxs_mbuf != NULL) { 1503 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1504 m_freem(rxs->rxs_mbuf); 1505 rxs->rxs_mbuf = NULL; 1506 } 1507 } 1508 } 1509 1510 void 1511 mii_statchg(struct ifnet *ifp) 1512 { 1513 struct scx_softc *sc = ifp->if_softc; 1514 struct mii_data *mii = &sc->sc_mii; 1515 const int Mbps[4] = { 10, 100, 1000, 0 }; 1516 uint32_t miisr, mcr, fcr; 1517 int spd; 1518 1519 /* decode MIISR register value */ 1520 miisr = mac_read(sc, GMACMIISR); 1521 spd = Mbps[(miisr >> 1) & 03]; 1522 #if 1 1523 printf("MII link status (0x%x) %s", 1524 miisr, (miisr & 8) ? "up" : "down"); 1525 if (miisr & 8) { 1526 printf(" spd%d", spd); 1527 if (miisr & 01) 1528 printf(",full-duplex"); 1529 } 1530 printf("\n"); 1531 #endif 1532 /* Get flow control negotiation result. */ 1533 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1534 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1535 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1536 1537 /* Adjust speed 1000/100/10. */ 1538 mcr = mac_read(sc, GMACMCR); 1539 if (spd == 1000) 1540 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1541 else { 1542 if (spd == 100 && sc->sc_100mii) 1543 mcr |= MCR_SPD100; 1544 mcr |= MCR_USEMII; 1545 } 1546 mcr |= MCR_CST | MCR_JE; 1547 if (sc->sc_100mii == 0) 1548 mcr |= MCR_IBN; 1549 1550 /* Adjust duplexity and PAUSE flow control. */ 1551 mcr &= ~MCR_USEFDX; 1552 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1553 if (miisr & 01) { 1554 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1555 fcr |= FCR_TFE; 1556 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1557 fcr |= FCR_RFE; 1558 mcr |= MCR_USEFDX; 1559 } 1560 mac_write(sc, GMACMCR, mcr); 1561 mac_write(sc, GMACFCR, fcr); 1562 1563 printf("%ctxfe, %crxfe\n", 1564 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1565 } 1566 1567 static void 1568 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1569 { 1570 struct scx_softc *sc = ifp->if_softc; 1571 struct mii_data *mii = &sc->sc_mii; 1572 1573 mii_pollstat(mii); 1574 ifmr->ifm_status = mii->mii_media_status; 1575 ifmr->ifm_active = sc->sc_flowflags | 1576 (mii->mii_media_active & ~IFM_ETH_FMASK); 1577 } 1578 1579 static int 1580 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1581 { 1582 struct scx_softc *sc = device_private(self); 1583 uint32_t miia; 1584 int ntries; 1585 1586 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1587 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1588 for (ntries = 0; ntries < 1000; ntries++) { 1589 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1590 goto unbusy; 1591 DELAY(1); 1592 } 1593 return ETIMEDOUT; 1594 unbusy: 1595 *val = mac_read(sc, GMACGDR); 1596 return 0; 1597 } 1598 1599 static int 1600 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1601 { 1602 struct scx_softc *sc = device_private(self); 1603 uint32_t miia; 1604 uint16_t dummy; 1605 int ntries; 1606 1607 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1608 mac_write(sc, GMACGDR, val); 1609 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1610 for (ntries = 0; ntries < 1000; ntries++) { 1611 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1612 goto unbusy; 1613 DELAY(1); 1614 } 1615 return ETIMEDOUT; 1616 unbusy: 1617 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1618 return 0; 1619 } 1620 1621 static void 1622 phy_tick(void *arg) 1623 { 1624 struct scx_softc *sc = arg; 1625 struct mii_data *mii = &sc->sc_mii; 1626 int s; 1627 1628 s = splnet(); 1629 mii_tick(mii); 1630 splx(s); 1631 #ifdef GMAC_EVENT_COUNTERS 1632 #endif 1633 callout_schedule(&sc->sc_callout, hz); 1634 } 1635 1636 /* 1637 * 3 independent uengines exist to process host2media, media2host and 1638 * packet data flows. 1639 */ 1640 static void 1641 loaducode(struct scx_softc *sc) 1642 { 1643 uint32_t up, lo, sz; 1644 uint64_t addr; 1645 1646 sc->sc_ucodeloaded = 1; 1647 1648 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1649 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1650 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1651 sz *= 4; 1652 addr = ((uint64_t)up << 32) | lo; 1653 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1654 injectucode(sc, UCODE_H2M, (bus_addr_t)addr, (bus_size_t)sz); 1655 1656 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1657 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1658 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1659 sz *= 4; 1660 addr = ((uint64_t)up << 32) | lo; 1661 injectucode(sc, UCODE_M2H, (bus_addr_t)addr, (bus_size_t)sz); 1662 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1663 1664 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1665 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1666 sz *= 4; 1667 injectucode(sc, UCODE_PKT, (bus_addr_t)lo, (bus_size_t)sz); 1668 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1669 } 1670 1671 static void 1672 injectucode(struct scx_softc *sc, int port, 1673 bus_addr_t addr, bus_size_t size) 1674 { 1675 bus_space_handle_t bsh; 1676 bus_size_t off; 1677 uint32_t ucode; 1678 1679 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1680 aprint_error_dev(sc->sc_dev, 1681 "eeprom map failure for ucode port 0x%x\n", port); 1682 return; 1683 } 1684 for (off = 0; off < size; off += 4) { 1685 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1686 CSR_WRITE(sc, port, ucode); 1687 } 1688 bus_space_unmap(sc->sc_st, bsh, size); 1689 } 1690 1691 /* GAR 5:2 MDIO frequency selection */ 1692 static int 1693 get_mdioclk(uint32_t freq) 1694 { 1695 1696 1697 freq /= 1000 * 1000; 1698 1699 if (freq < 35) 1700 return GAR_MDIO_25_35MHZ; 1701 if (freq < 60) 1702 return GAR_MDIO_35_60MHZ; 1703 if (freq < 100) 1704 return GAR_MDIO_60_100MHZ; 1705 if (freq < 150) 1706 return GAR_MDIO_100_150MHZ; 1707 if (freq < 250) 1708 return GAR_MDIO_150_250MHZ; 1709 return GAR_MDIO_250_300MHZ; 1710 } 1711
Indexes created Mon Sep 29 21:09:56 GMT 2025