if_scx.c revision 1.29
1 /* $NetBSD: if_scx.c,v 1.29 2021/12/20 02:24:33 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 /* 34 * Socionext SC2A11 SynQuacer NetSec GbE driver 35 * 36 * Multiple Tx and Rx queues exist inside and dedicated descriptor 37 * fields specifies which queue is to use. Three internal micro-processors 38 * to handle incoming frames, outgoing frames and packet data crypto 39 * processing. uP programs are stored in an external flash memory and 40 * have to be loaded by device driver. 41 * NetSec uses Synopsys DesignWare Core EMAC. DWC implementation 42 * register (0x20) is known to have 0x10.36 and feature register (0x1058) 43 * to report XX.XX. 44 */ 45 46 #define NOT_MP_SAFE 0 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.29 2021/12/20 02:24:33 nisimura Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/bus.h> 53 #include <sys/intr.h> 54 #include <sys/device.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/errno.h> 59 #include <sys/rndsource.h> 60 #include <sys/kernel.h> 61 #include <sys/systm.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_dl.h> 66 #include <net/if_ether.h> 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <net/bpf.h> 70 71 #include <dev/fdt/fdtvar.h> 72 #include <dev/acpi/acpireg.h> 73 #include <dev/acpi/acpivar.h> 74 #include <dev/acpi/acpi_intr.h> 75 76 /* SC2A11 GbE 64-bit paddr descriptor */ 77 struct tdes { 78 uint32_t t0, t1, t2, t3; 79 }; 80 81 struct rdes { 82 uint32_t r0, r1, r2, r3; 83 }; 84 85 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 86 #define T0_EOD (1U<<30) /* end of descriptor array */ 87 #define T0_DRID (24) /* 29:24 desc ring id */ 88 #define T0_PT (1U<<21) /* 23:21 "pass-through" */ 89 #define T0_TDRID (16) /* 20:16 target desc ring id: GMAC=15 */ 90 #define T0_FS (1U<<9) /* first segment of frame */ 91 #define T0_LS (1U<<8) /* last segment of frame */ 92 #define T0_CSUM (1U<<7) /* enable check sum offload */ 93 #define T0_TSO (1U<<6) /* enable TCP segment offload */ 94 #define T0_TRS (1U<<4) /* 5:4 "TRS" */ 95 /* T1 frame segment address 63:32 */ 96 /* T2 frame segment address 31:0 */ 97 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */ 98 99 #define R0_OWN (1U<<31) /* desc is empty */ 100 #define R0_EOD (1U<<30) /* end of descriptor array */ 101 #define R0_SDRID (24) /* 29:24 source desc ring id */ 102 #define R0_FR (1U<<23) /* found fragmented */ 103 #define R0_ER (1U<<21) /* Rx error indication */ 104 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 105 #define R0_TDRID (12) /* 15:12 target desc ring id */ 106 #define R0_FS (1U<<9) /* first segment of frame */ 107 #define R0_LS (1U<<8) /* last segment of frame */ 108 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 109 #define R0_CERR (2U<<6) /* 0: undone, 1: found ok, 2: bad */ 110 /* R1 frame address 63:32 */ 111 /* R2 frame address 31:0 */ 112 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 113 114 /* 115 * SC2A11 registers. 0x100 - 1204 116 */ 117 #define SWRESET 0x104 118 #define SRST_RUN (1U<<31) /* instruct start, 0 to stop */ 119 #define COMINIT 0x120 120 #define INIT_DB (1U<<2) /* ???; self clear when done */ 121 #define INIT_CLS (1U<<1) /* ???; self clear when done */ 122 #define PKTCTRL 0x140 /* pkt engine control */ 123 #define MODENRM (1U<<28) /* change mode to normal */ 124 #define ENJUMBO (1U<<27) /* allow jumbo frame */ 125 #define RPTCSUMERR (1U<<3) /* log Rx checksum error */ 126 #define RPTHDCOMP (1U<<2) /* log HD imcomplete condition */ 127 #define RPTHDERR (1U<<1) /* log HD error */ 128 #define DROPNOMATCH (1U<<0) /* drop no match frames */ 129 #define xINTSR 0x200 /* aggregated interrupt status */ 130 #define IRQ_RX (1U<<1) /* top level Rx interrupt */ 131 #define IRQ_TX (1U<<0) /* top level Rx interrupt */ 132 #define IRQ_UCODE (1U<<20) /* ucode load completed */ 133 #define xINTAEN 0x204 /* INT_A enable */ 134 #define xINTAE_SET 0x234 /* bit to set */ 135 #define xINTAE_CLR 0x238 /* bit to clr */ 136 #define xINTBEN 0x23c /* INT_B enable */ 137 #define xINTBE_SET 0x240 /* bit to set */ 138 #define xINTBE_CLR 0x244 /* bit to clr */ 139 #define TXISR 0x400 /* transmit status */ 140 #define TXIEN 0x404 /* tx interrupt enable */ 141 #define TXIE_SET 0x428 /* bit to set */ 142 #define TXIE_CLR 0x42c /* bit to clr */ 143 #define TXI_NTOWNR (1U<<17) /* ready desc got empty */ 144 #define TXI_TR_ERR (1U<<16) /* tx error */ 145 #define TXI_TXDONE (1U<<15) /* tx completed */ 146 #define TXI_TMREXP (1U<<14) /* coalesce timer expired */ 147 #define RXISR 0x440 /* receive status */ 148 #define RXIEN 0x444 /* rx interrupt enable */ 149 #define RXIE_SET 0x468 /* bit to set */ 150 #define RXIE_CLR 0x46c /* bit to clr */ 151 #define RXI_RC_ERR (1U<<16) /* rx error */ 152 #define RXI_PKTCNT (1U<<15) /* rx counter has new value */ 153 #define RXI_TMREXP (1U<<14) /* coalesce timer expired */ 154 #define TDBA_LO 0x408 /* tdes array base addr 31:0 */ 155 #define TDBA_HI 0x434 /* tdes array base addr 63:32 */ 156 #define RDBA_LO 0x448 /* rdes array base addr 31:0 */ 157 #define RDBA_HI 0x474 /* rdes array base addr 63:32 */ 158 /* 13 pairs of special purpose desc array base address register exist */ 159 #define TXCONF 0x430 160 #define RXCONF 0x470 161 #define DESCNF_UP (1U<<31) /* up-and-running */ 162 #define DESCNF_CHRST (1U<<30) /* channel reset */ 163 #define DESCNF_TMR (1U<<4) /* coalesce timer mode select */ 164 #define DESCNF_LE (1) /* little endian desc format */ 165 #define TXCOLMAX 0x410 /* tx intr coalesce upper bound */ 166 #define RXCOLMAX 0x454 /* rx intr coalesce upper bound */ 167 #define TXITIMER 0x420 /* coalesce timer usec, MSB to use */ 168 #define RXITIMER 0x460 /* coalesce timer usec, MSB to use */ 169 #define TXDONECNT 0x424 /* tx completed count, auto-zero */ 170 #define RXDONECNT 0x458 /* rx available count, auto-zero */ 171 #define UCODE_H2M 0x210 /* host2media engine ucode port */ 172 #define UCODE_M2H 0x21c /* media2host engine ucode port */ 173 #define CORESTAT 0x218 /* engine run state */ 174 #define PKTSTOP (1U<<2) 175 #define M2HSTOP (1U<<1) 176 #define H2MSTOP (1U<<0) 177 #define DMACTL_H2M 0x214 /* host2media engine control */ 178 #define DMACTL_M2H 0x220 /* media2host engine control */ 179 #define DMACTL_STOP (1U<<0) /* instruct stop; self-clear */ 180 #define UCODE_PKT 0x0d0 /* packet engine ucode port */ 181 #define CLKEN 0x100 /* clock distribution enable */ 182 #define CLK_G (1U<<5) /* feed clk domain E */ 183 #define CLK_C (1U<<1) /* feed clk domain C */ 184 #define CLK_D (1U<<0) /* feed clk domain D */ 185 #define CLK_ALL 0x23 /* all above; 0x24 ??? 0x3f ??? */ 186 187 /* GMAC register indirect access. thru MACCMD/MACDATA operation */ 188 #define MACDATA 0x11c0 /* gmac register rd/wr data */ 189 #define MACCMD 0x11c4 /* gmac register operation */ 190 #define CMD_IOWR (1U<<28) /* write op */ 191 #define CMD_BUSY (1U<<31) /* busy bit */ 192 #define MACSTAT 0x1024 /* gmac status; ??? */ 193 #define MACINTE 0x1028 /* interrupt enable; ??? */ 194 195 #define FLOWTHR 0x11cc /* flow control threshold */ 196 /* 31:16 pause threshold, 15:0 resume threshold */ 197 #define INTF_SEL 0x11d4 /* ??? */ 198 199 #define DESC_INIT 0x11fc /* write 1 for desc init, SC */ 200 #define DESC_SRST 0x1204 /* write 1 for desc sw reset, SC */ 201 #define MODE_TRANS 0x500 /* mode change completion status */ 202 #define N2T_DONE (1U<<20) /* normal->taiki change completed */ 203 #define T2N_DONE (1U<<19) /* taiki->normal change completed */ 204 #define MACADRH 0x10c /* ??? */ 205 #define MACADRL 0x110 /* ??? */ 206 #define MCVER 0x22c /* micro controller version */ 207 #define HWVER 0x230 /* hardware version */ 208 209 /* 210 * GMAC registers are mostly identical to Synopsys DesignWare Core 211 * Ethernet. These must be handled by indirect access. 212 */ 213 #define GMACMCR 0x0000 /* MAC configuration */ 214 #define MCR_IBN (1U<<30) /* ??? */ 215 #define MCR_CST (1U<<25) /* strip CRC */ 216 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 217 #define MCR_WD (1U<<23) /* allow long >2048 tx frame */ 218 #define MCR_JE (1U<<20) /* allow ~9018 tx jumbo frame */ 219 #define MCR_IFG (7U<<17) /* 19:17 IFG value 0~7 */ 220 #define MCR_DRCS (1U<<16) /* ignore (G)MII HDX Tx error */ 221 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII (_PS) */ 222 #define MCR_SPD100 (1U<<14) /* force speed 100 (_FES) */ 223 #define MCR_DO (1U<<13) /* don't receive my own HDX Tx frames */ 224 #define MCR_LOOP (1U<<12) /* run loop back */ 225 #define MCR_USEFDX (1U<<11) /* force full duplex */ 226 #define MCR_IPCEN (1U<<10) /* handle checksum */ 227 #define MCR_DR (1U<<9) /* attempt no tx retry, send once */ 228 #define MCR_LUD (1U<<8) /* link condition report when RGMII */ 229 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 230 #define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */ 231 #define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */ 232 #define MCR_PREA (3U) /* 1:0 preamble len. 0~2 */ 233 #define _MCR_FDX 0x0000280c /* XXX TBD */ 234 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 235 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 236 #define AFR_RA (1U<<31) /* accept all irrespective of filt. */ 237 #define AFR_HPF (1U<<10) /* hash+perfect filter, or hash only */ 238 #define AFR_SAF (1U<<9) /* source address filter */ 239 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 240 #define AFR_PCF (2U<<6) /* ??? */ 241 #define AFR_DBF (1U<<5) /* reject broadcast frame */ 242 #define AFR_PM (1U<<4) /* accept all multicast frame */ 243 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 244 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 245 #define AFR_UHTE (1U<<1) /* use hash table for unicast */ 246 #define AFR_PR (1U<<0) /* run promisc mode */ 247 #define GMACGAR 0x0010 /* MDIO operation */ 248 #define GAR_PHY (11) /* 15:11 mii phy */ 249 #define GAR_REG (6) /* 10:6 mii reg */ 250 #define GAR_CLK (2) /* 5:2 mdio clock tick ratio */ 251 #define GAR_IOWR (1U<<1) /* MDIO write op */ 252 #define GAR_BUSY (1U<<0) /* busy bit */ 253 #define GAR_MDIO_25_35MHZ 2 254 #define GAR_MDIO_35_60MHZ 3 255 #define GAR_MDIO_60_100MHZ 0 256 #define GAR_MDIO_100_150MHZ 1 257 #define GAR_MDIO_150_250MHZ 4 258 #define GAR_MDIO_250_300MHZ 5 259 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 260 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 261 /* 31:16 pause timer value, 5:4 pause timer threshold */ 262 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 263 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 264 #define GMACIMPL 0x0020 /* implementation id XX.YY (no use) */ 265 #define GMACISR 0x0038 /* interrupt status indication */ 266 #define GMACIMR 0x003c /* interrupt mask to inhibit */ 267 #define ISR_TS (1U<<9) /* time stamp operation detected */ 268 #define ISR_CO (1U<<7) /* Rx checksum offload completed */ 269 #define ISR_TX (1U<<6) /* Tx completed */ 270 #define ISR_RX (1U<<5) /* Rx completed */ 271 #define ISR_ANY (1U<<4) /* any of above 5-7 report */ 272 #define ISR_LC (1U<<0) /* link status change detected */ 273 #define GMACMAH0 0x0040 /* my own MAC address 47:32 */ 274 #define GMACMAL0 0x0044 /* my own MAC address 31:0 */ 275 #define GMACMAH(i) ((i)*8+0x40) /* supplemental MAC addr 1-15 */ 276 #define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */ 277 /* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */ 278 #define GMACAMAH(i) ((i)*8+0x800) /* supplemental MAC addr 16-31 */ 279 #define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */ 280 /* supplimental MAH bit-31: slot in use, no other bit is effective */ 281 #define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */ 282 #define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */ 283 #define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */ 284 #define EMACVTAG 0x001c /* VLAN tag control */ 285 #define VTAG_HASH (1U<<19) /* use VLAN tag hash table */ 286 #define VTAG_SVLAN (1U<<18) /* handle type 0x88A8 SVLAN frame */ 287 #define VTAG_INV (1U<<17) /* run inverse match logic */ 288 #define VTAG_ETV (1U<<16) /* use only 12bit VID field to match */ 289 /* 15:0 concat of PRIO+CFI+VID */ 290 #define GMACVHT 0x0588 /* 16-bit VLAN tag hash */ 291 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 292 #define MIISR_LUP (1U<<3) /* link up(1)/down(0) report */ 293 #define MIISR_SPD (3U<<1) /* 2:1 speed 10(0)/100(1)/1000(2) */ 294 #define MIISR_FDX (1U<<0) /* fdx detected */ 295 296 #define GMACLPIS 0x0030 /* LPI control & status */ 297 #define LPIS_TXA (1U<<19) /* complete Tx in progress and LPI */ 298 #define LPIS_PLS (1U<<17) 299 #define LPIS_EN (1U<<16) /* 1: enter LPI mode, 0: exit */ 300 #define LPIS_TEN (1U<<0) /* Tx LPI report */ 301 #define GMACLPIC 0x0034 /* LPI timer control */ 302 #define LPIC_LST (5) /* 16:5 ??? */ 303 #define LPIC_TWT (0) /* 15:0 ??? */ 304 #define GMACTSC 0x0700 /* timestamp control */ 305 #define GMACSTM 0x071c /* start time */ 306 #define GMACTGT 0x0720 /* target time */ 307 #define GMACTSS 0x0728 /* timestamp status */ 308 #define GMACPPS 0x072c /* PPS control */ 309 #define GMACPPS0 0x0764 /* PPS0 width */ 310 311 #define GMACBMR 0x1000 /* DMA bus mode control */ 312 /* 24 multiply by x8 for RPBL & PBL values 313 * 23 use RPBL for Rx DMA 314 * 22:17 RPBL 315 * 16 fixed burst 316 * 15:14 priority between Rx and Tx 317 * 3 rxtx ratio 41 318 * 2 rxtx ratio 31 319 * 1 rxtx ratio 21 320 * 0 rxtx ratio 11 321 * 13:8 PBL possible DMA burst length 322 * 7 select alternative 32-byte descriptor format for new features 323 * 6:2 descriptor spacing. 0 for adjuscent 324 * 0 GMAC reset op. self-clear 325 */ 326 #define _BMR 0x00412080 /* XXX TBD */ 327 #define _BMR0 0x00020181 /* XXX TBD */ 328 #define BMR_RST (1) /* reset op. self clear when done */ 329 #define GMACTPD 0x1004 /* write any to resume tdes */ 330 #define GMACRPD 0x1008 /* write any to resume rdes */ 331 #define GMACRDLA 0x100c /* rdes base address 32bit paddr */ 332 #define GMACTDLA 0x1010 /* tdes base address 32bit paddr */ 333 #define _RDLA 0x18000 /* system RAM for GMAC rdes */ 334 #define _TDLA 0x1c000 /* system RAM for GMAC tdes */ 335 #define GMACDSR 0x1014 /* DMA status detail report; W1C */ 336 #define GMACDIE 0x101c /* DMA interrupt enable */ 337 #define DMAI_LPI (1U<<30) /* LPI interrupt */ 338 #define DMAI_TTI (1U<<29) /* timestamp trigger interrupt */ 339 #define DMAI_GMI (1U<<27) /* management counter interrupt */ 340 #define DMAI_GLI (1U<<26) /* xMII link change detected */ 341 #define DMAI_EB (23) /* 25:23 DMA bus error detected */ 342 #define DMAI_TS (20) /* 22:20 Tx DMA state report */ 343 #define DMAI_RS (17) /* 29:17 Rx DMA state report */ 344 #define DMAI_NIS (1U<<16) /* normal interrupt summary; W1C */ 345 #define DMAI_AIS (1U<<15) /* abnormal interrupt summary; W1C */ 346 #define DMAI_ERI (1U<<14) /* the first Rx buffer is filled */ 347 #define DMAI_FBI (1U<<13) /* DMA bus error detected */ 348 #define DMAI_ETI (1U<<10) /* single frame Tx completed */ 349 #define DMAI_RWT (1U<<9) /* longer than 2048 frame received */ 350 #define DMAI_RPS (1U<<8) /* Rx process is now stopped */ 351 #define DMAI_RU (1U<<7) /* Rx descriptor not available */ 352 #define DMAI_RI (1U<<6) /* frame Rx completed by !R1_DIC */ 353 #define DMAI_UNF (1U<<5) /* Tx underflow detected */ 354 #define DMAI_OVF (1U<<4) /* receive buffer overflow detected */ 355 #define DMAI_TJT (1U<<3) /* longer than 2048 frame sent */ 356 #define DMAI_TU (1U<<2) /* Tx discriptor not available */ 357 #define DMAI_TPS (1U<<1) /* transmission is stopped */ 358 #define DMAI_TI (1U<<0) /* frame Tx completed by T0_IC */ 359 #define GMACOMR 0x1018 /* DMA operation mode */ 360 #define OMR_RSF (1U<<25) /* 1: Rx store&forword, 0: immed. */ 361 #define OMR_TSF (1U<<21) /* 1: Tx store&forward, 0: immed. */ 362 #define OMR_TTC (14) /* 16:14 Tx threshold */ 363 #define OMR_ST (1U<<13) /* run Tx DMA engine, 0 to stop */ 364 #define OMR_RFD (11) /* 12:11 Rx FIFO fill level */ 365 #define OMR_EFC (1U<<8) /* transmit PAUSE to throttle Rx lvl. */ 366 #define OMR_FEF (1U<<7) /* allow to receive error frames */ 367 #define OMR_SR (1U<<1) /* run Rx DMA engine, 0 to stop */ 368 #define GMACEVCS 0x1020 /* missed frame or ovf detected */ 369 #define GMACRWDT 0x1024 /* enable rx watchdog timer interrupt */ 370 #define GMACAXIB 0x1028 /* AXI bus mode control */ 371 #define GMACAXIS 0x102c /* AXI status report */ 372 /* 0x1048 current tx desc address */ 373 /* 0x104c current rx desc address */ 374 /* 0x1050 current tx buffer address */ 375 /* 0x1054 current rx buffer address */ 376 #define HWFEA 0x1058 /* DWC feature report */ 377 #define FEA_EXDESC (1U<<24) /* new desc layout */ 378 #define FEA_2COE (1U<<18) /* Rx type 2 IP checksum offload */ 379 #define FEA_1COE (1U<<17) /* Rx type 1 IP checksum offload */ 380 #define FEA_TXOE (1U<<16) /* Tx checksum offload */ 381 #define FEA_MMC (1U<<11) /* RMON management block */ 382 383 #define GMACEVCTL 0x0100 /* event counter control */ 384 #define EVC_FHP (1U<<5) /* full-half preset */ 385 #define EVC_CP (1U<<4) /* counters preset */ 386 #define EVC_MCF (1U<<3) /* MMC counter freeze */ 387 #define EVC_ROR (1U<<2) /* auto-zero on counter read */ 388 #define EVC_CSR (1U<<1) /* counter stop rollover */ 389 #define EVC_CR (1U<<0) /* reset counters */ 390 #define GMACEVCNT(i) ((i)*4+0x114) /* 80 event counters 0x114 - 0x284 */ 391 392 /* 393 * flash memory layout 394 * 0x00 - 07 48-bit MAC station address. 4 byte wise in BE order. 395 * 0x08 - 0b H->MAC xfer engine program start addr 63:32. 396 * 0x0c - 0f H2M program addr 31:0 (these are absolute addr, not offset) 397 * 0x10 - 13 H2M program length in 4 byte count. 398 * 0x14 - 0b M->HOST xfer engine program start addr 63:32. 399 * 0x18 - 0f M2H program addr 31:0 (absolute addr, not relative) 400 * 0x1c - 13 M2H program length in 4 byte count. 401 * 0x20 - 23 packet engine program addr 31:0, (absolute addr, not offset) 402 * 0x24 - 27 packet program length in 4 byte count. 403 * 404 * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0. 405 */ 406 407 /* 408 * all below are software constraction. 409 */ 410 #define MD_NTXSEGS 16 /* fixed */ 411 #define MD_TXQUEUELEN 8 /* tunable */ 412 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 413 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 414 #define MD_NTXDESC 128 415 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 416 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 417 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 418 419 #define MD_NRXDESC 64 /* tunable */ 420 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 421 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 422 423 struct control_data { 424 struct tdes cd_txdescs[MD_NTXDESC]; 425 struct rdes cd_rxdescs[MD_NRXDESC]; 426 }; 427 #define SCX_CDOFF(x) offsetof(struct control_data, x) 428 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 429 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 430 431 struct scx_txsoft { 432 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 433 bus_dmamap_t txs_dmamap; /* our DMA map */ 434 int txs_firstdesc; /* first descriptor in packet */ 435 int txs_lastdesc; /* last descriptor in packet */ 436 int txs_ndesc; /* # of descriptors used */ 437 }; 438 439 struct scx_rxsoft { 440 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 441 bus_dmamap_t rxs_dmamap; /* our DMA map */ 442 }; 443 444 struct scx_softc { 445 device_t sc_dev; /* generic device information */ 446 bus_space_tag_t sc_st; /* bus space tag */ 447 bus_space_handle_t sc_sh; /* bus space handle */ 448 bus_size_t sc_sz; /* csr map size */ 449 bus_space_handle_t sc_eesh; /* eeprom section handle */ 450 bus_size_t sc_eesz; /* eeprom map size */ 451 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 452 bus_dma_tag_t sc_dmat32; 453 struct ethercom sc_ethercom; /* Ethernet common data */ 454 struct mii_data sc_mii; /* MII */ 455 callout_t sc_callout; /* PHY monitor callout */ 456 bus_dma_segment_t sc_seg; /* descriptor store seg */ 457 int sc_nseg; /* descriptor store nseg */ 458 void *sc_ih; /* interrupt cookie */ 459 int sc_phy_id; /* PHY address */ 460 int sc_flowflags; /* 802.3x PAUSE flow control */ 461 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 462 uint32_t sc_t0cotso; /* T0_CSUM | T0_TSO to run */ 463 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 464 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 465 int sc_phandle; /* fdt phandle */ 466 uint64_t sc_freq; 467 468 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 469 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 470 471 struct control_data *sc_control_data; 472 #define sc_txdescs sc_control_data->cd_txdescs 473 #define sc_rxdescs sc_control_data->cd_rxdescs 474 475 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 476 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 477 int sc_txfree; /* number of free Tx descriptors */ 478 int sc_txnext; /* next ready Tx descriptor */ 479 int sc_txsfree; /* number of free Tx jobs */ 480 int sc_txsnext; /* next ready Tx job */ 481 int sc_txsdirty; /* dirty Tx jobs */ 482 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 483 484 krndsource_t rnd_source; /* random source */ 485 #ifdef GMAC_EVENT_COUNTERS 486 /* 80 event counters exist */ 487 #endif 488 }; 489 490 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 491 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 492 493 #define SCX_CDTXSYNC(sc, x, n, ops) \ 494 do { \ 495 int __x, __n; \ 496 \ 497 __x = (x); \ 498 __n = (n); \ 499 \ 500 /* If it will wrap around, sync to the end of the ring. */ \ 501 if ((__x + __n) > MD_NTXDESC) { \ 502 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 503 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 504 (MD_NTXDESC - __x), (ops)); \ 505 __n -= (MD_NTXDESC - __x); \ 506 __x = 0; \ 507 } \ 508 \ 509 /* Now sync whatever is left. */ \ 510 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 511 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 512 } while (/*CONSTCOND*/0) 513 514 #define SCX_CDRXSYNC(sc, x, ops) \ 515 do { \ 516 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 517 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 518 } while (/*CONSTCOND*/0) 519 520 #define SCX_INIT_RXDESC(sc, x) \ 521 do { \ 522 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 523 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 524 struct mbuf *__m = __rxs->rxs_mbuf; \ 525 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 526 __m->m_data = __m->m_ext.ext_buf; \ 527 __rxd->r3 = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_len); \ 528 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 529 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 530 __rxd->r0 = htole32(R0_OWN | R0_FS | R0_LS); \ 531 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= htole32(R0_EOD); \ 532 } while (/*CONSTCOND*/0) 533 534 /* memory mapped CSR register access */ 535 #define CSR_READ(sc,off) \ 536 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 537 #define CSR_WRITE(sc,off,val) \ 538 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 539 540 /* flash memory access */ 541 #define EE_READ(sc,off) \ 542 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 543 544 static int scx_fdt_match(device_t, cfdata_t, void *); 545 static void scx_fdt_attach(device_t, device_t, void *); 546 static int scx_acpi_match(device_t, cfdata_t, void *); 547 static void scx_acpi_attach(device_t, device_t, void *); 548 549 const CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 550 scx_fdt_match, scx_fdt_attach, NULL, NULL); 551 552 const CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 553 scx_acpi_match, scx_acpi_attach, NULL, NULL); 554 555 static void scx_attach_i(struct scx_softc *); 556 static void scx_reset(struct scx_softc *); 557 static int scx_init(struct ifnet *); 558 static void scx_stop(struct ifnet *, int); 559 static int scx_ioctl(struct ifnet *, u_long, void *); 560 static void scx_set_rcvfilt(struct scx_softc *); 561 static void scx_start(struct ifnet *); 562 static void scx_watchdog(struct ifnet *); 563 static int scx_intr(void *); 564 static void txreap(struct scx_softc *); 565 static void rxintr(struct scx_softc *); 566 static int add_rxbuf(struct scx_softc *, int); 567 static void rxdrain(struct scx_softc *sc); 568 static void mii_statchg(struct ifnet *); 569 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 570 static int mii_readreg(device_t, int, int, uint16_t *); 571 static int mii_writereg(device_t, int, int, uint16_t); 572 static void phy_tick(void *); 573 574 static void loaducode(struct scx_softc *); 575 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 576 577 static int get_mdioclk(uint32_t); 578 579 #define WAIT_FOR_SET(sc, reg, set, fail) \ 580 wait_for_bits(sc, reg, set, ~0, fail) 581 #define WAIT_FOR_CLR(sc, reg, clr, fail) \ 582 wait_for_bits(sc, reg, 0, clr, fail) 583 584 static int 585 wait_for_bits(struct scx_softc *sc, int reg, 586 uint32_t set, uint32_t clr, uint32_t fail) 587 { 588 uint32_t val; 589 int ntries; 590 591 for (ntries = 0; ntries < 1000; ntries++) { 592 val = CSR_READ(sc, reg); 593 if ((val & set) || !(val & clr)) 594 return 0; 595 if (val & fail) 596 return 1; 597 DELAY(1); 598 } 599 return 1; 600 } 601 602 /* GMAC register indirect access */ 603 static int 604 mac_read(struct scx_softc *sc, int reg) 605 { 606 607 CSR_WRITE(sc, MACCMD, reg); 608 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 609 return CSR_READ(sc, MACDATA); 610 } 611 612 static void 613 mac_write(struct scx_softc *sc, int reg, int val) 614 { 615 616 CSR_WRITE(sc, MACDATA, val); 617 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 618 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 619 } 620 621 static const struct device_compatible_entry compat_data[] = { 622 { .compat = "socionext,synquacer-netsec" }, 623 DEVICE_COMPAT_EOL 624 }; 625 static const struct device_compatible_entry compatible[] = { 626 { .compat = "SCX0001" }, 627 DEVICE_COMPAT_EOL 628 }; 629 630 static int 631 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 632 { 633 struct fdt_attach_args * const faa = aux; 634 635 return of_compatible_match(faa->faa_phandle, compat_data); 636 } 637 638 static void 639 scx_fdt_attach(device_t parent, device_t self, void *aux) 640 { 641 struct scx_softc * const sc = device_private(self); 642 struct fdt_attach_args * const faa = aux; 643 const int phandle = faa->faa_phandle; 644 bus_space_tag_t bst = faa->faa_bst; 645 bus_space_handle_t bsh; 646 bus_space_handle_t eebsh; 647 bus_addr_t addr[2]; 648 bus_size_t size[2]; 649 char intrstr[128]; 650 const char *phy_mode; 651 652 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 653 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 654 aprint_error(": unable to map device csr\n"); 655 return; 656 } 657 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 658 aprint_error(": failed to decode interrupt\n"); 659 goto fail; 660 } 661 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 662 NOT_MP_SAFE, scx_intr, sc); 663 if (sc->sc_ih == NULL) { 664 aprint_error_dev(self, "couldn't establish interrupt\n"); 665 goto fail; 666 } 667 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 668 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 669 aprint_error(": unable to map device eeprom\n"); 670 goto fail; 671 } 672 673 aprint_naive("\n"); 674 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 675 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 676 677 sc->sc_dev = self; 678 sc->sc_st = bst; 679 sc->sc_sh = bsh; 680 sc->sc_sz = size[0]; 681 sc->sc_eesh = eebsh; 682 sc->sc_eesz = size[1]; 683 sc->sc_dmat = faa->faa_dmat; 684 sc->sc_dmat32 = faa->faa_dmat; /* XXX */ 685 sc->sc_phandle = phandle; 686 687 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 688 if (phy_mode == NULL) 689 aprint_error(": missing 'phy-mode' property\n"); 690 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 691 692 scx_attach_i(sc); 693 return; 694 fail: 695 if (sc->sc_eesz) 696 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 697 if (sc->sc_sz) 698 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 699 return; 700 } 701 702 static int 703 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 704 { 705 struct acpi_attach_args *aa = aux; 706 707 return acpi_compatible_match(aa, compatible); 708 } 709 710 static void 711 scx_acpi_attach(device_t parent, device_t self, void *aux) 712 { 713 struct scx_softc * const sc = device_private(self); 714 struct acpi_attach_args * const aa = aux; 715 ACPI_HANDLE handle = aa->aa_node->ad_handle; 716 bus_space_tag_t bst = aa->aa_memt; 717 bus_space_handle_t bsh, eebsh; 718 struct acpi_resources res; 719 struct acpi_mem *mem; 720 struct acpi_irq *irq; 721 char *phy_mode; 722 ACPI_INTEGER acpi_phy, acpi_freq; 723 ACPI_STATUS rv; 724 725 aprint_normal(": Gigabit Ethernet Controller\n"); 726 rv = acpi_resource_parse(self, handle, "_CRS", 727 &res, &acpi_resource_parse_ops_default); 728 if (ACPI_FAILURE(rv)) 729 return; 730 mem = acpi_res_mem(&res, 0); 731 irq = acpi_res_irq(&res, 0); 732 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 733 aprint_error(": incomplete csr resources\n"); 734 return; 735 } 736 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 737 aprint_error(": couldn't map registers\n"); 738 return; 739 } 740 sc->sc_sz = mem->ar_length; 741 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 742 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 743 if (sc->sc_ih == NULL) { 744 aprint_error_dev(self, "couldn't establish interrupt\n"); 745 goto fail; 746 } 747 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 748 if (mem == NULL || mem->ar_length == 0) { 749 aprint_error(": incomplete eeprom resources\n"); 750 goto fail; 751 } 752 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 753 aprint_error(": couldn't map registers\n"); 754 goto fail; 755 } 756 sc->sc_eesz = mem->ar_length; 757 758 rv = acpi_dsd_string(handle, "phy-mode", &phy_mode); 759 if (ACPI_FAILURE(rv)) { 760 aprint_error(": missing 'phy-mode' property\n"); 761 phy_mode = NULL; 762 } 763 rv = acpi_dsd_integer(handle, "phy-channel", &acpi_phy); 764 if (ACPI_FAILURE(rv)) 765 acpi_phy = 31; 766 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 767 &acpi_freq); 768 if (ACPI_FAILURE(rv)) 769 acpi_freq = 999; 770 771 aprint_naive("\n"); 772 /* aprint_normal(": Gigabit Ethernet Controller\n"); */ 773 774 sc->sc_dev = self; 775 sc->sc_st = bst; 776 sc->sc_sh = bsh; 777 sc->sc_eesh = eebsh; 778 sc->sc_dmat = aa->aa_dmat64; 779 sc->sc_dmat32 = aa->aa_dmat; 780 781 aprint_normal_dev(self, 782 "phy mode %s, phy id %d, freq %ld\n", phy_mode, (int)acpi_phy, acpi_freq); 783 sc->sc_100mii = (phy_mode && strcmp(phy_mode, "rgmii") != 0); 784 sc->sc_phy_id = (int)acpi_phy; 785 sc->sc_freq = acpi_freq; 786 aprint_normal_dev(self, 787 "GMACGAR %08x\n", mac_read(sc, GMACGAR)); 788 789 scx_attach_i(sc); 790 791 acpi_resource_cleanup(&res); 792 return; 793 fail: 794 if (sc->sc_eesz > 0) 795 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 796 if (sc->sc_sz > 0) 797 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 798 acpi_resource_cleanup(&res); 799 return; 800 } 801 802 static void 803 scx_attach_i(struct scx_softc *sc) 804 { 805 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 806 struct mii_data * const mii = &sc->sc_mii; 807 struct ifmedia * const ifm = &mii->mii_media; 808 uint32_t which, dwimp, dwfea; 809 uint8_t enaddr[ETHER_ADDR_LEN]; 810 bus_dma_segment_t seg; 811 uint32_t csr; 812 int i, nseg, error = 0; 813 814 which = CSR_READ(sc, HWVER); /* Socionext version 5.00xx */ 815 dwimp = mac_read(sc, GMACIMPL); /* DWC EMAC XX.YY */ 816 dwfea = mac_read(sc, HWFEA); /* DWC feature */ 817 aprint_normal_dev(sc->sc_dev, 818 "Socionext NetSec GbE %x.%x" 819 " (impl 0x%x, feature 0x%x)\n", 820 which >> 16, which & 0xffff, 821 dwimp, dwfea); 822 823 /* fetch MAC address in flash. stored in big endian order */ 824 csr = EE_READ(sc, 0x00); 825 enaddr[0] = csr >> 24; 826 enaddr[1] = csr >> 16; 827 enaddr[2] = csr >> 8; 828 enaddr[3] = csr; 829 csr = EE_READ(sc, 0x04); 830 enaddr[4] = csr >> 24; 831 enaddr[5] = csr >> 16; 832 aprint_normal_dev(sc->sc_dev, 833 "Ethernet address %s\n", ether_sprintf(enaddr)); 834 835 sc->sc_mdclk = get_mdioclk(sc->sc_freq) << GAR_CLK; /* 5:2 clk ratio */ 836 837 if (sc->sc_ucodeloaded == 0) 838 loaducode(sc); 839 840 mii->mii_ifp = ifp; 841 mii->mii_readreg = mii_readreg; 842 mii->mii_writereg = mii_writereg; 843 mii->mii_statchg = mii_statchg; 844 845 sc->sc_ethercom.ec_mii = mii; 846 ifmedia_init(ifm, 0, ether_mediachange, scx_ifmedia_sts); 847 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 848 MII_OFFSET_ANY, MIIF_DOPAUSE); 849 if (LIST_FIRST(&mii->mii_phys) == NULL) { 850 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 851 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 852 } else 853 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 854 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 855 856 /* 857 * Allocate the control data structures, and create and load the 858 * DMA map for it. 859 */ 860 error = bus_dmamem_alloc(sc->sc_dmat32, 861 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 862 if (error != 0) { 863 aprint_error_dev(sc->sc_dev, 864 "unable to allocate control data, error = %d\n", error); 865 goto fail_0; 866 } 867 error = bus_dmamem_map(sc->sc_dmat32, &seg, nseg, 868 sizeof(struct control_data), (void **)&sc->sc_control_data, 869 BUS_DMA_COHERENT); 870 if (error != 0) { 871 aprint_error_dev(sc->sc_dev, 872 "unable to map control data, error = %d\n", error); 873 goto fail_1; 874 } 875 error = bus_dmamap_create(sc->sc_dmat32, 876 sizeof(struct control_data), 1, 877 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 878 if (error != 0) { 879 aprint_error_dev(sc->sc_dev, 880 "unable to create control data DMA map, " 881 "error = %d\n", error); 882 goto fail_2; 883 } 884 error = bus_dmamap_load(sc->sc_dmat32, sc->sc_cddmamap, 885 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 886 if (error != 0) { 887 aprint_error_dev(sc->sc_dev, 888 "unable to load control data DMA map, error = %d\n", 889 error); 890 goto fail_3; 891 } 892 for (i = 0; i < MD_TXQUEUELEN; i++) { 893 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 894 MD_NTXSEGS, MCLBYTES, 0, 0, 895 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 896 aprint_error_dev(sc->sc_dev, 897 "unable to create tx DMA map %d, error = %d\n", 898 i, error); 899 goto fail_4; 900 } 901 } 902 for (i = 0; i < MD_NRXDESC; i++) { 903 if ((error = bus_dmamap_create(sc->sc_dmat32, MCLBYTES, 904 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 905 aprint_error_dev(sc->sc_dev, 906 "unable to create rx DMA map %d, error = %d\n", 907 i, error); 908 goto fail_5; 909 } 910 sc->sc_rxsoft[i].rxs_mbuf = NULL; 911 } 912 sc->sc_seg = seg; 913 sc->sc_nseg = nseg; 914 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 915 916 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 917 ifp->if_softc = sc; 918 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 919 ifp->if_ioctl = scx_ioctl; 920 ifp->if_start = scx_start; 921 ifp->if_watchdog = scx_watchdog; 922 ifp->if_init = scx_init; 923 ifp->if_stop = scx_stop; 924 IFQ_SET_READY(&ifp->if_snd); 925 926 sc->sc_flowflags = 0; 927 928 if_attach(ifp); 929 if_deferred_start_init(ifp, NULL); 930 ether_ifattach(ifp, enaddr); 931 932 callout_init(&sc->sc_callout, 0); 933 callout_setfunc(&sc->sc_callout, phy_tick, sc); 934 935 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 936 RND_TYPE_NET, RND_FLAG_DEFAULT); 937 938 return; 939 940 fail_5: 941 for (i = 0; i < MD_NRXDESC; i++) { 942 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 943 bus_dmamap_destroy(sc->sc_dmat, 944 sc->sc_rxsoft[i].rxs_dmamap); 945 } 946 fail_4: 947 for (i = 0; i < MD_TXQUEUELEN; i++) { 948 if (sc->sc_txsoft[i].txs_dmamap != NULL) 949 bus_dmamap_destroy(sc->sc_dmat, 950 sc->sc_txsoft[i].txs_dmamap); 951 } 952 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 953 fail_3: 954 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 955 fail_2: 956 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 957 sizeof(struct control_data)); 958 fail_1: 959 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 960 fail_0: 961 if (sc->sc_phandle) 962 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 963 else 964 acpi_intr_disestablish(sc->sc_ih); 965 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 966 return; 967 } 968 969 static void 970 scx_reset(struct scx_softc *sc) 971 { 972 int loop = 0, busy; 973 974 mac_write(sc, GMACOMR, 0); 975 mac_write(sc, GMACBMR, BMR_RST); 976 do { 977 DELAY(1); 978 busy = mac_read(sc, GMACBMR) & BMR_RST; 979 } while (++loop < 3000 && busy); 980 mac_write(sc, GMACBMR, _BMR); 981 mac_write(sc, GMACAFR, 0); 982 983 CSR_WRITE(sc, CLKEN, CLK_ALL); /* distribute clock sources */ 984 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 985 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */ 986 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS); 987 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0); 988 989 mac_write(sc, GMACEVCTL, 1); 990 } 991 992 static int 993 scx_init(struct ifnet *ifp) 994 { 995 struct scx_softc *sc = ifp->if_softc; 996 const uint8_t *ea = CLLADDR(ifp->if_sadl); 997 paddr_t paddr; 998 uint32_t csr; 999 int i, error; 1000 1001 /* Cancel pending I/O. */ 1002 scx_stop(ifp, 0); 1003 1004 /* Reset the chip to a known state. */ 1005 scx_reset(sc); 1006 1007 /* build sane Tx */ 1008 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 1009 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 1010 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 1011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1012 sc->sc_txfree = MD_NTXDESC; 1013 sc->sc_txnext = 0; 1014 for (i = 0; i < MD_TXQUEUELEN; i++) 1015 sc->sc_txsoft[i].txs_mbuf = NULL; 1016 sc->sc_txsfree = MD_TXQUEUELEN; 1017 sc->sc_txsnext = 0; 1018 sc->sc_txsdirty = 0; 1019 1020 /* load Rx descriptors with fresh mbuf */ 1021 for (i = 0; i < MD_NRXDESC; i++) { 1022 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 1023 if ((error = add_rxbuf(sc, i)) != 0) { 1024 aprint_error_dev(sc->sc_dev, 1025 "unable to allocate or map rx " 1026 "buffer %d, error = %d\n", 1027 i, error); 1028 rxdrain(sc); 1029 goto out; 1030 } 1031 } 1032 else 1033 SCX_INIT_RXDESC(sc, i); 1034 } 1035 sc->sc_rxdescs[MD_NRXDESC - 1].r0 = R0_EOD; 1036 sc->sc_rxptr = 0; 1037 sc->sc_rxptr = 0; 1038 1039 /* set my address in perfect match slot 0. little endian order */ 1040 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 1041 mac_write(sc, GMACMAL0, csr); 1042 csr = (ea[5] << 8) | ea[4]; 1043 mac_write(sc, GMACMAH0, csr); 1044 1045 /* accept multicast frame or run promisc mode */ 1046 scx_set_rcvfilt(sc); 1047 1048 /* set current media */ 1049 if ((error = ether_mediachange(ifp)) != 0) 1050 goto out; 1051 1052 paddr = SCX_CDTXADDR(sc, 0); 1053 mac_write(sc, TDBA_HI, BUS_ADDR_HI32(paddr)); 1054 mac_write(sc, TDBA_LO, BUS_ADDR_LO32(paddr)); 1055 paddr = SCX_CDRXADDR(sc, 0); 1056 mac_write(sc, RDBA_HI, BUS_ADDR_HI32(paddr)); 1057 mac_write(sc, RDBA_LO, BUS_ADDR_LO32(paddr)); 1058 1059 CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */ 1060 CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian */ 1061 1062 CSR_WRITE(sc, DESC_SRST, 01); 1063 WAIT_FOR_CLR(sc, DESC_SRST, 01, 0); 1064 1065 CSR_WRITE(sc, DESC_INIT, 01); 1066 WAIT_FOR_CLR(sc, DESC_INIT, 01, 0); 1067 1068 CSR_WRITE(sc, GMACRDLA, _RDLA); 1069 CSR_WRITE(sc, GMACTDLA, _TDLA); 1070 1071 CSR_WRITE(sc, FLOWTHR, (48<<16) | 36); /* pause|resume threshold */ 1072 mac_write(sc, GMACFCR, 256 << 16); /* 31:16 pause value */ 1073 1074 CSR_WRITE(sc, RXIE_CLR, ~0); 1075 CSR_WRITE(sc, TXIE_CLR, ~0); 1076 1077 /* kick to start GMAC engine */ 1078 csr = mac_read(sc, GMACOMR); 1079 mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST); 1080 1081 ifp->if_flags |= IFF_RUNNING; 1082 ifp->if_flags &= ~IFF_OACTIVE; 1083 1084 /* start one second timer */ 1085 callout_schedule(&sc->sc_callout, hz); 1086 out: 1087 return error; 1088 } 1089 1090 static void 1091 scx_stop(struct ifnet *ifp, int disable) 1092 { 1093 struct scx_softc *sc = ifp->if_softc; 1094 1095 /* Stop the one second clock. */ 1096 callout_stop(&sc->sc_callout); 1097 1098 /* Down the MII. */ 1099 mii_down(&sc->sc_mii); 1100 1101 /* Mark the interface down and cancel the watchdog timer. */ 1102 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1103 ifp->if_timer = 0; 1104 1105 if (CSR_READ(sc, CORESTAT) != 0) { 1106 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP); 1107 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP); 1108 1109 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP, 0); 1110 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP, 0); 1111 } 1112 } 1113 1114 static int 1115 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1116 { 1117 struct scx_softc *sc = ifp->if_softc; 1118 struct ifreq *ifr = (struct ifreq *)data; 1119 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1120 int s, error; 1121 1122 s = splnet(); 1123 1124 switch (cmd) { 1125 case SIOCSIFMEDIA: 1126 /* Flow control requires full-duplex mode. */ 1127 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1128 (ifr->ifr_media & IFM_FDX) == 0) 1129 ifr->ifr_media &= ~IFM_ETH_FMASK; 1130 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1131 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1132 /* We can do both TXPAUSE and RXPAUSE. */ 1133 ifr->ifr_media |= 1134 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1135 } 1136 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1137 } 1138 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 1139 break; 1140 default: 1141 error = ether_ioctl(ifp, cmd, data); 1142 if (error != ENETRESET) 1143 break; 1144 error = 0; 1145 if (cmd == SIOCSIFCAP) 1146 error = (*ifp->if_init)(ifp); 1147 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1148 ; 1149 else if (ifp->if_flags & IFF_RUNNING) { 1150 /* 1151 * Multicast list has changed; set the hardware filter 1152 * accordingly. 1153 */ 1154 scx_set_rcvfilt(sc); 1155 } 1156 break; 1157 } 1158 1159 splx(s); 1160 return error; 1161 } 1162 1163 static uint32_t 1164 bit_reverse_32(uint32_t x) 1165 { 1166 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 1167 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 1168 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 1169 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 1170 return (x >> 16) | (x << 16); 1171 } 1172 1173 static void 1174 scx_set_rcvfilt(struct scx_softc *sc) 1175 { 1176 struct ethercom * const ec = &sc->sc_ethercom; 1177 struct ifnet * const ifp = &ec->ec_if; 1178 struct ether_multistep step; 1179 struct ether_multi *enm; 1180 uint32_t mchash[2]; /* 2x 32 = 64 bit */ 1181 uint32_t csr, crc; 1182 int i; 1183 1184 csr = mac_read(sc, GMACAFR); 1185 csr &= ~(AFR_PR | AFR_PM | AFR_MHTE | AFR_HPF); 1186 mac_write(sc, GMACAFR, csr); 1187 1188 /* clear 15 entry supplemental perfect match filter */ 1189 for (i = 1; i < 16; i++) 1190 mac_write(sc, GMACMAH(i), 0); 1191 /* build 64 bit multicast hash filter */ 1192 crc = mchash[1] = mchash[0] = 0; 1193 1194 ETHER_LOCK(ec); 1195 if (ifp->if_flags & IFF_PROMISC) { 1196 ec->ec_flags |= ETHER_F_ALLMULTI; 1197 ETHER_UNLOCK(ec); 1198 /* run promisc. mode */ 1199 csr |= AFR_PR; 1200 goto update; 1201 } 1202 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1203 ETHER_FIRST_MULTI(step, ec, enm); 1204 i = 1; /* slot 0 is occupied */ 1205 while (enm != NULL) { 1206 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1207 /* 1208 * We must listen to a range of multicast addresses. 1209 * For now, just accept all multicasts, rather than 1210 * trying to set only those filter bits needed to match 1211 * the range. (At this time, the only use of address 1212 * ranges is for IP multicast routing, for which the 1213 * range is big enough to require all bits set.) 1214 */ 1215 ec->ec_flags |= ETHER_F_ALLMULTI; 1216 ETHER_UNLOCK(ec); 1217 /* accept all multi */ 1218 csr |= AFR_PM; 1219 goto update; 1220 } 1221 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 1222 if (i < 16) { 1223 /* use 15 entry perfect match filter */ 1224 uint32_t addr; 1225 uint8_t *ep = enm->enm_addrlo; 1226 addr = (ep[3] << 24) | (ep[2] << 16) 1227 | (ep[1] << 8) | ep[0]; 1228 mac_write(sc, GMACMAL(i), addr); 1229 addr = (ep[5] << 8) | ep[4]; 1230 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1231 } else { 1232 /* use hash table when too many */ 1233 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1234 crc = bit_reverse_32(~crc); 1235 /* 1(31) 5(30:26) bit sampling */ 1236 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 1237 } 1238 ETHER_NEXT_MULTI(step, enm); 1239 i++; 1240 } 1241 ETHER_UNLOCK(ec); 1242 if (crc) 1243 csr |= AFR_MHTE; 1244 csr |= AFR_HPF; /* use hash+perfect */ 1245 mac_write(sc, GMACMHTH, mchash[1]); 1246 mac_write(sc, GMACMHTL, mchash[0]); 1247 update: 1248 /* With PR or PM, MHTE/MHTL/MHTH are never consulted. really? */ 1249 mac_write(sc, GMACAFR, csr); 1250 return; 1251 } 1252 1253 static void 1254 scx_start(struct ifnet *ifp) 1255 { 1256 struct scx_softc *sc = ifp->if_softc; 1257 struct mbuf *m0; 1258 struct scx_txsoft *txs; 1259 bus_dmamap_t dmamap; 1260 int error, nexttx, lasttx, ofree, seg; 1261 uint32_t tdes0; 1262 1263 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1264 return; 1265 1266 /* Remember the previous number of free descriptors. */ 1267 ofree = sc->sc_txfree; 1268 1269 /* 1270 * Loop through the send queue, setting up transmit descriptors 1271 * until we drain the queue, or use up all available transmit 1272 * descriptors. 1273 */ 1274 for (;;) { 1275 IFQ_POLL(&ifp->if_snd, m0); 1276 if (m0 == NULL) 1277 break; 1278 1279 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1280 txreap(sc); 1281 if (sc->sc_txsfree == 0) 1282 break; 1283 } 1284 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1285 dmamap = txs->txs_dmamap; 1286 1287 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1288 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1289 if (error) { 1290 if (error == EFBIG) { 1291 aprint_error_dev(sc->sc_dev, 1292 "Tx packet consumes too many " 1293 "DMA segments, dropping...\n"); 1294 IFQ_DEQUEUE(&ifp->if_snd, m0); 1295 m_freem(m0); 1296 continue; 1297 } 1298 /* Short on resources, just stop for now. */ 1299 break; 1300 } 1301 1302 if (dmamap->dm_nsegs > sc->sc_txfree) { 1303 /* 1304 * Not enough free descriptors to transmit this 1305 * packet. We haven't committed anything yet, 1306 * so just unload the DMA map, put the packet 1307 * back on the queue, and punt. Notify the upper 1308 * layer that there are not more slots left. 1309 */ 1310 ifp->if_flags |= IFF_OACTIVE; 1311 bus_dmamap_unload(sc->sc_dmat, dmamap); 1312 break; 1313 } 1314 1315 IFQ_DEQUEUE(&ifp->if_snd, m0); 1316 1317 /* 1318 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1319 */ 1320 1321 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1322 BUS_DMASYNC_PREWRITE); 1323 1324 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1325 lasttx = -1; 1326 for (nexttx = sc->sc_txnext, seg = 0; 1327 seg < dmamap->dm_nsegs; 1328 seg++, nexttx = MD_NEXTTX(nexttx)) { 1329 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1330 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1331 /* 1332 * If this is the first descriptor we're 1333 * enqueueing, don't set the OWN bit just 1334 * yet. That could cause a race condition. 1335 * We'll do it below. 1336 */ 1337 tdes->t3 = htole32(dmamap->dm_segs[seg].ds_len); 1338 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1339 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1340 tdes->t0 = htole32(tdes0 | (tdes->t0 & T0_EOD) | 1341 (15 << T0_TDRID) | T0_PT | 1342 sc->sc_t0cotso | T0_TRS); 1343 tdes0 = T0_OWN; /* 2nd and other segments */ 1344 /* NB; t0 DRID field contains zero */ 1345 lasttx = nexttx; 1346 } 1347 1348 /* Write deferred 1st segment T0_OWN at the final stage */ 1349 sc->sc_txdescs[lasttx].t0 |= htole32(T0_LS); 1350 sc->sc_txdescs[sc->sc_txnext].t0 |= htole32(T0_FS | T0_OWN); 1351 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1353 1354 /* Tell DMA start transmit */ 1355 mac_write(sc, GMACTPD, 1); 1356 1357 txs->txs_mbuf = m0; 1358 txs->txs_firstdesc = sc->sc_txnext; 1359 txs->txs_lastdesc = lasttx; 1360 txs->txs_ndesc = dmamap->dm_nsegs; 1361 1362 sc->sc_txfree -= txs->txs_ndesc; 1363 sc->sc_txnext = nexttx; 1364 sc->sc_txsfree--; 1365 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1366 /* 1367 * Pass the packet to any BPF listeners. 1368 */ 1369 bpf_mtap(ifp, m0, BPF_D_OUT); 1370 } 1371 1372 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1373 /* No more slots left; notify upper layer. */ 1374 ifp->if_flags |= IFF_OACTIVE; 1375 } 1376 if (sc->sc_txfree != ofree) { 1377 /* Set a watchdog timer in case the chip flakes out. */ 1378 ifp->if_timer = 5; 1379 } 1380 } 1381 1382 static void 1383 scx_watchdog(struct ifnet *ifp) 1384 { 1385 struct scx_softc *sc = ifp->if_softc; 1386 1387 /* 1388 * Since we're not interrupting every packet, sweep 1389 * up before we report an error. 1390 */ 1391 txreap(sc); 1392 1393 if (sc->sc_txfree != MD_NTXDESC) { 1394 aprint_error_dev(sc->sc_dev, 1395 "device timeout (txfree %d txsfree %d txnext %d)\n", 1396 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1397 if_statinc(ifp, if_oerrors); 1398 1399 /* Reset the interface. */ 1400 scx_init(ifp); 1401 } 1402 1403 scx_start(ifp); 1404 } 1405 1406 static int 1407 scx_intr(void *arg) 1408 { 1409 struct scx_softc *sc = arg; 1410 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1411 1412 (void)ifp; 1413 /* XXX decode interrupt cause to pick isr() XXX */ 1414 rxintr(sc); 1415 txreap(sc); 1416 return 1; 1417 } 1418 1419 static void 1420 txreap(struct scx_softc *sc) 1421 { 1422 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1423 struct scx_txsoft *txs; 1424 uint32_t txstat; 1425 int i; 1426 1427 ifp->if_flags &= ~IFF_OACTIVE; 1428 1429 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1430 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1431 txs = &sc->sc_txsoft[i]; 1432 1433 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1435 1436 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1437 if (txstat & T0_OWN) /* desc is still in use */ 1438 break; 1439 1440 /* There is no way to tell transmission status per frame */ 1441 1442 if_statinc(ifp, if_opackets); 1443 1444 sc->sc_txfree += txs->txs_ndesc; 1445 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1446 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1447 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1448 m_freem(txs->txs_mbuf); 1449 txs->txs_mbuf = NULL; 1450 } 1451 sc->sc_txsdirty = i; 1452 if (sc->sc_txsfree == MD_TXQUEUELEN) 1453 ifp->if_timer = 0; 1454 } 1455 1456 static void 1457 rxintr(struct scx_softc *sc) 1458 { 1459 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1460 struct scx_rxsoft *rxs; 1461 struct mbuf *m; 1462 uint32_t rxstat; 1463 int i, len; 1464 1465 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1466 rxs = &sc->sc_rxsoft[i]; 1467 1468 SCX_CDRXSYNC(sc, i, 1469 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1470 1471 rxstat = le32toh(sc->sc_rxdescs[i].r0); 1472 if (rxstat & R0_OWN) /* desc is left empty */ 1473 break; 1474 1475 /* R0_FS | R0_LS must have been marked for this desc */ 1476 1477 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1478 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1479 1480 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1481 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1482 m = rxs->rxs_mbuf; 1483 1484 if (add_rxbuf(sc, i) != 0) { 1485 if_statinc(ifp, if_ierrors); 1486 SCX_INIT_RXDESC(sc, i); 1487 bus_dmamap_sync(sc->sc_dmat, 1488 rxs->rxs_dmamap, 0, 1489 rxs->rxs_dmamap->dm_mapsize, 1490 BUS_DMASYNC_PREREAD); 1491 continue; 1492 } 1493 1494 m_set_rcvif(m, ifp); 1495 m->m_pkthdr.len = m->m_len = len; 1496 1497 if (rxstat & R0_CSUM) { 1498 uint32_t csum = M_CSUM_IPv4; 1499 if (rxstat & R0_CERR) 1500 csum |= M_CSUM_IPv4_BAD; 1501 m->m_pkthdr.csum_flags |= csum; 1502 } 1503 if_percpuq_enqueue(ifp->if_percpuq, m); 1504 } 1505 sc->sc_rxptr = i; 1506 } 1507 1508 static int 1509 add_rxbuf(struct scx_softc *sc, int i) 1510 { 1511 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1512 struct mbuf *m; 1513 int error; 1514 1515 MGETHDR(m, M_DONTWAIT, MT_DATA); 1516 if (m == NULL) 1517 return ENOBUFS; 1518 1519 MCLGET(m, M_DONTWAIT); 1520 if ((m->m_flags & M_EXT) == 0) { 1521 m_freem(m); 1522 return ENOBUFS; 1523 } 1524 1525 if (rxs->rxs_mbuf != NULL) 1526 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1527 1528 rxs->rxs_mbuf = m; 1529 1530 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1531 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1532 if (error) { 1533 aprint_error_dev(sc->sc_dev, 1534 "can't load rx DMA map %d, error = %d\n", i, error); 1535 panic("add_rxbuf"); 1536 } 1537 1538 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1539 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1540 SCX_INIT_RXDESC(sc, i); 1541 1542 return 0; 1543 } 1544 1545 static void 1546 rxdrain(struct scx_softc *sc) 1547 { 1548 struct scx_rxsoft *rxs; 1549 int i; 1550 1551 for (i = 0; i < MD_NRXDESC; i++) { 1552 rxs = &sc->sc_rxsoft[i]; 1553 if (rxs->rxs_mbuf != NULL) { 1554 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1555 m_freem(rxs->rxs_mbuf); 1556 rxs->rxs_mbuf = NULL; 1557 } 1558 } 1559 } 1560 1561 void 1562 mii_statchg(struct ifnet *ifp) 1563 { 1564 struct scx_softc *sc = ifp->if_softc; 1565 struct mii_data *mii = &sc->sc_mii; 1566 const int Mbps[4] = { 10, 100, 1000, 0 }; 1567 uint32_t miisr, mcr, fcr; 1568 int spd; 1569 1570 /* decode MIISR register value */ 1571 miisr = mac_read(sc, GMACMIISR); 1572 spd = Mbps[(miisr & MIISR_SPD) >> 1]; 1573 #if 1 1574 static uint32_t oldmiisr = 0; 1575 if (miisr != oldmiisr) { 1576 printf("MII link status (0x%x) %s", 1577 miisr, (miisr & MIISR_LUP) ? "up" : "down"); 1578 if (miisr & MIISR_LUP) { 1579 printf(" spd%d", spd); 1580 if (miisr & MIISR_FDX) 1581 printf(",full-duplex"); 1582 } 1583 printf("\n"); 1584 } 1585 #endif 1586 /* Get flow control negotiation result. */ 1587 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1588 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1589 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1590 1591 /* Adjust speed 1000/100/10. */ 1592 mcr = mac_read(sc, GMACMCR); 1593 if (spd == 1000) 1594 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1595 else { 1596 if (spd == 100 && sc->sc_100mii) 1597 mcr |= MCR_SPD100; 1598 mcr |= MCR_USEMII; 1599 } 1600 mcr |= MCR_CST | MCR_JE; 1601 if (sc->sc_100mii == 0) 1602 mcr |= MCR_IBN; 1603 1604 /* Adjust duplexity and PAUSE flow control. */ 1605 mcr &= ~MCR_USEFDX; 1606 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1607 if (miisr & MIISR_FDX) { 1608 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1609 fcr |= FCR_TFE; 1610 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1611 fcr |= FCR_RFE; 1612 mcr |= MCR_USEFDX; 1613 } 1614 mac_write(sc, GMACMCR, mcr); 1615 mac_write(sc, GMACFCR, fcr); 1616 1617 #if 1 1618 if (miisr != oldmiisr) { 1619 printf("%ctxfe, %crxfe\n", 1620 (fcr & FCR_TFE) ? '+' : '-', 1621 (fcr & FCR_RFE) ? '+' : '-'); 1622 } 1623 oldmiisr = miisr; 1624 #endif 1625 } 1626 1627 static void 1628 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1629 { 1630 struct scx_softc *sc = ifp->if_softc; 1631 struct mii_data *mii = &sc->sc_mii; 1632 1633 mii_pollstat(mii); 1634 ifmr->ifm_status = mii->mii_media_status; 1635 ifmr->ifm_active = sc->sc_flowflags | 1636 (mii->mii_media_active & ~IFM_ETH_FMASK); 1637 } 1638 1639 static int 1640 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1641 { 1642 struct scx_softc *sc = device_private(self); 1643 uint32_t miia; 1644 int ntries; 1645 1646 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1647 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1648 for (ntries = 0; ntries < 1000; ntries++) { 1649 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1650 goto unbusy; 1651 DELAY(1); 1652 } 1653 return ETIMEDOUT; 1654 unbusy: 1655 *val = mac_read(sc, GMACGDR); 1656 return 0; 1657 } 1658 1659 static int 1660 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1661 { 1662 struct scx_softc *sc = device_private(self); 1663 uint32_t miia; 1664 uint16_t dummy; 1665 int ntries; 1666 1667 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1668 mac_write(sc, GMACGDR, val); 1669 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1670 for (ntries = 0; ntries < 1000; ntries++) { 1671 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1672 goto unbusy; 1673 DELAY(1); 1674 } 1675 return ETIMEDOUT; 1676 unbusy: 1677 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1678 return 0; 1679 } 1680 1681 static void 1682 phy_tick(void *arg) 1683 { 1684 struct scx_softc *sc = arg; 1685 struct mii_data *mii = &sc->sc_mii; 1686 int s; 1687 1688 s = splnet(); 1689 mii_tick(mii); 1690 splx(s); 1691 #ifdef GMAC_EVENT_COUNTERS 1692 /* 80 event counters exist */ 1693 #endif 1694 callout_schedule(&sc->sc_callout, hz); 1695 } 1696 1697 /* 1698 * 3 independent uengines exist to process host2media, media2host and 1699 * packet data flows. 1700 */ 1701 static void 1702 loaducode(struct scx_softc *sc) 1703 { 1704 uint32_t up, lo, sz; 1705 uint64_t addr; 1706 1707 sc->sc_ucodeloaded = 1; 1708 1709 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1710 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1711 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1712 sz *= 4; 1713 addr = ((uint64_t)up << 32) | lo; 1714 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1715 injectucode(sc, UCODE_H2M, (bus_addr_t)addr, (bus_size_t)sz); 1716 1717 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1718 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1719 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1720 sz *= 4; 1721 addr = ((uint64_t)up << 32) | lo; 1722 injectucode(sc, UCODE_M2H, (bus_addr_t)addr, (bus_size_t)sz); 1723 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1724 1725 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1726 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1727 sz *= 4; 1728 injectucode(sc, UCODE_PKT, (bus_addr_t)lo, (bus_size_t)sz); 1729 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1730 } 1731 1732 static void 1733 injectucode(struct scx_softc *sc, int port, 1734 bus_addr_t addr, bus_size_t size) 1735 { 1736 bus_space_handle_t bsh; 1737 bus_size_t off; 1738 uint32_t ucode; 1739 1740 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1741 aprint_error_dev(sc->sc_dev, 1742 "eeprom map failure for ucode port 0x%x\n", port); 1743 return; 1744 } 1745 for (off = 0; off < size; off += 4) { 1746 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1747 CSR_WRITE(sc, port, ucode); 1748 } 1749 bus_space_unmap(sc->sc_st, bsh, size); 1750 } 1751 1752 /* GAR 5:2 MDIO frequency selection */ 1753 static int 1754 get_mdioclk(uint32_t freq) 1755 { 1756 1757 1758 freq /= 1000 * 1000; 1759 1760 if (freq < 35) 1761 return GAR_MDIO_25_35MHZ; 1762 if (freq < 60) 1763 return GAR_MDIO_35_60MHZ; 1764 if (freq < 100) 1765 return GAR_MDIO_60_100MHZ; 1766 if (freq < 150) 1767 return GAR_MDIO_100_150MHZ; 1768 if (freq < 250) 1769 return GAR_MDIO_150_250MHZ; 1770 return GAR_MDIO_250_300MHZ; 1771 } 1772
Indexes created Mon Oct 13 21:09:55 GMT 2025