if_scx.c revision 1.3
1 /* $NetBSD: if_scx.c,v 1.3 2020/03/23 04:34:16 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 32 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~31 are for supplimental MAC addresses. Independently enabled 47 * for use. Good to catch multicast. Byte-wise selective match available. 48 * Use to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - The size of multicast hash filter store is unknown. Might be 256 bit. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.3 2020/03/23 04:34:16 nisimura Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 #include <sys/device.h> 59 #include <sys/callout.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/errno.h> 63 #include <sys/rndsource.h> 64 #include <sys/kernel.h> 65 #include <sys/systm.h> 66 67 #include <net/if.h> 68 #include <net/if_media.h> 69 #include <net/if_dl.h> 70 #include <net/if_ether.h> 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 #include <net/bpf.h> 74 75 #include <dev/fdt/fdtvar.h> 76 #include <dev/acpi/acpireg.h> 77 #include <dev/acpi/acpivar.h> 78 #include <dev/acpi/acpi_intr.h> 79 80 #define SWRESET 0x104 81 #define COMINIT 0x120 82 #define INTRST 0x200 83 #define IRQ_RX (1U<<1) 84 #define IRQ_TX (1U<<0) 85 #define INTREN 0x204 86 #define INTR_SET 0x234 87 #define INTR_CLR 0x238 88 #define TXINTST 0x400 89 #define TXINTEN 0x404 90 #define TXINT_SET 0x428 91 #define TXINT_CLR 0x42c 92 #define TXI_NTOWNR (1U<<17) 93 #define TXI_TR_ERR (1U<<16) 94 #define TXI_TXDONE (1U<<15) 95 #define TXI_TMREXP (1U<<14) 96 #define RXINTST 0x440 97 #define RXINTEN 0x444 98 #define RXINT_SET 0x468 99 #define RXINT_CLR 0x46c 100 #define RXI_RC_ERR (1U<<16) 101 #define RXI_PKTCNT (1U<<15) 102 #define RXI_TMREXP (1U<<14) 103 #define TXTIMER 0x41c 104 #define RXTIMER 0x45c 105 #define TXCOUNT 0x410 106 #define RXCOUNT 0x454 107 #define H2MENG 0x210 /* DMAC host2media ucode port */ 108 #define M2HENG 0x21c /* DMAC media2host ucode port */ 109 #define PKTENG 0x0d0 /* packet engine ucode port */ 110 #define HWVER0 0x22c 111 #define HWVER1 0x230 112 113 #define MACSTAT 0x1024 /* gmac status */ 114 #define MACDATA 0x11c0 /* gmac rd/wr data */ 115 #define MACCMD 0x11c4 /* gmac operation */ 116 #define CMD_IOWR (1U<<28) /* write op */ 117 #define CMD_BUSY (1U<<31) /* busy bit */ 118 #define DESCENG_INIT 0x11fc 119 #define DESCENG_SRST 0x1204 120 121 #define GMACMCR 0x0000 /* MAC configuration */ 122 #define MCR_IBN (1U<<30) /* */ 123 #define MCR_CST (1U<<25) /* strip CRC */ 124 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 125 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 126 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 127 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 128 #define MCR_USEFDX (1U<<11) /* force full duplex */ 129 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 130 #define MCR_ACS (1U<<7) /* auto pad CRC strip */ 131 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 132 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 133 #define _MCR_FDX 0x0000280c /* XXX TBD */ 134 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 135 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 136 #define AFR_RA (1U<<31) /* receive block all on */ 137 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 138 #define AFR_SAF (1U<<9) /* source address filter */ 139 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 140 #define AFR_PCF (3U<<6) /* */ 141 #define AFR_RB (1U<<5) /* reject broadcast frame */ 142 #define AFR_AM (1U<<4) /* accept all multicast frame */ 143 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 144 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 145 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 146 #define AFR_PM (1U<<0) /* run promisc mode */ 147 #define _AFR 0x80000001 /* XXX TBD */ 148 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 149 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 150 #define GMACGAR 0x0010 /* MDIO operation */ 151 #define GAR_PHY (11) /* mii phy 15:11 */ 152 #define GAR_REG (6) /* mii reg 10:6 */ 153 #define GAR_CTL (2) /* control 5:2 */ 154 #define GAR_IOWR (1U<<1) /* MDIO write op */ 155 #define GAR_BUSY (1U) /* busy bit */ 156 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 157 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 158 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 159 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 160 #define GMACIMPL 0x0020 /* implementation number XXXX.YYYY */ 161 #define GMACVTAG 0x001c /* VLAN tag control */ 162 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 163 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 164 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */ 165 #define GMACMAL(i) ((i)*8+0x44) 166 #define GMACMHT0 0x0500 /* multicast hash table 0 - 8*/ 167 168 #define GMACBMR 0x1000 /* DMA bus mode control 169 * 24 4PBL 170 * 22:17 RPBL 171 * 16 fix burst 172 * 15:14 priority between Rx and Tx 173 * 3 rxtx41 174 * 2 rxtx31 175 * 1 rxtx21 176 * 0 rxtx11 177 * 13:8 PBL possible DMA burst len 178 * 0 reset op. self clear 179 */ 180 #define _BMR 0x00412080 /* XXX TBD */ 181 #define _BMR0 0x00020181 /* XXX TBD */ 182 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 183 #define GMACRDLAR 0x100c /* */ 184 #define _RDLAR 0x18000 /* XXX TBD */ 185 #define GMACTDLAR 0x1010 /* */ 186 #define _TDLAR 0x1c000 /* XXX TBD */ 187 #define GMACOMR 0x1018 /* DMA operation */ 188 #define OMR_TXE (1U<<13) /* start Tx DMA engine, 0 to stop */ 189 #define OMR_RXE (1U<<1) /* start Rx DMA engine, 0 to stop */ 190 191 const struct { 192 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 193 } garclk[] = { 194 { 35, 2 }, /* 25-35 MHz */ 195 { 60, 3 }, /* 35-60 MHz */ 196 { 100, 0 }, /* 60-100 MHz */ 197 { 150, 1 }, /* 100-150 MHz */ 198 { 250, 4 }, /* 150-250 MHz */ 199 { 300, 5 }, /* 250-300 MHz */ 200 { 0 }, 201 }; 202 static int get_garclk(uint32_t); 203 204 /* descriptor format definition */ 205 struct tdes { 206 uint32_t t0, t1, t2, t3; 207 }; 208 209 struct rdes { 210 uint32_t r0, r1, r2, r3; 211 }; 212 213 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 214 #define T0_EOD (1U<<30) /* end of descriptor array */ 215 #define T0_DRID (24) /* 29:24 DRID */ 216 #define T0_PT (1U<<21) /* 23:21 PT */ 217 #define T0_TRID (16) /* 20:16 TRID */ 218 #define T0_FS (1U<<9) /* first segment of frame */ 219 #define T0_LS (1U<<8) /* last segment of frame */ 220 #define T0_CSUM (1U<<7) /* enable check sum offload */ 221 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 222 #define T0_TRS (1U<<4) /* 5:4 TRS */ 223 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 224 /* T1 segment address 63:32 */ 225 /* T2 segment address 31:0 */ 226 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 227 #define R0_OWN (1U<<31) /* desc is empty */ 228 #define R0_EOD (1U<<30) /* end of descriptor array */ 229 #define R0_SRID (24) /* 29:24 SRID */ 230 #define R0_FR (1U<<23) /* FR */ 231 #define R0_ER (1U<<21) /* Rx error indication */ 232 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 233 #define R0_TDRID (14) /* 15:14 TDRID */ 234 #define R0_FS (1U<<9) /* first segment of frame */ 235 #define R0_LS (1U<<8) /* last segment of frame */ 236 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 237 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 238 /* R1 frame address 63:32 */ 239 /* R2 frame address 31:0 */ 240 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 241 242 #define SCX_NTXSEGS 16 243 #define SCX_TXQUEUELEN 16 244 #define SCX_TXQUEUELEN_MASK (SCX_TXQUEUELEN - 1) 245 #define SCX_TXQUEUE_GC (SCX_TXQUEUELEN / 4) 246 #define SCX_NTXDESC (SCX_TXQUEUELEN * SCX_NTXSEGS) 247 #define SCX_NTXDESC_MASK (SCX_NTXDESC - 1) 248 #define SCX_NEXTTX(x) (((x) + 1) & SCX_NTXDESC_MASK) 249 #define SCX_NEXTTXS(x) (((x) + 1) & SCX_TXQUEUELEN_MASK) 250 251 #define SCX_NRXDESC 64 252 #define SCX_NRXDESC_MASK (SCX_NRXDESC - 1) 253 #define SCX_NEXTRX(x) (((x) + 1) & SCX_NRXDESC_MASK) 254 255 #define SCX_INIT_RXDESC(sc, x) \ 256 do { \ 257 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 258 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 259 struct mbuf *__m = __rxs->rxs_mbuf; \ 260 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 261 __m->m_data = __m->m_ext.ext_buf; \ 262 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 263 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 264 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 265 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 266 if ((x) == SCX_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 267 } while (/*CONSTCOND*/0) 268 269 struct control_data { 270 struct tdes cd_txdescs[SCX_NTXDESC]; 271 struct rdes cd_rxdescs[SCX_NRXDESC]; 272 }; 273 #define SCX_CDOFF(x) offsetof(struct control_data, x) 274 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 275 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 276 277 struct scx_txsoft { 278 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 279 bus_dmamap_t txs_dmamap; /* our DMA map */ 280 int txs_firstdesc; /* first descriptor in packet */ 281 int txs_lastdesc; /* last descriptor in packet */ 282 int txs_ndesc; /* # of descriptors used */ 283 }; 284 285 struct scx_rxsoft { 286 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 287 bus_dmamap_t rxs_dmamap; /* our DMA map */ 288 }; 289 290 struct scx_softc { 291 device_t sc_dev; /* generic device information */ 292 bus_space_tag_t sc_st; /* bus space tag */ 293 bus_space_handle_t sc_sh; /* bus space handle */ 294 bus_size_t sc_sz; /* csr map size */ 295 bus_space_handle_t sc_eesh; /* eeprom section handle */ 296 bus_size_t sc_eesz; /* eeprom map size */ 297 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 298 struct ethercom sc_ethercom; /* Ethernet common data */ 299 struct mii_data sc_mii; /* MII */ 300 callout_t sc_tick_ch; /* PHY monitor callout */ 301 bus_dma_segment_t sc_seg; /* descriptor store seg */ 302 int sc_nseg; /* descriptor store nseg */ 303 void *sc_ih; /* interrupt cookie */ 304 int sc_phy_id; /* PHY address */ 305 int sc_flowflags; /* 802.3x PAUSE flow control */ 306 uint32_t sc_gar; /* GAR 5:2 clock selection */ 307 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 308 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 309 int sc_phandle; /* fdt phandle */ 310 311 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 312 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 313 314 struct control_data *sc_control_data; 315 #define sc_txdescs sc_control_data->cd_txdescs 316 #define sc_rxdescs sc_control_data->cd_rxdescs 317 318 struct scx_txsoft sc_txsoft[SCX_TXQUEUELEN]; 319 struct scx_rxsoft sc_rxsoft[SCX_NRXDESC]; 320 int sc_txfree; /* number of free Tx descriptors */ 321 int sc_txnext; /* next ready Tx descriptor */ 322 int sc_txsfree; /* number of free Tx jobs */ 323 int sc_txsnext; /* next ready Tx job */ 324 int sc_txsdirty; /* dirty Tx jobs */ 325 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 326 327 krndsource_t rnd_source; /* random source */ 328 }; 329 330 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 331 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 332 333 #define SCX_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > SCX_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 344 (SCX_NTXDESC - __x), (ops)); \ 345 __n -= (SCX_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 352 } while (/*CONSTCOND*/0) 353 354 #define SCX_CDRXSYNC(sc, x, ops) \ 355 do { \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 358 } while (/*CONSTCOND*/0) 359 360 static int scx_fdt_match(device_t, cfdata_t, void *); 361 static void scx_fdt_attach(device_t, device_t, void *); 362 static int scx_acpi_match(device_t, cfdata_t, void *); 363 static void scx_acpi_attach(device_t, device_t, void *); 364 365 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 366 scx_fdt_match, scx_fdt_attach, NULL, NULL); 367 368 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 369 scx_acpi_match, scx_acpi_attach, NULL, NULL); 370 371 static void scx_attach_i(struct scx_softc *); 372 static void scx_reset(struct scx_softc *); 373 static int scx_init(struct ifnet *); 374 static void scx_start(struct ifnet *); 375 static void scx_stop(struct ifnet *, int); 376 static void scx_watchdog(struct ifnet *); 377 static int scx_ioctl(struct ifnet *, u_long, void *); 378 static void scx_set_rcvfilt(struct scx_softc *); 379 static int scx_ifmedia_upd(struct ifnet *); 380 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 381 static void mii_statchg(struct ifnet *); 382 static void phy_tick(void *); 383 static int mii_readreg(device_t, int, int, uint16_t *); 384 static int mii_writereg(device_t, int, int, uint16_t); 385 static int scx_intr(void *); 386 static void txreap(struct scx_softc *); 387 static void rxintr(struct scx_softc *); 388 static int add_rxbuf(struct scx_softc *, int); 389 static int spin_waitfor(struct scx_softc *, int, int); 390 static int mac_read(struct scx_softc *, int); 391 static void mac_write(struct scx_softc *, int, int); 392 static void loaducode(struct scx_softc *); 393 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 394 395 #define CSR_READ(sc,off) \ 396 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 397 #define CSR_WRITE(sc,off,val) \ 398 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 399 #define EE_READ(sc,off) \ 400 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 401 402 static int 403 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 404 { 405 static const char * compatible[] = { 406 "socionext,synquacer-netsec", 407 NULL 408 }; 409 struct fdt_attach_args * const faa = aux; 410 411 return of_match_compatible(faa->faa_phandle, compatible); 412 } 413 414 static void 415 scx_fdt_attach(device_t parent, device_t self, void *aux) 416 { 417 struct scx_softc * const sc = device_private(self); 418 struct fdt_attach_args * const faa = aux; 419 const int phandle = faa->faa_phandle; 420 bus_space_tag_t bst = faa->faa_bst; 421 bus_space_handle_t bsh; 422 bus_space_handle_t eebsh; 423 bus_addr_t addr[2]; 424 bus_size_t size[2]; 425 char intrstr[128]; 426 427 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 428 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 429 aprint_error(": unable to map device csr\n"); 430 return; 431 } 432 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 433 aprint_error(": failed to decode interrupt\n"); 434 goto fail; 435 } 436 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 437 NOT_MP_SAFE, scx_intr, sc); 438 if (sc->sc_ih == NULL) { 439 aprint_error_dev(self, "couldn't establish interrupt\n"); 440 goto fail; 441 } 442 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 443 || bus_space_map(faa->faa_bst, addr[0], size[1], 0, &eebsh) != 0) { 444 aprint_error(": unable to map device eeprom\n"); 445 goto fail; 446 } 447 448 aprint_naive("\n"); 449 aprint_normal(": Gigabit Ethernet Controller\n"); 450 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 451 452 sc->sc_dev = self; 453 sc->sc_st = bst; 454 sc->sc_sh = bsh; 455 sc->sc_sz = size[0]; 456 sc->sc_eesh = eebsh; 457 sc->sc_eesz = size[1]; 458 sc->sc_dmat = faa->faa_dmat; 459 sc->sc_phandle = phandle; 460 461 scx_attach_i(sc); 462 return; 463 fail: 464 if (sc->sc_eesz) 465 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 466 if (sc->sc_sz) 467 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 468 return; 469 } 470 471 static int 472 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 473 { 474 static const char * compatible[] = { 475 "SCX0001", 476 NULL 477 }; 478 struct acpi_attach_args *aa = aux; 479 480 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 481 return 0; 482 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 483 } 484 485 static void 486 scx_acpi_attach(device_t parent, device_t self, void *aux) 487 { 488 struct scx_softc * const sc = device_private(self); 489 struct acpi_attach_args * const aa = aux; 490 ACPI_HANDLE handle = aa->aa_node->ad_handle; 491 bus_space_tag_t bst = aa->aa_memt; 492 bus_space_handle_t bsh, eebsh; 493 struct acpi_resources res; 494 struct acpi_mem *mem; 495 struct acpi_irq *irq; 496 ACPI_STATUS rv; 497 498 rv = acpi_resource_parse(self, handle, "_CRS", 499 &res, &acpi_resource_parse_ops_default); 500 if (ACPI_FAILURE(rv)) 501 return; 502 mem = acpi_res_mem(&res, 0); 503 irq = acpi_res_irq(&res, 0); 504 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 505 aprint_error(": incomplete csr resources\n"); 506 return; 507 } 508 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 509 aprint_error(": couldn't map registers\n"); 510 return; 511 } 512 sc->sc_sz = mem->ar_length; 513 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 514 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 515 if (sc->sc_ih == NULL) { 516 aprint_error_dev(self, "couldn't establish interrupt\n"); 517 goto fail; 518 } 519 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 520 if (mem == NULL || mem->ar_length == 0) { 521 aprint_error(": incomplete eeprom resources\n"); 522 goto fail; 523 } 524 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 525 aprint_error(": couldn't map registers\n"); 526 goto fail; 527 } 528 sc->sc_eesz = mem->ar_length; 529 530 aprint_naive("\n"); 531 aprint_normal(": Gigabit Ethernet Controller\n"); 532 533 sc->sc_dev = self; 534 sc->sc_st = bst; 535 sc->sc_sh = bsh; 536 sc->sc_eesh = eebsh; 537 sc->sc_dmat = aa->aa_dmat64; 538 539 scx_attach_i(sc); 540 541 acpi_resource_cleanup(&res); 542 return; 543 fail: 544 if (sc->sc_eesz > 0) 545 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 546 if (sc->sc_sz > 0) 547 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 548 acpi_resource_cleanup(&res); 549 return; 550 } 551 552 static void 553 scx_attach_i(struct scx_softc *sc) 554 { 555 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 556 struct mii_data * const mii = &sc->sc_mii; 557 struct ifmedia * const ifm = &mii->mii_media; 558 uint32_t hwver, phyfreq; 559 uint8_t enaddr[ETHER_ADDR_LEN]; 560 bus_dma_segment_t seg; 561 uint32_t csr; 562 int i, nseg, error = 0; 563 564 hwver = CSR_READ(sc, HWVER1); 565 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 566 enaddr[0] = csr >> 24; 567 enaddr[1] = csr >> 16; 568 enaddr[2] = csr >> 8; 569 enaddr[3] = csr; 570 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 571 enaddr[4] = csr >> 24; 572 enaddr[5] = csr >> 16; 573 csr = CSR_READ(sc, GMACIMPL); 574 575 aprint_normal_dev(sc->sc_dev, "NetSec GbE (%d.%d) impl (%x.%x)\n", 576 hwver >> 16, hwver & 0xffff, csr >> 16, csr & 0xffff); 577 aprint_normal_dev(sc->sc_dev, 578 "Ethernet address %s\n", ether_sprintf(enaddr)); 579 580 phyfreq = 0; 581 sc->sc_phy_id = MII_PHY_ANY; 582 sc->sc_gar = get_garclk(phyfreq) << GAR_CTL; /* 5:2 gar control */ 583 584 sc->sc_flowflags = 0; 585 586 if (sc->sc_ucodeloaded == 0) 587 loaducode(sc); 588 589 mii->mii_ifp = ifp; 590 mii->mii_readreg = mii_readreg; 591 mii->mii_writereg = mii_writereg; 592 mii->mii_statchg = mii_statchg; 593 594 sc->sc_ethercom.ec_mii = mii; 595 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 596 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 597 MII_OFFSET_ANY, MIIF_DOPAUSE); 598 if (LIST_FIRST(&mii->mii_phys) == NULL) { 599 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 600 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 601 } else 602 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 603 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 604 605 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 606 ifp->if_softc = sc; 607 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 608 ifp->if_ioctl = scx_ioctl; 609 ifp->if_start = scx_start; 610 ifp->if_watchdog = scx_watchdog; 611 ifp->if_init = scx_init; 612 ifp->if_stop = scx_stop; 613 IFQ_SET_READY(&ifp->if_snd); 614 615 if_attach(ifp); 616 if_deferred_start_init(ifp, NULL); 617 ether_ifattach(ifp, enaddr); 618 619 callout_init(&sc->sc_tick_ch, 0); 620 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 621 622 /* 623 * Allocate the control data structures, and create and load the 624 * DMA map for it. 625 */ 626 error = bus_dmamem_alloc(sc->sc_dmat, 627 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 628 if (error != 0) { 629 aprint_error_dev(sc->sc_dev, 630 "unable to allocate control data, error = %d\n", error); 631 goto fail_0; 632 } 633 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 634 sizeof(struct control_data), (void **)&sc->sc_control_data, 635 BUS_DMA_COHERENT); 636 if (error != 0) { 637 aprint_error_dev(sc->sc_dev, 638 "unable to map control data, error = %d\n", error); 639 goto fail_1; 640 } 641 error = bus_dmamap_create(sc->sc_dmat, 642 sizeof(struct control_data), 1, 643 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 644 if (error != 0) { 645 aprint_error_dev(sc->sc_dev, 646 "unable to create control data DMA map, " 647 "error = %d\n", error); 648 goto fail_2; 649 } 650 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 651 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 652 if (error != 0) { 653 aprint_error_dev(sc->sc_dev, 654 "unable to load control data DMA map, error = %d\n", 655 error); 656 goto fail_3; 657 } 658 for (i = 0; i < SCX_TXQUEUELEN; i++) { 659 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 660 SCX_NTXSEGS, MCLBYTES, 0, 0, 661 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 662 aprint_error_dev(sc->sc_dev, 663 "unable to create tx DMA map %d, error = %d\n", 664 i, error); 665 goto fail_4; 666 } 667 } 668 for (i = 0; i < SCX_NRXDESC; i++) { 669 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 670 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 671 aprint_error_dev(sc->sc_dev, 672 "unable to create rx DMA map %d, error = %d\n", 673 i, error); 674 goto fail_5; 675 } 676 sc->sc_rxsoft[i].rxs_mbuf = NULL; 677 } 678 sc->sc_seg = seg; 679 sc->sc_nseg = nseg; 680 printf("bus_dmaseg ds_addr %08lx, ds_len %08lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 681 682 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 683 pmf_class_network_register(sc->sc_dev, ifp); 684 else 685 aprint_error_dev(sc->sc_dev, 686 "couldn't establish power handler\n"); 687 688 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 689 RND_TYPE_NET, RND_FLAG_DEFAULT); 690 691 return; 692 693 fail_5: 694 for (i = 0; i < SCX_NRXDESC; i++) { 695 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 696 bus_dmamap_destroy(sc->sc_dmat, 697 sc->sc_rxsoft[i].rxs_dmamap); 698 } 699 fail_4: 700 for (i = 0; i < SCX_TXQUEUELEN; i++) { 701 if (sc->sc_txsoft[i].txs_dmamap != NULL) 702 bus_dmamap_destroy(sc->sc_dmat, 703 sc->sc_txsoft[i].txs_dmamap); 704 } 705 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 706 fail_3: 707 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 708 fail_2: 709 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 710 sizeof(struct control_data)); 711 fail_1: 712 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 713 fail_0: 714 if (sc->sc_phandle) 715 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 716 else 717 acpi_intr_disestablish(sc->sc_ih); 718 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 719 return; 720 } 721 722 static void 723 scx_reset(struct scx_softc *sc) 724 { 725 726 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 727 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 728 729 CSR_WRITE(sc, DESCENG_SRST, 1); 730 CSR_WRITE(sc, DESCENG_INIT, 1); 731 mac_write(sc, GMACBMR, _BMR); 732 mac_write(sc, GMACRDLAR, _RDLAR); 733 mac_write(sc, GMACTDLAR, _TDLAR); 734 mac_write(sc, GMACAFR, _AFR); 735 } 736 737 static int 738 scx_init(struct ifnet *ifp) 739 { 740 struct scx_softc *sc = ifp->if_softc; 741 const uint8_t *ea = CLLADDR(ifp->if_sadl); 742 uint32_t csr; 743 int i; 744 745 /* Cancel pending I/O. */ 746 scx_stop(ifp, 0); 747 748 /* Reset the chip to a known state. */ 749 scx_reset(sc); 750 751 /* build sane Tx and load Rx descriptors with mbuf */ 752 for (i = 0; i < SCX_NTXDESC; i++) 753 sc->sc_txdescs[i].t0 = T0_OWN; 754 sc->sc_txdescs[SCX_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 755 for (i = 0; i < SCX_NRXDESC; i++) 756 (void)add_rxbuf(sc, i); 757 758 /* set my address in perfect match slot 0 */ 759 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 760 CSR_WRITE(sc, GMACMAL0, csr); 761 csr = (ea[5] << 8) | ea[4]; 762 CSR_WRITE(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 763 764 /* accept multicast frame or run promisc mode */ 765 scx_set_rcvfilt(sc); 766 767 (void)scx_ifmedia_upd(ifp); 768 769 /* kick to start GMAC engine */ 770 csr = mac_read(sc, GMACOMR); 771 CSR_WRITE(sc, RXINT_CLR, ~0); 772 CSR_WRITE(sc, TXINT_CLR, ~0); 773 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 774 775 ifp->if_flags |= IFF_RUNNING; 776 ifp->if_flags &= ~IFF_OACTIVE; 777 778 /* start one second timer */ 779 callout_schedule(&sc->sc_tick_ch, hz); 780 781 return 0; 782 } 783 784 static void 785 scx_stop(struct ifnet *ifp, int disable) 786 { 787 struct scx_softc *sc = ifp->if_softc; 788 789 /* Stop the one second clock. */ 790 callout_stop(&sc->sc_tick_ch); 791 792 /* Down the MII. */ 793 mii_down(&sc->sc_mii); 794 795 /* Mark the interface down and cancel the watchdog timer. */ 796 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 797 ifp->if_timer = 0; 798 } 799 800 static void 801 scx_watchdog(struct ifnet *ifp) 802 { 803 struct scx_softc *sc = ifp->if_softc; 804 805 /* 806 * Since we're not interrupting every packet, sweep 807 * up before we report an error. 808 */ 809 txreap(sc); 810 811 if (sc->sc_txfree != SCX_NTXDESC) { 812 aprint_error_dev(sc->sc_dev, 813 "device timeout (txfree %d txsfree %d txnext %d)\n", 814 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 815 if_statinc(ifp, if_oerrors); 816 817 /* Reset the interface. */ 818 scx_init(ifp); 819 } 820 821 scx_start(ifp); 822 } 823 824 static int 825 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 826 { 827 struct scx_softc *sc = ifp->if_softc; 828 struct ifreq *ifr = (struct ifreq *)data; 829 struct ifmedia *ifm; 830 int s, error; 831 832 s = splnet(); 833 834 switch (cmd) { 835 case SIOCSIFMEDIA: 836 /* Flow control requires full-duplex mode. */ 837 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 838 (ifr->ifr_media & IFM_FDX) == 0) 839 ifr->ifr_media &= ~IFM_ETH_FMASK; 840 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 841 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 842 /* We can do both TXPAUSE and RXPAUSE. */ 843 ifr->ifr_media |= 844 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 845 } 846 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 847 } 848 ifm = &sc->sc_mii.mii_media; 849 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 850 break; 851 default: 852 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 853 break; 854 855 error = 0; 856 857 if (cmd == SIOCSIFCAP) 858 error = (*ifp->if_init)(ifp); 859 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 860 ; 861 else if (ifp->if_flags & IFF_RUNNING) { 862 /* 863 * Multicast list has changed; set the hardware filter 864 * accordingly. 865 */ 866 scx_set_rcvfilt(sc); 867 } 868 break; 869 } 870 871 splx(s); 872 return error; 873 } 874 875 static void 876 scx_set_rcvfilt(struct scx_softc *sc) 877 { 878 struct ethercom * const ec = &sc->sc_ethercom; 879 struct ifnet * const ifp = &ec->ec_if; 880 struct ether_multistep step; 881 struct ether_multi *enm; 882 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 883 uint32_t csr, crc; 884 int i; 885 886 csr = CSR_READ(sc, GMACAFR); 887 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 888 CSR_WRITE(sc, GMACAFR, csr); 889 890 ETHER_LOCK(ec); 891 if (ifp->if_flags & IFF_PROMISC) { 892 ec->ec_flags |= ETHER_F_ALLMULTI; 893 ETHER_UNLOCK(ec); 894 goto update; 895 } 896 ec->ec_flags &= ~ETHER_F_ALLMULTI; 897 898 /* clear 15 entry supplimental perfect match filter */ 899 for (i = 1; i < 16; i++) 900 CSR_WRITE(sc, GMACMAH(i), 0); 901 /* build 256 bit multicast hash filter */ 902 memset(mchash, 0, sizeof(mchash)); 903 crc = 0; 904 905 ETHER_FIRST_MULTI(step, ec, enm); 906 i = 1; /* slot 0 is occupied */ 907 while (enm != NULL) { 908 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 909 /* 910 * We must listen to a range of multicast addresses. 911 * For now, just accept all multicasts, rather than 912 * trying to set only those filter bits needed to match 913 * the range. (At this time, the only use of address 914 * ranges is for IP multicast routing, for which the 915 * range is big enough to require all bits set.) 916 */ 917 ec->ec_flags |= ETHER_F_ALLMULTI; 918 ETHER_UNLOCK(ec); 919 goto update; 920 } 921 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 922 if (i < 16) { 923 /* use 31 entry perfect match filter */ 924 uint32_t addr; 925 uint8_t *ep = enm->enm_addrlo; 926 addr = (ep[3] << 24) | (ep[2] << 16) 927 | (ep[1] << 8) | ep[0]; 928 CSR_WRITE(sc, GMACMAL(i), addr); 929 addr = (ep[5] << 8) | ep[4]; 930 CSR_WRITE(sc, GMACMAH(i), addr | 1U<<31); 931 } else { 932 /* use hash table when too many */ 933 /* bit_reserve_32(~crc) !? */ 934 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 935 /* 3(31:29) 5(28:24) bit sampling */ 936 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 937 } 938 ETHER_NEXT_MULTI(step, enm); 939 i++; 940 } 941 ETHER_UNLOCK(ec); 942 943 if (crc) 944 csr |= AFR_MHTE; 945 for (i = 0; i < 8; i++) 946 CSR_WRITE(sc, GMACMHT0 + i * 4, mchash[i]); 947 CSR_WRITE(sc, GMACAFR, csr); 948 return; 949 950 update: 951 /* With PM or AM, MHTE/MHTL/MHTH are never consulted. really? */ 952 if (ifp->if_flags & IFF_PROMISC) 953 csr |= AFR_PM; /* run promisc. mode */ 954 else 955 csr |= AFR_AM; /* accept all multicast */ 956 CSR_WRITE(sc, GMACAFR, csr); 957 return; 958 } 959 960 static int 961 scx_ifmedia_upd(struct ifnet *ifp) 962 { 963 struct scx_softc *sc = ifp->if_softc; 964 struct ifmedia *ifm = &sc->sc_mii.mii_media; 965 966 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 967 ; /* restart AN */ 968 ; /* enable AN */ 969 ; /* advertise flow control pause */ 970 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 971 } else { 972 #if 1 973 uint32_t mcr = mac_read(sc, GMACMCR); 974 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 975 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 976 else { 977 mcr |= MCR_USEMII; /* RMII/MII */ 978 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX) 979 mcr |= MCR_SPD100; 980 } 981 if (ifm->ifm_cur->ifm_media & IFM_FDX) 982 mcr |= MCR_USEFDX; 983 mcr |= MCR_CST | MCR_JE; 984 mcr |= MCR_IBN; 985 mac_write(sc, GMACMCR, mcr); 986 #endif 987 } 988 return 0; 989 } 990 991 static void 992 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 993 { 994 struct scx_softc *sc = ifp->if_softc; 995 struct mii_data *mii = &sc->sc_mii; 996 997 mii_pollstat(mii); 998 ifmr->ifm_status = mii->mii_media_status; 999 ifmr->ifm_active = sc->sc_flowflags | 1000 (mii->mii_media_active & ~IFM_ETH_FMASK); 1001 } 1002 1003 void 1004 mii_statchg(struct ifnet *ifp) 1005 { 1006 struct scx_softc *sc = ifp->if_softc; 1007 struct mii_data *mii = &sc->sc_mii; 1008 uint32_t fcr; 1009 1010 /* Get flow control negotiation result. */ 1011 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1012 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1013 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1014 1015 /* Adjust PAUSE flow control. */ 1016 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1017 if (mii->mii_media_active & IFM_FDX) { 1018 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1019 fcr |= FCR_TFE; 1020 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1021 fcr |= FCR_RFE; 1022 } 1023 mac_write(sc, GMACFCR, fcr); 1024 1025 printf("%ctxfe, %crxfe\n", 1026 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1027 } 1028 1029 static void 1030 phy_tick(void *arg) 1031 { 1032 struct scx_softc *sc = arg; 1033 struct mii_data *mii = &sc->sc_mii; 1034 int s; 1035 1036 s = splnet(); 1037 mii_tick(mii); 1038 splx(s); 1039 1040 callout_schedule(&sc->sc_tick_ch, hz); 1041 } 1042 1043 static int 1044 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1045 { 1046 struct scx_softc *sc = device_private(self); 1047 uint32_t gar; 1048 int error; 1049 1050 gar = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_gar; 1051 mac_write(sc, GMACGAR, gar | GAR_BUSY); 1052 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1053 if (error) 1054 return error; 1055 *val = mac_read(sc, GMACGDR); 1056 return 0; 1057 } 1058 1059 static int 1060 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1061 { 1062 struct scx_softc *sc = device_private(self); 1063 uint32_t gar; 1064 uint16_t dummy; 1065 int error; 1066 1067 gar = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_gar; 1068 mac_write(sc, GMACGDR, val); 1069 mac_write(sc, GMACGAR, gar | GAR_IOWR | GAR_BUSY); 1070 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1071 if (error) 1072 return error; 1073 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1074 return 0; 1075 } 1076 1077 static void 1078 scx_start(struct ifnet *ifp) 1079 { 1080 struct scx_softc *sc = ifp->if_softc; 1081 struct mbuf *m0, *m; 1082 struct scx_txsoft *txs; 1083 bus_dmamap_t dmamap; 1084 int error, nexttx, lasttx, ofree, seg; 1085 uint32_t tdes0; 1086 1087 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1088 return; 1089 1090 /* Remember the previous number of free descriptors. */ 1091 ofree = sc->sc_txfree; 1092 1093 /* 1094 * Loop through the send queue, setting up transmit descriptors 1095 * until we drain the queue, or use up all available transmit 1096 * descriptors. 1097 */ 1098 for (;;) { 1099 IFQ_POLL(&ifp->if_snd, m0); 1100 if (m0 == NULL) 1101 break; 1102 1103 if (sc->sc_txsfree < SCX_TXQUEUE_GC) { 1104 txreap(sc); 1105 if (sc->sc_txsfree == 0) 1106 break; 1107 } 1108 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1109 dmamap = txs->txs_dmamap; 1110 1111 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1112 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1113 if (error) { 1114 if (error == EFBIG) { 1115 aprint_error_dev(sc->sc_dev, 1116 "Tx packet consumes too many " 1117 "DMA segments, dropping...\n"); 1118 IFQ_DEQUEUE(&ifp->if_snd, m0); 1119 m_freem(m0); 1120 continue; 1121 } 1122 /* Short on resources, just stop for now. */ 1123 break; 1124 } 1125 1126 if (dmamap->dm_nsegs > sc->sc_txfree) { 1127 /* 1128 * Not enough free descriptors to transmit this 1129 * packet. We haven't committed anything yet, 1130 * so just unload the DMA map, put the packet 1131 * back on the queue, and punt. Notify the upper 1132 * layer that there are not more slots left. 1133 */ 1134 ifp->if_flags |= IFF_OACTIVE; 1135 bus_dmamap_unload(sc->sc_dmat, dmamap); 1136 break; 1137 } 1138 1139 IFQ_DEQUEUE(&ifp->if_snd, m0); 1140 1141 /* 1142 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1143 */ 1144 1145 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1146 BUS_DMASYNC_PREWRITE); 1147 1148 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1149 lasttx = -1; 1150 for (nexttx = sc->sc_txnext, seg = 0; 1151 seg < dmamap->dm_nsegs; 1152 seg++, nexttx = SCX_NEXTTX(nexttx)) { 1153 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1154 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1155 /* 1156 * If this is the first descriptor we're 1157 * enqueueing, don't set the OWN bit just 1158 * yet. That could cause a race condition. 1159 * We'll do it below. 1160 */ 1161 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1162 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1163 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1164 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1165 (15 << T0_TRID) | T0_PT | 1166 sc->sc_t0coso | T0_TRS; 1167 tdes0 = T0_OWN; /* 2nd and other segments */ 1168 lasttx = nexttx; 1169 } 1170 /* 1171 * Outgoing NFS mbuf must be unloaded when Tx completed. 1172 * Without T1_IC NFS mbuf is left unack'ed for excessive 1173 * time and NFS stops to proceed until scx_watchdog() 1174 * calls txreap() to reclaim the unack'ed mbuf. 1175 * It's painful to traverse every mbuf chain to determine 1176 * whether someone is waiting for Tx completion. 1177 */ 1178 m = m0; 1179 do { 1180 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1181 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1182 break; 1183 } 1184 } while ((m = m->m_next) != NULL); 1185 1186 /* Write deferred 1st segment T0_OWN at the final stage */ 1187 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1188 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1189 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1190 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1191 1192 /* Tell DMA start transmit */ 1193 /* CSR_WRITE(sc, MDTSC, 1); */ 1194 1195 txs->txs_mbuf = m0; 1196 txs->txs_firstdesc = sc->sc_txnext; 1197 txs->txs_lastdesc = lasttx; 1198 txs->txs_ndesc = dmamap->dm_nsegs; 1199 1200 sc->sc_txfree -= txs->txs_ndesc; 1201 sc->sc_txnext = nexttx; 1202 sc->sc_txsfree--; 1203 sc->sc_txsnext = SCX_NEXTTXS(sc->sc_txsnext); 1204 /* 1205 * Pass the packet to any BPF listeners. 1206 */ 1207 bpf_mtap(ifp, m0, BPF_D_OUT); 1208 } 1209 1210 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1211 /* No more slots left; notify upper layer. */ 1212 ifp->if_flags |= IFF_OACTIVE; 1213 } 1214 if (sc->sc_txfree != ofree) { 1215 /* Set a watchdog timer in case the chip flakes out. */ 1216 ifp->if_timer = 5; 1217 } 1218 } 1219 1220 static int 1221 scx_intr(void *arg) 1222 { 1223 struct scx_softc *sc = arg; 1224 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1225 1226 (void)ifp; 1227 rxintr(sc); 1228 txreap(sc); 1229 return 1; 1230 } 1231 1232 static void 1233 txreap(struct scx_softc *sc) 1234 { 1235 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1236 struct scx_txsoft *txs; 1237 uint32_t txstat; 1238 int i; 1239 1240 ifp->if_flags &= ~IFF_OACTIVE; 1241 1242 for (i = sc->sc_txsdirty; sc->sc_txsfree != SCX_TXQUEUELEN; 1243 i = SCX_NEXTTXS(i), sc->sc_txsfree++) { 1244 txs = &sc->sc_txsoft[i]; 1245 1246 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1247 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1248 1249 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1250 if (txstat & T0_OWN) /* desc is still in use */ 1251 break; 1252 1253 /* There is no way to tell transmission status per frame */ 1254 1255 if_statinc(ifp, if_opackets); 1256 1257 sc->sc_txfree += txs->txs_ndesc; 1258 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1259 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1260 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1261 m_freem(txs->txs_mbuf); 1262 txs->txs_mbuf = NULL; 1263 } 1264 sc->sc_txsdirty = i; 1265 if (sc->sc_txsfree == SCX_TXQUEUELEN) 1266 ifp->if_timer = 0; 1267 } 1268 1269 static void 1270 rxintr(struct scx_softc *sc) 1271 { 1272 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1273 struct scx_rxsoft *rxs; 1274 struct mbuf *m; 1275 uint32_t rxstat; 1276 int i, len; 1277 1278 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = SCX_NEXTRX(i)) { 1279 rxs = &sc->sc_rxsoft[i]; 1280 1281 SCX_CDRXSYNC(sc, i, 1282 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1283 1284 rxstat = sc->sc_rxdescs[i].r0; 1285 if (rxstat & R0_OWN) /* desc is left empty */ 1286 break; 1287 1288 /* R0_FS | R0_LS must have been marked for this desc */ 1289 1290 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1291 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1292 1293 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1294 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1295 m = rxs->rxs_mbuf; 1296 1297 if (add_rxbuf(sc, i) != 0) { 1298 if_statinc(ifp, if_ierrors); 1299 SCX_INIT_RXDESC(sc, i); 1300 bus_dmamap_sync(sc->sc_dmat, 1301 rxs->rxs_dmamap, 0, 1302 rxs->rxs_dmamap->dm_mapsize, 1303 BUS_DMASYNC_PREREAD); 1304 continue; 1305 } 1306 1307 m_set_rcvif(m, ifp); 1308 m->m_pkthdr.len = m->m_len = len; 1309 1310 if (rxstat & R0_CSUM) { 1311 uint32_t csum = M_CSUM_IPv4; 1312 if (rxstat & R0_CERR) 1313 csum |= M_CSUM_IPv4_BAD; 1314 m->m_pkthdr.csum_flags |= csum; 1315 } 1316 if_percpuq_enqueue(ifp->if_percpuq, m); 1317 } 1318 sc->sc_rxptr = i; 1319 } 1320 1321 static int 1322 add_rxbuf(struct scx_softc *sc, int i) 1323 { 1324 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1325 struct mbuf *m; 1326 int error; 1327 1328 MGETHDR(m, M_DONTWAIT, MT_DATA); 1329 if (m == NULL) 1330 return ENOBUFS; 1331 1332 MCLGET(m, M_DONTWAIT); 1333 if ((m->m_flags & M_EXT) == 0) { 1334 m_freem(m); 1335 return ENOBUFS; 1336 } 1337 1338 if (rxs->rxs_mbuf != NULL) 1339 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1340 1341 rxs->rxs_mbuf = m; 1342 1343 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1344 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1345 if (error) { 1346 aprint_error_dev(sc->sc_dev, 1347 "can't load rx DMA map %d, error = %d\n", i, error); 1348 panic("add_rxbuf"); 1349 } 1350 1351 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1352 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1353 SCX_INIT_RXDESC(sc, i); 1354 1355 return 0; 1356 } 1357 1358 static int 1359 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1360 { 1361 int val, loop; 1362 1363 val = CSR_READ(sc, reg); 1364 if ((val & exist) == 0) 1365 return 0; 1366 loop = 3000; 1367 do { 1368 DELAY(10); 1369 val = CSR_READ(sc, reg); 1370 } while (--loop > 0 && (val & exist) != 0); 1371 return (loop > 0) ? 0 : ETIMEDOUT; 1372 } 1373 1374 static int 1375 mac_read(struct scx_softc *sc, int reg) 1376 { 1377 1378 CSR_WRITE(sc, MACCMD, reg); 1379 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1380 return CSR_READ(sc, MACDATA); 1381 } 1382 1383 static void 1384 mac_write(struct scx_softc *sc, int reg, int val) 1385 { 1386 1387 CSR_WRITE(sc, MACDATA, val); 1388 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1389 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1390 } 1391 1392 static int 1393 get_garclk(uint32_t freq) 1394 { 1395 int i; 1396 1397 for (i = 0; garclk[i].freq != 0; i++) { 1398 if (freq < garclk[i].freq) 1399 return garclk[i].bit; 1400 } 1401 return garclk[i - 1].bit; 1402 } 1403 1404 static void 1405 loaducode(struct scx_softc *sc) 1406 { 1407 uint32_t up, lo, sz; 1408 uint64_t addr; 1409 1410 sc->sc_ucodeloaded = 1; 1411 1412 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1413 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1414 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1415 sz *= 4; 1416 addr = ((uint64_t)up << 32) | lo; 1417 aprint_normal_dev(sc->sc_dev, "H2M ucode %u\n", sz); 1418 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1419 1420 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1421 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1422 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1423 sz *= 4; 1424 addr = ((uint64_t)up << 32) | lo; 1425 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1426 aprint_normal_dev(sc->sc_dev, "M2H ucode %u\n", sz); 1427 1428 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1429 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1430 sz *= 4; 1431 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1432 aprint_normal_dev(sc->sc_dev, "PKT ucode %u\n", sz); 1433 } 1434 1435 static void 1436 injectucode(struct scx_softc *sc, int port, 1437 bus_addr_t addr, bus_size_t size) 1438 { 1439 bus_space_handle_t bsh; 1440 bus_size_t off; 1441 uint32_t ucode; 1442 int i; 1443 1444 port &= 03; 1445 if (!bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1446 aprint_error_dev(sc->sc_dev, 1447 "eeprom map failure for ucode port 0x%x\n", port); 1448 return; 1449 } 1450 off = 0; 1451 for (i = 0; i < size; i++) { 1452 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1453 CSR_WRITE(sc, port, ucode); 1454 off += 4; 1455 } 1456 bus_space_unmap(sc->sc_st, bsh, size); 1457 } 1458
Indexes created Sat Sep 27 14:09:57 GMT 2025