if_scx.c revision 1.31
1 /* $NetBSD: if_scx.c,v 1.31 2021/12/21 11:07:51 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 /* 34 * Socionext SC2A11 SynQuacer NetSec GbE driver 35 * 36 * Multiple Tx and Rx queues exist inside and dedicated descriptor 37 * fields specifies which queue is to use. Three internal micro-processors 38 * to handle incoming frames, outgoing frames and packet data crypto 39 * processing. uP programs are stored in an external flash memory and 40 * have to be loaded by device driver. 41 * NetSec uses Synopsys DesignWare Core EMAC. DWC implementation 42 * register (0x20) is known to have 0x10.36 and feature register (0x1058) 43 * to report XX.XX. 44 */ 45 46 #define NOT_MP_SAFE 0 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.31 2021/12/21 11:07:51 nisimura Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/bus.h> 53 #include <sys/intr.h> 54 #include <sys/device.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/errno.h> 59 #include <sys/rndsource.h> 60 #include <sys/kernel.h> 61 #include <sys/systm.h> 62 63 #include <net/if.h> 64 #include <net/if_media.h> 65 #include <net/if_dl.h> 66 #include <net/if_ether.h> 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <net/bpf.h> 70 71 #include <dev/fdt/fdtvar.h> 72 #include <dev/acpi/acpireg.h> 73 #include <dev/acpi/acpivar.h> 74 #include <dev/acpi/acpi_intr.h> 75 76 /* SC2A11 GbE 64-bit paddr descriptor */ 77 struct tdes { 78 uint32_t t0, t1, t2, t3; 79 }; 80 81 struct rdes { 82 uint32_t r0, r1, r2, r3; 83 }; 84 85 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 86 #define T0_EOD (1U<<30) /* end of descriptor array */ 87 #define T0_DRID (24) /* 29:24 desc ring id */ 88 #define T0_PT (1U<<21) /* 23:21 "pass-through" */ 89 #define T0_TDRID (16) /* 20:16 target desc ring id: GMAC=15 */ 90 #define T0_FS (1U<<9) /* first segment of frame */ 91 #define T0_LS (1U<<8) /* last segment of frame */ 92 #define T0_CSUM (1U<<7) /* enable check sum offload */ 93 #define T0_TSO (1U<<6) /* enable TCP segment offload */ 94 #define T0_TRS (1U<<4) /* 5:4 "TRS" */ 95 /* T1 frame segment address 63:32 */ 96 /* T2 frame segment address 31:0 */ 97 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */ 98 99 #define R0_OWN (1U<<31) /* desc is empty */ 100 #define R0_EOD (1U<<30) /* end of descriptor array */ 101 #define R0_SDRID (24) /* 29:24 source desc ring id */ 102 #define R0_FR (1U<<23) /* found fragmented */ 103 #define R0_ER (1U<<21) /* Rx error indication */ 104 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 105 #define R0_TDRID (12) /* 15:12 target desc ring id */ 106 #define R0_FS (1U<<9) /* first segment of frame */ 107 #define R0_LS (1U<<8) /* last segment of frame */ 108 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 109 #define R0_CERR (2U<<6) /* 0: undone, 1: found ok, 2: bad */ 110 /* R1 frame address 63:32 */ 111 /* R2 frame address 31:0 */ 112 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 113 114 /* 115 * SC2A11 registers. 0x100 - 1204 116 */ 117 #define SWRESET 0x104 118 #define SRST_RUN (1U<<31) /* instruct start, 0 to stop */ 119 #define COMINIT 0x120 120 #define INIT_DB (1U<<2) /* ???; self clear when done */ 121 #define INIT_CLS (1U<<1) /* ???; self clear when done */ 122 #define PKTCTRL 0x140 /* pkt engine control */ 123 #define MODENRM (1U<<28) /* change mode to normal */ 124 #define ENJUMBO (1U<<27) /* allow jumbo frame */ 125 #define RPTCSUMERR (1U<<3) /* log Rx checksum error */ 126 #define RPTHDCOMP (1U<<2) /* log HD imcomplete condition */ 127 #define RPTHDERR (1U<<1) /* log HD error */ 128 #define DROPNOMATCH (1U<<0) /* drop no match frames */ 129 #define xINTSR 0x200 /* aggregated interrupt status */ 130 #define IRQ_RX (1U<<1) /* top level Rx interrupt */ 131 #define IRQ_TX (1U<<0) /* top level Rx interrupt */ 132 #define IRQ_UCODE (1U<<20) /* ucode load completed; W1C */ 133 #define xINTAEN 0x204 /* INT_A enable */ 134 #define xINTAE_SET 0x234 /* bit to set */ 135 #define xINTAE_CLR 0x238 /* bit to clr */ 136 #define xINTBEN 0x23c /* INT_B enable */ 137 #define xINTBE_SET 0x240 /* bit to set */ 138 #define xINTBE_CLR 0x244 /* bit to clr */ 139 #define TXISR 0x400 /* transmit status; W1C */ 140 #define TXIEN 0x404 /* tx interrupt enable */ 141 #define TXIE_SET 0x428 /* bit to set */ 142 #define TXIE_CLR 0x42c /* bit to clr */ 143 #define TXI_NTOWNR (1U<<17) /* ??? desc array got empty */ 144 #define TXI_TR_ERR (1U<<16) /* tx error */ 145 #define TXI_TXDONE (1U<<15) /* tx completed */ 146 #define TXI_TMREXP (1U<<14) /* coalesce timer expired */ 147 #define RXISR 0x440 /* receive status; W1C */ 148 #define RXIEN 0x444 /* rx interrupt enable */ 149 #define RXIE_SET 0x468 /* bit to set */ 150 #define RXIE_CLR 0x46c /* bit to clr */ 151 #define RXI_RC_ERR (1U<<16) /* rx error */ 152 #define RXI_PKTCNT (1U<<15) /* rx counter has new value */ 153 #define RXI_TMREXP (1U<<14) /* coalesce timer expired */ 154 /* 13 sets of special purpose desc interrupt handling register exist */ 155 #define TDBA_LO 0x408 /* tdes array base addr 31:0 */ 156 #define TDBA_HI 0x434 /* tdes array base addr 63:32 */ 157 #define RDBA_LO 0x448 /* rdes array base addr 31:0 */ 158 #define RDBA_HI 0x474 /* rdes array base addr 63:32 */ 159 /* 13 pairs of special purpose desc array base address register exist */ 160 #define TXCONF 0x430 161 #define RXCONF 0x470 162 #define DESCNF_UP (1U<<31) /* up-and-running */ 163 #define DESCNF_CHRST (1U<<30) /* channel reset */ 164 #define DESCNF_TMR (1U<<4) /* coalesce timer mode select */ 165 #define DESCNF_LE (1) /* little endian desc format */ 166 #define TXCOLMAX 0x410 /* tx intr coalesce upper bound */ 167 #define RXCOLMAX 0x454 /* rx intr coalesce upper bound */ 168 #define TXITIMER 0x420 /* coalesce timer usec, MSB to use */ 169 #define RXITIMER 0x460 /* coalesce timer usec, MSB to use */ 170 #define TXDONECNT 0x424 /* tx completed count, auto-zero */ 171 #define RXDONECNT 0x458 /* rx available count, auto-zero */ 172 #define UCODE_H2M 0x210 /* host2media engine ucode port */ 173 #define UCODE_M2H 0x21c /* media2host engine ucode port */ 174 #define CORESTAT 0x218 /* engine run state */ 175 #define PKTSTOP (1U<<2) 176 #define M2HSTOP (1U<<1) 177 #define H2MSTOP (1U<<0) 178 #define DMACTL_H2M 0x214 /* host2media engine control */ 179 #define DMACTL_M2H 0x220 /* media2host engine control */ 180 #define DMACTL_STOP (1U<<0) /* instruct stop; self-clear */ 181 #define UCODE_PKT 0x0d0 /* packet engine ucode port */ 182 #define CLKEN 0x100 /* clock distribution enable */ 183 #define CLK_G (1U<<5) /* feed clk domain E */ 184 #define CLK_C (1U<<1) /* feed clk domain C */ 185 #define CLK_D (1U<<0) /* feed clk domain D */ 186 #define CLK_ALL 0x23 /* all above; 0x24 ??? 0x3f ??? */ 187 188 /* GMAC register indirect access. thru MACCMD/MACDATA operation */ 189 #define MACDATA 0x11c0 /* gmac register rd/wr data */ 190 #define MACCMD 0x11c4 /* gmac register operation */ 191 #define CMD_IOWR (1U<<28) /* write op */ 192 #define CMD_BUSY (1U<<31) /* busy bit */ 193 #define MACSTAT 0x1024 /* gmac status; ??? */ 194 #define MACINTE 0x1028 /* interrupt enable; ??? */ 195 196 #define FLOWTHR 0x11cc /* flow control threshold */ 197 /* 31:16 pause threshold, 15:0 resume threshold */ 198 #define INTF_SEL 0x11d4 /* ??? */ 199 200 #define DESC_INIT 0x11fc /* write 1 for desc init, SC */ 201 #define DESC_SRST 0x1204 /* write 1 for desc sw reset, SC */ 202 #define MODE_TRANS 0x500 /* mode change completion status */ 203 #define N2T_DONE (1U<<20) /* normal->taiki change completed */ 204 #define T2N_DONE (1U<<19) /* taiki->normal change completed */ 205 #define MACADRH 0x10c /* ??? */ 206 #define MACADRL 0x110 /* ??? */ 207 #define MCVER 0x22c /* micro controller version */ 208 #define HWVER 0x230 /* hardware version */ 209 210 /* 211 * GMAC registers are mostly identical to Synopsys DesignWare Core 212 * Ethernet. These must be handled by indirect access. 213 */ 214 #define GMACMCR 0x0000 /* MAC configuration */ 215 #define MCR_IBN (1U<<30) /* ??? */ 216 #define MCR_CST (1U<<25) /* strip CRC */ 217 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 218 #define MCR_WD (1U<<23) /* allow long >2048 tx frame */ 219 #define MCR_JE (1U<<20) /* allow ~9018 tx jumbo frame */ 220 #define MCR_IFG (7U<<17) /* 19:17 IFG value 0~7 */ 221 #define MCR_DRCS (1U<<16) /* ignore (G)MII HDX Tx error */ 222 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII (_PS) */ 223 #define MCR_SPD100 (1U<<14) /* force speed 100 (_FES) */ 224 #define MCR_DO (1U<<13) /* don't receive my own HDX Tx frames */ 225 #define MCR_LOOP (1U<<12) /* run loop back */ 226 #define MCR_USEFDX (1U<<11) /* force full duplex */ 227 #define MCR_IPCEN (1U<<10) /* handle checksum */ 228 #define MCR_DR (1U<<9) /* attempt no tx retry, send once */ 229 #define MCR_LUD (1U<<8) /* link condition report when RGMII */ 230 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 231 #define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */ 232 #define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */ 233 #define MCR_PREA (3U) /* 1:0 preamble len. 0~2 */ 234 #define _MCR_FDX 0x0000280c /* XXX TBD */ 235 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 236 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 237 #define AFR_RA (1U<<31) /* accept all irrespective of filt. */ 238 #define AFR_HPF (1U<<10) /* hash+perfect filter, or hash only */ 239 #define AFR_SAF (1U<<9) /* source address filter */ 240 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 241 #define AFR_PCF (2U<<6) /* ??? */ 242 #define AFR_DBF (1U<<5) /* reject broadcast frame */ 243 #define AFR_PM (1U<<4) /* accept all multicast frame */ 244 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 245 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 246 #define AFR_UHTE (1U<<1) /* use hash table for unicast */ 247 #define AFR_PR (1U<<0) /* run promisc mode */ 248 #define GMACGAR 0x0010 /* MDIO operation */ 249 #define GAR_PHY (11) /* 15:11 mii phy */ 250 #define GAR_REG (6) /* 10:6 mii reg */ 251 #define GAR_CLK (2) /* 5:2 mdio clock tick ratio */ 252 #define GAR_IOWR (1U<<1) /* MDIO write op */ 253 #define GAR_BUSY (1U<<0) /* busy bit */ 254 #define GAR_MDIO_25_35MHZ 2 255 #define GAR_MDIO_35_60MHZ 3 256 #define GAR_MDIO_60_100MHZ 0 257 #define GAR_MDIO_100_150MHZ 1 258 #define GAR_MDIO_150_250MHZ 4 259 #define GAR_MDIO_250_300MHZ 5 260 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 261 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 262 /* 31:16 pause timer value, 5:4 pause timer threshold */ 263 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 264 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 265 #define GMACIMPL 0x0020 /* implementation id XX.YY (no use) */ 266 #define GMACISR 0x0038 /* interrupt status indication */ 267 #define GMACIMR 0x003c /* interrupt mask to inhibit */ 268 #define ISR_TS (1U<<9) /* time stamp operation detected */ 269 #define ISR_CO (1U<<7) /* Rx checksum offload completed */ 270 #define ISR_TX (1U<<6) /* Tx completed */ 271 #define ISR_RX (1U<<5) /* Rx completed */ 272 #define ISR_ANY (1U<<4) /* any of above 5-7 report */ 273 #define ISR_LC (1U<<0) /* link status change detected */ 274 #define GMACMAH0 0x0040 /* my own MAC address 47:32 */ 275 #define GMACMAL0 0x0044 /* my own MAC address 31:0 */ 276 #define GMACMAH(i) ((i)*8+0x40) /* supplemental MAC addr 1-15 */ 277 #define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */ 278 /* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */ 279 #define GMACAMAH(i) ((i)*8+0x800) /* supplemental MAC addr 16-31 */ 280 #define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */ 281 /* supplimental MAH bit-31: slot in use, no other bit is effective */ 282 #define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */ 283 #define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */ 284 #define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */ 285 #define EMACVTAG 0x001c /* VLAN tag control */ 286 #define VTAG_HASH (1U<<19) /* use VLAN tag hash table */ 287 #define VTAG_SVLAN (1U<<18) /* handle type 0x88A8 SVLAN frame */ 288 #define VTAG_INV (1U<<17) /* run inverse match logic */ 289 #define VTAG_ETV (1U<<16) /* use only 12bit VID field to match */ 290 /* 15:0 concat of PRIO+CFI+VID */ 291 #define GMACVHT 0x0588 /* 16-bit VLAN tag hash */ 292 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 293 #define MIISR_LUP (1U<<3) /* link up(1)/down(0) report */ 294 #define MIISR_SPD (3U<<1) /* 2:1 speed 10(0)/100(1)/1000(2) */ 295 #define MIISR_FDX (1U<<0) /* fdx detected */ 296 297 #define GMACLPIS 0x0030 /* LPI control & status */ 298 #define LPIS_TXA (1U<<19) /* complete Tx in progress and LPI */ 299 #define LPIS_PLS (1U<<17) 300 #define LPIS_EN (1U<<16) /* 1: enter LPI mode, 0: exit */ 301 #define LPIS_TEN (1U<<0) /* Tx LPI report */ 302 #define GMACLPIC 0x0034 /* LPI timer control */ 303 #define LPIC_LST (5) /* 16:5 ??? */ 304 #define LPIC_TWT (0) /* 15:0 ??? */ 305 #define GMACTSC 0x0700 /* timestamp control */ 306 #define GMACSTM 0x071c /* start time */ 307 #define GMACTGT 0x0720 /* target time */ 308 #define GMACTSS 0x0728 /* timestamp status */ 309 #define GMACPPS 0x072c /* PPS control */ 310 #define GMACPPS0 0x0764 /* PPS0 width */ 311 312 #define GMACBMR 0x1000 /* DMA bus mode control */ 313 /* 24 multiply by x8 for RPBL & PBL values 314 * 23 use RPBL for Rx DMA 315 * 22:17 RPBL 316 * 16 fixed burst 317 * 15:14 priority between Rx and Tx 318 * 3 rxtx ratio 41 319 * 2 rxtx ratio 31 320 * 1 rxtx ratio 21 321 * 0 rxtx ratio 11 322 * 13:8 PBL possible DMA burst length 323 * 7 select alternative 32-byte descriptor format for new features 324 * 6:2 descriptor spacing. 0 for adjuscent 325 * 0 GMAC reset op. self-clear 326 */ 327 #define _BMR 0x00412080 /* XXX TBD */ 328 #define _BMR0 0x00020181 /* XXX TBD */ 329 #define BMR_RST (1) /* reset op. self clear when done */ 330 #define GMACTPD 0x1004 /* write any to resume tdes */ 331 #define GMACRPD 0x1008 /* write any to resume rdes */ 332 #define GMACRDLA 0x100c /* rdes base address 32bit paddr */ 333 #define GMACTDLA 0x1010 /* tdes base address 32bit paddr */ 334 #define _RDLA 0x18000 /* system RAM for GMAC rdes */ 335 #define _TDLA 0x1c000 /* system RAM for GMAC tdes */ 336 #define GMACDSR 0x1014 /* DMA status detail report; W1C */ 337 #define GMACDIE 0x101c /* DMA interrupt enable */ 338 #define DMAI_LPI (1U<<30) /* LPI interrupt */ 339 #define DMAI_TTI (1U<<29) /* timestamp trigger interrupt */ 340 #define DMAI_GMI (1U<<27) /* management counter interrupt */ 341 #define DMAI_GLI (1U<<26) /* xMII link change detected */ 342 #define DMAI_EB (23) /* 25:23 DMA bus error detected */ 343 #define DMAI_TS (20) /* 22:20 Tx DMA state report */ 344 #define DMAI_RS (17) /* 29:17 Rx DMA state report */ 345 #define DMAI_NIS (1U<<16) /* normal interrupt summary; W1C */ 346 #define DMAI_AIS (1U<<15) /* abnormal interrupt summary; W1C */ 347 #define DMAI_ERI (1U<<14) /* the first Rx buffer is filled */ 348 #define DMAI_FBI (1U<<13) /* DMA bus error detected */ 349 #define DMAI_ETI (1U<<10) /* single frame Tx completed */ 350 #define DMAI_RWT (1U<<9) /* longer than 2048 frame received */ 351 #define DMAI_RPS (1U<<8) /* Rx process is now stopped */ 352 #define DMAI_RU (1U<<7) /* Rx descriptor not available */ 353 #define DMAI_RI (1U<<6) /* frame Rx completed by !R1_DIC */ 354 #define DMAI_UNF (1U<<5) /* Tx underflow detected */ 355 #define DMAI_OVF (1U<<4) /* receive buffer overflow detected */ 356 #define DMAI_TJT (1U<<3) /* longer than 2048 frame sent */ 357 #define DMAI_TU (1U<<2) /* Tx discriptor not available */ 358 #define DMAI_TPS (1U<<1) /* transmission is stopped */ 359 #define DMAI_TI (1U<<0) /* frame Tx completed by T0_IC */ 360 #define GMACOMR 0x1018 /* DMA operation mode */ 361 #define OMR_RSF (1U<<25) /* 1: Rx store&forword, 0: immed. */ 362 #define OMR_TSF (1U<<21) /* 1: Tx store&forward, 0: immed. */ 363 #define OMR_TTC (14) /* 16:14 Tx threshold */ 364 #define OMR_ST (1U<<13) /* run Tx DMA engine, 0 to stop */ 365 #define OMR_RFD (11) /* 12:11 Rx FIFO fill level */ 366 #define OMR_EFC (1U<<8) /* transmit PAUSE to throttle Rx lvl. */ 367 #define OMR_FEF (1U<<7) /* allow to receive error frames */ 368 #define OMR_SR (1U<<1) /* run Rx DMA engine, 0 to stop */ 369 #define GMACEVCS 0x1020 /* missed frame or ovf detected */ 370 #define GMACRWDT 0x1024 /* enable rx watchdog timer interrupt */ 371 #define GMACAXIB 0x1028 /* AXI bus mode control */ 372 #define GMACAXIS 0x102c /* AXI status report */ 373 /* 0x1048 current tx desc address */ 374 /* 0x104c current rx desc address */ 375 /* 0x1050 current tx buffer address */ 376 /* 0x1054 current rx buffer address */ 377 #define HWFEA 0x1058 /* DWC feature report */ 378 #define FEA_EXDESC (1U<<24) /* new desc layout */ 379 #define FEA_2COE (1U<<18) /* Rx type 2 IP checksum offload */ 380 #define FEA_1COE (1U<<17) /* Rx type 1 IP checksum offload */ 381 #define FEA_TXOE (1U<<16) /* Tx checksum offload */ 382 #define FEA_MMC (1U<<11) /* RMON management block */ 383 384 #define GMACEVCTL 0x0100 /* event counter control */ 385 #define EVC_FHP (1U<<5) /* full-half preset */ 386 #define EVC_CP (1U<<4) /* counters preset */ 387 #define EVC_MCF (1U<<3) /* MMC counter freeze */ 388 #define EVC_ROR (1U<<2) /* auto-zero on counter read */ 389 #define EVC_CSR (1U<<1) /* counter stop rollover */ 390 #define EVC_CR (1U<<0) /* reset counters */ 391 #define GMACEVCNT(i) ((i)*4+0x114) /* 80 event counters 0x114 - 0x284 */ 392 393 /* 394 * flash memory layout 395 * 0x00 - 07 48-bit MAC station address. 4 byte wise in BE order. 396 * 0x08 - 0b H->MAC xfer engine program start addr 63:32. 397 * 0x0c - 0f H2M program addr 31:0 (these are absolute addr, not offset) 398 * 0x10 - 13 H2M program length in 4 byte count. 399 * 0x14 - 0b M->HOST xfer engine program start addr 63:32. 400 * 0x18 - 0f M2H program addr 31:0 (absolute addr, not relative) 401 * 0x1c - 13 M2H program length in 4 byte count. 402 * 0x20 - 23 packet engine program addr 31:0, (absolute addr, not offset) 403 * 0x24 - 27 packet program length in 4 byte count. 404 * 405 * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0. 406 */ 407 408 /* 409 * all below are software constraction. 410 */ 411 #define MD_NTXSEGS 16 /* fixed */ 412 #define MD_TXQUEUELEN 8 /* tunable */ 413 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 414 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 415 #define MD_NTXDESC 128 416 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 417 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 418 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 419 420 #define MD_NRXDESC 64 /* tunable */ 421 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 422 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 423 424 struct control_data { 425 struct tdes cd_txdescs[MD_NTXDESC]; 426 struct rdes cd_rxdescs[MD_NRXDESC]; 427 }; 428 #define SCX_CDOFF(x) offsetof(struct control_data, x) 429 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 430 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 431 432 struct scx_txsoft { 433 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 434 bus_dmamap_t txs_dmamap; /* our DMA map */ 435 int txs_firstdesc; /* first descriptor in packet */ 436 int txs_lastdesc; /* last descriptor in packet */ 437 int txs_ndesc; /* # of descriptors used */ 438 }; 439 440 struct scx_rxsoft { 441 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 442 bus_dmamap_t rxs_dmamap; /* our DMA map */ 443 }; 444 445 struct scx_softc { 446 device_t sc_dev; /* generic device information */ 447 bus_space_tag_t sc_st; /* bus space tag */ 448 bus_space_handle_t sc_sh; /* bus space handle */ 449 bus_size_t sc_sz; /* csr map size */ 450 bus_space_handle_t sc_eesh; /* eeprom section handle */ 451 bus_size_t sc_eesz; /* eeprom map size */ 452 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 453 struct ethercom sc_ethercom; /* Ethernet common data */ 454 struct mii_data sc_mii; /* MII */ 455 callout_t sc_callout; /* PHY monitor callout */ 456 bus_dma_segment_t sc_seg; /* descriptor store seg */ 457 int sc_nseg; /* descriptor store nseg */ 458 void *sc_ih; /* interrupt cookie */ 459 int sc_phy_id; /* PHY address */ 460 int sc_flowflags; /* 802.3x PAUSE flow control */ 461 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 462 uint32_t sc_t0cotso; /* T0_CSUM | T0_TSO to run */ 463 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 464 int sc_phandle; /* fdt phandle */ 465 uint64_t sc_freq; 466 467 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 468 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 469 470 struct control_data *sc_control_data; 471 #define sc_txdescs sc_control_data->cd_txdescs 472 #define sc_rxdescs sc_control_data->cd_rxdescs 473 474 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 475 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 476 int sc_txfree; /* number of free Tx descriptors */ 477 int sc_txnext; /* next ready Tx descriptor */ 478 int sc_txsfree; /* number of free Tx jobs */ 479 int sc_txsnext; /* next ready Tx job */ 480 int sc_txsdirty; /* dirty Tx jobs */ 481 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 482 483 krndsource_t rnd_source; /* random source */ 484 #ifdef GMAC_EVENT_COUNTERS 485 /* 80 event counters exist */ 486 #endif 487 }; 488 489 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 490 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 491 492 #define SCX_CDTXSYNC(sc, x, n, ops) \ 493 do { \ 494 int __x, __n; \ 495 \ 496 __x = (x); \ 497 __n = (n); \ 498 \ 499 /* If it will wrap around, sync to the end of the ring. */ \ 500 if ((__x + __n) > MD_NTXDESC) { \ 501 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 502 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 503 (MD_NTXDESC - __x), (ops)); \ 504 __n -= (MD_NTXDESC - __x); \ 505 __x = 0; \ 506 } \ 507 \ 508 /* Now sync whatever is left. */ \ 509 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 510 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 511 } while (/*CONSTCOND*/0) 512 513 #define SCX_CDRXSYNC(sc, x, ops) \ 514 do { \ 515 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 516 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 517 } while (/*CONSTCOND*/0) 518 519 #define SCX_INIT_RXDESC(sc, x) \ 520 do { \ 521 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 522 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 523 struct mbuf *__m = __rxs->rxs_mbuf; \ 524 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 525 __m->m_data = __m->m_ext.ext_buf; \ 526 __rxd->r3 = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_len); \ 527 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 528 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 529 __rxd->r0 = htole32(R0_OWN | R0_FS | R0_LS); \ 530 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= htole32(R0_EOD); \ 531 } while (/*CONSTCOND*/0) 532 533 /* memory mapped CSR register access */ 534 #define CSR_READ(sc,off) \ 535 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 536 #define CSR_WRITE(sc,off,val) \ 537 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 538 539 /* flash memory access */ 540 #define EE_READ(sc,off) \ 541 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 542 543 static int scx_fdt_match(device_t, cfdata_t, void *); 544 static void scx_fdt_attach(device_t, device_t, void *); 545 static int scx_acpi_match(device_t, cfdata_t, void *); 546 static void scx_acpi_attach(device_t, device_t, void *); 547 548 const CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 549 scx_fdt_match, scx_fdt_attach, NULL, NULL); 550 551 const CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 552 scx_acpi_match, scx_acpi_attach, NULL, NULL); 553 554 static void scx_attach_i(struct scx_softc *); 555 static void scx_reset(struct scx_softc *); 556 static int scx_init(struct ifnet *); 557 static void scx_stop(struct ifnet *, int); 558 static int scx_ioctl(struct ifnet *, u_long, void *); 559 static void scx_set_rcvfilt(struct scx_softc *); 560 static void scx_start(struct ifnet *); 561 static void scx_watchdog(struct ifnet *); 562 static int scx_intr(void *); 563 static void txreap(struct scx_softc *); 564 static void rxintr(struct scx_softc *); 565 static int add_rxbuf(struct scx_softc *, int); 566 static void rxdrain(struct scx_softc *sc); 567 static void mii_statchg(struct ifnet *); 568 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 569 static int mii_readreg(device_t, int, int, uint16_t *); 570 static int mii_writereg(device_t, int, int, uint16_t); 571 static void phy_tick(void *); 572 573 static void loaducode(struct scx_softc *); 574 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 575 576 static int get_mdioclk(uint32_t); 577 578 #define WAIT_FOR_SET(sc, reg, set, fail) \ 579 wait_for_bits(sc, reg, set, ~0, fail) 580 #define WAIT_FOR_CLR(sc, reg, clr, fail) \ 581 wait_for_bits(sc, reg, 0, clr, fail) 582 583 static int 584 wait_for_bits(struct scx_softc *sc, int reg, 585 uint32_t set, uint32_t clr, uint32_t fail) 586 { 587 uint32_t val; 588 int ntries; 589 590 for (ntries = 0; ntries < 1000; ntries++) { 591 val = CSR_READ(sc, reg); 592 if ((val & set) || !(val & clr)) 593 return 0; 594 if (val & fail) 595 return 1; 596 DELAY(1); 597 } 598 return 1; 599 } 600 601 /* GMAC register indirect access */ 602 static int 603 mac_read(struct scx_softc *sc, int reg) 604 { 605 606 CSR_WRITE(sc, MACCMD, reg | CMD_BUSY); 607 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 608 return CSR_READ(sc, MACDATA); 609 } 610 611 static void 612 mac_write(struct scx_softc *sc, int reg, int val) 613 { 614 615 CSR_WRITE(sc, MACDATA, val); 616 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY); 617 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 618 } 619 620 /* dig and decode "clock-frequency" value for a given clkname */ 621 static int 622 get_clk_freq(int phandle, const char *clkname) 623 { 624 u_int index, n, cells; 625 const u_int *p; 626 int err, len, resid; 627 unsigned int freq = 0; 628 629 err = fdtbus_get_index(phandle, "clock-names", clkname, &index); 630 if (err == -1) 631 return -1; 632 p = fdtbus_get_prop(phandle, "clocks", &len); 633 if (p == NULL) 634 return -1; 635 for (n = 0, resid = len; resid > 0; n++) { 636 const int cc_phandle = 637 fdtbus_get_phandle_from_native(be32toh(p[0])); 638 if (of_getprop_uint32(cc_phandle, "#clock-cells", &cells)) 639 return -1; 640 if (n == index) { 641 if (of_getprop_uint32(cc_phandle, 642 "clock-frequency", &freq)) 643 return -1; 644 return freq; 645 } 646 resid -= (cells + 1) * 4; 647 p += (cells + 1) * 4; 648 } 649 return -1; 650 } 651 652 static const struct device_compatible_entry compat_data[] = { 653 { .compat = "socionext,synquacer-netsec" }, 654 DEVICE_COMPAT_EOL 655 }; 656 static const struct device_compatible_entry compatible[] = { 657 { .compat = "SCX0001" }, 658 DEVICE_COMPAT_EOL 659 }; 660 661 static int 662 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 663 { 664 struct fdt_attach_args * const faa = aux; 665 666 return of_compatible_match(faa->faa_phandle, compat_data); 667 } 668 669 static void 670 scx_fdt_attach(device_t parent, device_t self, void *aux) 671 { 672 struct scx_softc * const sc = device_private(self); 673 struct fdt_attach_args * const faa = aux; 674 const int phandle = faa->faa_phandle; 675 bus_space_handle_t bsh; 676 bus_space_handle_t eebsh; 677 bus_addr_t addr[2]; 678 bus_size_t size[2]; 679 char intrstr[128]; 680 int phy_phandle; 681 bus_addr_t phy_id; 682 const char *phy_type; 683 long ref_clk; 684 685 aprint_naive("\n"); 686 aprint_normal(": Socionext Gigabit Ethernet controller\n"); 687 688 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 689 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 690 aprint_error_dev(self, "unable to map device csr\n"); 691 return; 692 } 693 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 694 aprint_error_dev(self, "failed to decode interrupt\n"); 695 goto fail; 696 } 697 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 698 NOT_MP_SAFE, scx_intr, sc); 699 if (sc->sc_ih == NULL) { 700 aprint_error_dev(self, "couldn't establish interrupt\n"); 701 goto fail; 702 } 703 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 704 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 705 aprint_error_dev(self, "unable to map device eeprom\n"); 706 goto fail; 707 } 708 709 sc->sc_dev = self; 710 sc->sc_st = faa->faa_bst; 711 sc->sc_sh = bsh; 712 sc->sc_sz = size[0]; 713 sc->sc_eesh = eebsh; 714 sc->sc_eesz = size[1]; 715 sc->sc_dmat = faa->faa_dmat; 716 sc->sc_phandle = phandle; 717 718 phy_type = fdtbus_get_string(phandle, "phy-mode"); 719 if (phy_type == NULL) 720 aprint_error_dev(self, "missing 'phy-mode' property\n"); 721 phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 722 if (phy_phandle == -1 723 || fdtbus_get_reg(phy_phandle, 0, &phy_id, NULL) != 0) 724 phy_id = MII_PHY_ANY; 725 ref_clk = get_clk_freq(phandle, "phy_ref_clk"); 726 if (ref_clk == -1) 727 ref_clk = 250 * 1000 * 1000; 728 729 sc->sc_100mii = (phy_type && strncmp(phy_type, "rgmii", 5) != 0); 730 sc->sc_phy_id = phy_id; 731 sc->sc_freq = ref_clk; 732 733 scx_attach_i(sc); 734 return; 735 fail: 736 if (sc->sc_eesz) 737 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 738 if (sc->sc_sz) 739 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 740 return; 741 } 742 743 static int 744 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 745 { 746 struct acpi_attach_args *aa = aux; 747 748 return acpi_compatible_match(aa, compatible); 749 } 750 751 static void 752 scx_acpi_attach(device_t parent, device_t self, void *aux) 753 { 754 struct scx_softc * const sc = device_private(self); 755 struct acpi_attach_args * const aa = aux; 756 ACPI_HANDLE handle = aa->aa_node->ad_handle; 757 bus_space_handle_t bsh, eebsh; 758 struct acpi_resources res; 759 struct acpi_mem *mem; 760 struct acpi_irq *irq; 761 ACPI_INTEGER phy_type, phy_id, ref_freq; 762 ACPI_STATUS rv; 763 764 aprint_naive("\n"); 765 aprint_normal(": Socionext Gigabit Ethernet controller\n"); 766 767 rv = acpi_resource_parse(self, handle, "_CRS", 768 &res, &acpi_resource_parse_ops_default); 769 if (ACPI_FAILURE(rv)) { 770 aprint_error_dev(self, "missing crs resources\n"); 771 return; 772 } 773 mem = acpi_res_mem(&res, 0); 774 irq = acpi_res_irq(&res, 0); 775 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 776 aprint_error_dev(self, "incomplete crs resources\n"); 777 return; 778 } 779 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0, 780 &bsh) != 0) { 781 aprint_error_dev(self, "couldn't map registers\n"); 782 return; 783 } 784 sc->sc_sz = mem->ar_length; 785 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 786 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 787 if (sc->sc_ih == NULL) { 788 aprint_error_dev(self, "couldn't establish interrupt\n"); 789 goto fail; 790 } 791 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 792 if (mem == NULL || mem->ar_length == 0) { 793 aprint_error_dev(self, "incomplete eeprom resources\n"); 794 goto fail; 795 } 796 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0, 797 &eebsh)) { 798 aprint_error_dev(self, "couldn't map registers\n"); 799 goto fail; 800 } 801 sc->sc_eesz = mem->ar_length; 802 803 rv = acpi_dsd_integer(handle, "max-speed", &phy_type); 804 if (ACPI_FAILURE(rv)) { 805 aprint_error_dev(self, "missing 'max-speed' property\n"); 806 phy_type = 1000; 807 } 808 rv = acpi_dsd_integer(handle, "phy-channel", &phy_id); 809 if (ACPI_FAILURE(rv)) 810 phy_id = 7; 811 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 812 &ref_freq); 813 if (ACPI_FAILURE(rv)) 814 ref_freq = 250 * 1000 * 1000; 815 816 sc->sc_dev = self; 817 sc->sc_st = aa->aa_memt; 818 sc->sc_sh = bsh; 819 sc->sc_eesh = eebsh; 820 sc->sc_dmat = aa->aa_dmat64; 821 822 aprint_normal_dev(self, 823 "phy type %d, phy id %d, freq %ld\n", (int)phy_type, (int)phy_id, ref_freq); 824 sc->sc_100mii = (phy_type != 1000); 825 sc->sc_phy_id = (int)phy_id; 826 sc->sc_freq = ref_freq; 827 aprint_normal_dev(self, 828 "GMACGAR %08x\n", mac_read(sc, GMACGAR)); 829 830 scx_attach_i(sc); 831 832 acpi_resource_cleanup(&res); 833 return; 834 fail: 835 if (sc->sc_eesz > 0) 836 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 837 if (sc->sc_sz > 0) 838 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 839 acpi_resource_cleanup(&res); 840 return; 841 } 842 843 static void 844 scx_attach_i(struct scx_softc *sc) 845 { 846 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 847 struct mii_data * const mii = &sc->sc_mii; 848 struct ifmedia * const ifm = &mii->mii_media; 849 uint32_t which, dwimp, dwfea; 850 uint8_t enaddr[ETHER_ADDR_LEN]; 851 bus_dma_segment_t seg; 852 uint32_t csr; 853 int i, nseg, error = 0; 854 855 which = CSR_READ(sc, HWVER); /* Socionext version 5.00xx */ 856 dwimp = mac_read(sc, GMACIMPL); /* DWC EMAC XX.YY */ 857 dwfea = mac_read(sc, HWFEA); /* DWC feature */ 858 aprint_normal_dev(sc->sc_dev, 859 "Socionext NetSec GbE %x.%x" 860 " (impl 0x%x, feature 0x%x)\n", 861 which >> 16, which & 0xffff, 862 dwimp, dwfea); 863 864 /* fetch MAC address in flash. stored in big endian order */ 865 csr = EE_READ(sc, 0x00); 866 enaddr[0] = csr >> 24; 867 enaddr[1] = csr >> 16; 868 enaddr[2] = csr >> 8; 869 enaddr[3] = csr; 870 csr = EE_READ(sc, 0x04); 871 enaddr[4] = csr >> 24; 872 enaddr[5] = csr >> 16; 873 aprint_normal_dev(sc->sc_dev, 874 "Ethernet address %s\n", ether_sprintf(enaddr)); 875 876 sc->sc_mdclk = get_mdioclk(sc->sc_freq) << GAR_CLK; /* 5:2 clk ratio */ 877 878 loaducode(sc); 879 880 mii->mii_ifp = ifp; 881 mii->mii_readreg = mii_readreg; 882 mii->mii_writereg = mii_writereg; 883 mii->mii_statchg = mii_statchg; 884 885 sc->sc_ethercom.ec_mii = mii; 886 ifmedia_init(ifm, 0, ether_mediachange, scx_ifmedia_sts); 887 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 888 MII_OFFSET_ANY, MIIF_DOPAUSE); 889 if (LIST_FIRST(&mii->mii_phys) == NULL) { 890 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 891 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 892 } else 893 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 894 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 895 896 /* 897 * Allocate the control data structures, and create and load the 898 * DMA map for it. 899 */ 900 error = bus_dmamem_alloc(sc->sc_dmat, 901 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 902 if (error != 0) { 903 aprint_error_dev(sc->sc_dev, 904 "unable to allocate control data, error = %d\n", error); 905 goto fail_0; 906 } 907 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 908 sizeof(struct control_data), (void **)&sc->sc_control_data, 909 BUS_DMA_COHERENT); 910 if (error != 0) { 911 aprint_error_dev(sc->sc_dev, 912 "unable to map control data, error = %d\n", error); 913 goto fail_1; 914 } 915 error = bus_dmamap_create(sc->sc_dmat, 916 sizeof(struct control_data), 1, 917 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 918 if (error != 0) { 919 aprint_error_dev(sc->sc_dev, 920 "unable to create control data DMA map, " 921 "error = %d\n", error); 922 goto fail_2; 923 } 924 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 925 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 926 if (error != 0) { 927 aprint_error_dev(sc->sc_dev, 928 "unable to load control data DMA map, error = %d\n", 929 error); 930 goto fail_3; 931 } 932 for (i = 0; i < MD_TXQUEUELEN; i++) { 933 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 934 MD_NTXSEGS, MCLBYTES, 0, 0, 935 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 936 aprint_error_dev(sc->sc_dev, 937 "unable to create tx DMA map %d, error = %d\n", 938 i, error); 939 goto fail_4; 940 } 941 } 942 for (i = 0; i < MD_NRXDESC; i++) { 943 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 944 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 945 aprint_error_dev(sc->sc_dev, 946 "unable to create rx DMA map %d, error = %d\n", 947 i, error); 948 goto fail_5; 949 } 950 sc->sc_rxsoft[i].rxs_mbuf = NULL; 951 } 952 sc->sc_seg = seg; 953 sc->sc_nseg = nseg; 954 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 955 956 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 957 ifp->if_softc = sc; 958 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 959 ifp->if_ioctl = scx_ioctl; 960 ifp->if_start = scx_start; 961 ifp->if_watchdog = scx_watchdog; 962 ifp->if_init = scx_init; 963 ifp->if_stop = scx_stop; 964 IFQ_SET_READY(&ifp->if_snd); 965 966 sc->sc_flowflags = 0; 967 968 if_attach(ifp); 969 if_deferred_start_init(ifp, NULL); 970 ether_ifattach(ifp, enaddr); 971 972 callout_init(&sc->sc_callout, 0); 973 callout_setfunc(&sc->sc_callout, phy_tick, sc); 974 975 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 976 RND_TYPE_NET, RND_FLAG_DEFAULT); 977 978 return; 979 980 fail_5: 981 for (i = 0; i < MD_NRXDESC; i++) { 982 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 983 bus_dmamap_destroy(sc->sc_dmat, 984 sc->sc_rxsoft[i].rxs_dmamap); 985 } 986 fail_4: 987 for (i = 0; i < MD_TXQUEUELEN; i++) { 988 if (sc->sc_txsoft[i].txs_dmamap != NULL) 989 bus_dmamap_destroy(sc->sc_dmat, 990 sc->sc_txsoft[i].txs_dmamap); 991 } 992 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 993 fail_3: 994 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 995 fail_2: 996 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 997 sizeof(struct control_data)); 998 fail_1: 999 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 1000 fail_0: 1001 if (sc->sc_phandle) 1002 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 1003 else 1004 acpi_intr_disestablish(sc->sc_ih); 1005 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 1006 return; 1007 } 1008 1009 static void 1010 scx_reset(struct scx_softc *sc) 1011 { 1012 int loop = 0, busy; 1013 1014 mac_write(sc, GMACOMR, 0); 1015 mac_write(sc, GMACBMR, BMR_RST); 1016 do { 1017 DELAY(1); 1018 busy = mac_read(sc, GMACBMR) & BMR_RST; 1019 } while (++loop < 3000 && busy); 1020 mac_write(sc, GMACBMR, _BMR); 1021 mac_write(sc, GMACAFR, 0); 1022 1023 CSR_WRITE(sc, CLKEN, CLK_ALL); /* distribute clock sources */ 1024 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 1025 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */ 1026 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS); 1027 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0); 1028 1029 CSR_WRITE(sc, TXISR, ~0); 1030 CSR_WRITE(sc, xINTAE_CLR, ~0); 1031 1032 mac_write(sc, GMACEVCTL, 1); 1033 } 1034 1035 static int 1036 scx_init(struct ifnet *ifp) 1037 { 1038 struct scx_softc *sc = ifp->if_softc; 1039 const uint8_t *ea = CLLADDR(ifp->if_sadl); 1040 paddr_t paddr; 1041 uint32_t csr; 1042 int i, error; 1043 1044 /* Cancel pending I/O. */ 1045 scx_stop(ifp, 0); 1046 1047 /* Reset the chip to a known state. */ 1048 scx_reset(sc); 1049 1050 /* build sane Tx */ 1051 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 1052 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 1053 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 1054 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1055 sc->sc_txfree = MD_NTXDESC; 1056 sc->sc_txnext = 0; 1057 for (i = 0; i < MD_TXQUEUELEN; i++) 1058 sc->sc_txsoft[i].txs_mbuf = NULL; 1059 sc->sc_txsfree = MD_TXQUEUELEN; 1060 sc->sc_txsnext = 0; 1061 sc->sc_txsdirty = 0; 1062 1063 /* load Rx descriptors with fresh mbuf */ 1064 for (i = 0; i < MD_NRXDESC; i++) { 1065 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 1066 if ((error = add_rxbuf(sc, i)) != 0) { 1067 aprint_error_dev(sc->sc_dev, 1068 "unable to allocate or map rx " 1069 "buffer %d, error = %d\n", 1070 i, error); 1071 rxdrain(sc); 1072 goto out; 1073 } 1074 } 1075 else 1076 SCX_INIT_RXDESC(sc, i); 1077 } 1078 sc->sc_rxdescs[MD_NRXDESC - 1].r0 = R0_EOD; 1079 sc->sc_rxptr = 0; 1080 sc->sc_rxptr = 0; 1081 1082 paddr = SCX_CDTXADDR(sc, 0); /* tdes array (ring#0) */ 1083 mac_write(sc, TDBA_HI, BUS_ADDR_HI32(paddr)); 1084 mac_write(sc, TDBA_LO, BUS_ADDR_LO32(paddr)); 1085 paddr = SCX_CDRXADDR(sc, 0); /* rdes array (ring#1) */ 1086 mac_write(sc, RDBA_HI, BUS_ADDR_HI32(paddr)); 1087 mac_write(sc, RDBA_LO, BUS_ADDR_LO32(paddr)); 1088 1089 CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */ 1090 CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian */ 1091 1092 /* set my address in perfect match slot 0. little endian order */ 1093 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 1094 mac_write(sc, GMACMAL0, csr); 1095 csr = (ea[5] << 8) | ea[4]; 1096 mac_write(sc, GMACMAH0, csr); 1097 1098 /* accept multicast frame or run promisc mode */ 1099 scx_set_rcvfilt(sc); 1100 1101 /* set current media */ 1102 if ((error = ether_mediachange(ifp)) != 0) 1103 goto out; 1104 1105 CSR_WRITE(sc, DESC_SRST, 01); 1106 WAIT_FOR_CLR(sc, DESC_SRST, 01, 0); 1107 1108 CSR_WRITE(sc, DESC_INIT, 01); 1109 WAIT_FOR_CLR(sc, DESC_INIT, 01, 0); 1110 1111 CSR_WRITE(sc, GMACRDLA, _RDLA); /* GMAC rdes store */ 1112 CSR_WRITE(sc, GMACTDLA, _TDLA); /* GMAC tdes store */ 1113 1114 CSR_WRITE(sc, FLOWTHR, (48<<16) | 36); /* pause|resume threshold */ 1115 mac_write(sc, GMACFCR, 256 << 16); /* 31:16 pause value */ 1116 1117 CSR_WRITE(sc, RXIE_CLR, ~0); /* clear Rx interrupt enable */ 1118 CSR_WRITE(sc, TXIE_CLR, ~0); /* clear Tx interrupt enable */ 1119 1120 CSR_WRITE(sc, RXCOLMAX, 8); /* Rx coalesce upper bound */ 1121 CSR_WRITE(sc, TXCOLMAX, 8); /* Tx coalesce upper bound */ 1122 CSR_WRITE(sc, RXITIMER, 500); /* Rx co. timer usec */ 1123 CSR_WRITE(sc, TXITIMER, 500); /* Tx co. timer usec */ 1124 1125 CSR_WRITE(sc, RXIE_SET, RXI_RC_ERR | RXI_PKTCNT | RXI_TMREXP); 1126 CSR_WRITE(sc, TXIE_SET, TXI_TR_ERR | TXI_TXDONE | TXI_TMREXP); 1127 1128 CSR_WRITE(sc, xINTAE_SET, IRQ_RX | IRQ_TX); 1129 1130 /* kick to start GMAC engine */ 1131 csr = mac_read(sc, GMACOMR); 1132 mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST); 1133 1134 ifp->if_flags |= IFF_RUNNING; 1135 ifp->if_flags &= ~IFF_OACTIVE; 1136 1137 /* start one second timer */ 1138 callout_schedule(&sc->sc_callout, hz); 1139 out: 1140 return error; 1141 } 1142 1143 static void 1144 scx_stop(struct ifnet *ifp, int disable) 1145 { 1146 struct scx_softc *sc = ifp->if_softc; 1147 1148 /* Stop the one second clock. */ 1149 callout_stop(&sc->sc_callout); 1150 1151 /* Down the MII. */ 1152 mii_down(&sc->sc_mii); 1153 1154 /* Mark the interface down and cancel the watchdog timer. */ 1155 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1156 ifp->if_timer = 0; 1157 1158 CSR_WRITE(sc, xINTAE_CLR, ~0); 1159 CSR_WRITE(sc, TXISR, ~0); 1160 CSR_WRITE(sc, RXISR, ~0); 1161 1162 if (CSR_READ(sc, CORESTAT) != 0) { 1163 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP); 1164 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP); 1165 1166 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP, 0); 1167 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP, 0); 1168 } 1169 } 1170 1171 static int 1172 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1173 { 1174 struct scx_softc *sc = ifp->if_softc; 1175 struct ifreq *ifr = (struct ifreq *)data; 1176 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1177 int s, error; 1178 1179 s = splnet(); 1180 1181 switch (cmd) { 1182 case SIOCSIFMEDIA: 1183 /* Flow control requires full-duplex mode. */ 1184 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1185 (ifr->ifr_media & IFM_FDX) == 0) 1186 ifr->ifr_media &= ~IFM_ETH_FMASK; 1187 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1188 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1189 /* We can do both TXPAUSE and RXPAUSE. */ 1190 ifr->ifr_media |= 1191 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1192 } 1193 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1194 } 1195 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 1196 break; 1197 default: 1198 error = ether_ioctl(ifp, cmd, data); 1199 if (error != ENETRESET) 1200 break; 1201 error = 0; 1202 if (cmd == SIOCSIFCAP) 1203 error = (*ifp->if_init)(ifp); 1204 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1205 ; 1206 else if (ifp->if_flags & IFF_RUNNING) { 1207 /* 1208 * Multicast list has changed; set the hardware filter 1209 * accordingly. 1210 */ 1211 scx_set_rcvfilt(sc); 1212 } 1213 break; 1214 } 1215 1216 splx(s); 1217 return error; 1218 } 1219 1220 static uint32_t 1221 bit_reverse_32(uint32_t x) 1222 { 1223 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 1224 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 1225 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 1226 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 1227 return (x >> 16) | (x << 16); 1228 } 1229 1230 static void 1231 scx_set_rcvfilt(struct scx_softc *sc) 1232 { 1233 struct ethercom * const ec = &sc->sc_ethercom; 1234 struct ifnet * const ifp = &ec->ec_if; 1235 struct ether_multistep step; 1236 struct ether_multi *enm; 1237 uint32_t mchash[2]; /* 2x 32 = 64 bit */ 1238 uint32_t csr, crc; 1239 int i; 1240 1241 csr = mac_read(sc, GMACAFR); 1242 csr &= ~(AFR_PR | AFR_PM | AFR_MHTE | AFR_HPF); 1243 mac_write(sc, GMACAFR, csr); 1244 1245 /* clear 15 entry supplemental perfect match filter */ 1246 for (i = 1; i < 16; i++) 1247 mac_write(sc, GMACMAH(i), 0); 1248 /* build 64 bit multicast hash filter */ 1249 crc = mchash[1] = mchash[0] = 0; 1250 1251 ETHER_LOCK(ec); 1252 if (ifp->if_flags & IFF_PROMISC) { 1253 ec->ec_flags |= ETHER_F_ALLMULTI; 1254 ETHER_UNLOCK(ec); 1255 /* run promisc. mode */ 1256 csr |= AFR_PR; 1257 goto update; 1258 } 1259 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1260 ETHER_FIRST_MULTI(step, ec, enm); 1261 i = 1; /* slot 0 is occupied */ 1262 while (enm != NULL) { 1263 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1264 /* 1265 * We must listen to a range of multicast addresses. 1266 * For now, just accept all multicasts, rather than 1267 * trying to set only those filter bits needed to match 1268 * the range. (At this time, the only use of address 1269 * ranges is for IP multicast routing, for which the 1270 * range is big enough to require all bits set.) 1271 */ 1272 ec->ec_flags |= ETHER_F_ALLMULTI; 1273 ETHER_UNLOCK(ec); 1274 /* accept all multi */ 1275 csr |= AFR_PM; 1276 goto update; 1277 } 1278 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 1279 if (i < 16) { 1280 /* use 15 entry perfect match filter */ 1281 uint32_t addr; 1282 uint8_t *ep = enm->enm_addrlo; 1283 addr = (ep[3] << 24) | (ep[2] << 16) 1284 | (ep[1] << 8) | ep[0]; 1285 mac_write(sc, GMACMAL(i), addr); 1286 addr = (ep[5] << 8) | ep[4]; 1287 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1288 } else { 1289 /* use hash table when too many */ 1290 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1291 crc = bit_reverse_32(~crc); 1292 /* 1(31) 5(30:26) bit sampling */ 1293 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 1294 } 1295 ETHER_NEXT_MULTI(step, enm); 1296 i++; 1297 } 1298 ETHER_UNLOCK(ec); 1299 if (crc) 1300 csr |= AFR_MHTE; 1301 csr |= AFR_HPF; /* use hash+perfect */ 1302 mac_write(sc, GMACMHTH, mchash[1]); 1303 mac_write(sc, GMACMHTL, mchash[0]); 1304 update: 1305 /* With PR or PM, MHTE/MHTL/MHTH are never consulted. really? */ 1306 mac_write(sc, GMACAFR, csr); 1307 return; 1308 } 1309 1310 static void 1311 scx_start(struct ifnet *ifp) 1312 { 1313 struct scx_softc *sc = ifp->if_softc; 1314 struct mbuf *m0; 1315 struct scx_txsoft *txs; 1316 bus_dmamap_t dmamap; 1317 int error, nexttx, lasttx, ofree, seg; 1318 uint32_t tdes0; 1319 1320 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1321 return; 1322 1323 /* Remember the previous number of free descriptors. */ 1324 ofree = sc->sc_txfree; 1325 1326 /* 1327 * Loop through the send queue, setting up transmit descriptors 1328 * until we drain the queue, or use up all available transmit 1329 * descriptors. 1330 */ 1331 for (;;) { 1332 IFQ_POLL(&ifp->if_snd, m0); 1333 if (m0 == NULL) 1334 break; 1335 1336 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1337 txreap(sc); 1338 if (sc->sc_txsfree == 0) 1339 break; 1340 } 1341 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1342 dmamap = txs->txs_dmamap; 1343 1344 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1345 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1346 if (error) { 1347 if (error == EFBIG) { 1348 aprint_error_dev(sc->sc_dev, 1349 "Tx packet consumes too many " 1350 "DMA segments, dropping...\n"); 1351 IFQ_DEQUEUE(&ifp->if_snd, m0); 1352 m_freem(m0); 1353 continue; 1354 } 1355 /* Short on resources, just stop for now. */ 1356 break; 1357 } 1358 1359 if (dmamap->dm_nsegs > sc->sc_txfree) { 1360 /* 1361 * Not enough free descriptors to transmit this 1362 * packet. We haven't committed anything yet, 1363 * so just unload the DMA map, put the packet 1364 * back on the queue, and punt. Notify the upper 1365 * layer that there are not more slots left. 1366 */ 1367 ifp->if_flags |= IFF_OACTIVE; 1368 bus_dmamap_unload(sc->sc_dmat, dmamap); 1369 break; 1370 } 1371 1372 IFQ_DEQUEUE(&ifp->if_snd, m0); 1373 1374 /* 1375 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1376 */ 1377 1378 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1379 BUS_DMASYNC_PREWRITE); 1380 1381 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1382 lasttx = -1; 1383 for (nexttx = sc->sc_txnext, seg = 0; 1384 seg < dmamap->dm_nsegs; 1385 seg++, nexttx = MD_NEXTTX(nexttx)) { 1386 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1387 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1388 /* 1389 * If this is the first descriptor we're 1390 * enqueueing, don't set the OWN bit just 1391 * yet. That could cause a race condition. 1392 * We'll do it below. 1393 */ 1394 tdes->t3 = htole32(dmamap->dm_segs[seg].ds_len); 1395 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1396 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1397 tdes->t0 = htole32(tdes0 | (tdes->t0 & T0_EOD) | 1398 (15 << T0_TDRID) | T0_PT | 1399 sc->sc_t0cotso | T0_TRS); 1400 tdes0 = T0_OWN; /* 2nd and other segments */ 1401 /* NB; t0 DRID field contains zero */ 1402 lasttx = nexttx; 1403 } 1404 1405 /* Write deferred 1st segment T0_OWN at the final stage */ 1406 sc->sc_txdescs[lasttx].t0 |= htole32(T0_LS); 1407 sc->sc_txdescs[sc->sc_txnext].t0 |= htole32(T0_FS | T0_OWN); 1408 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1410 1411 /* Tell DMA start transmit */ 1412 mac_write(sc, GMACTPD, 1); 1413 1414 txs->txs_mbuf = m0; 1415 txs->txs_firstdesc = sc->sc_txnext; 1416 txs->txs_lastdesc = lasttx; 1417 txs->txs_ndesc = dmamap->dm_nsegs; 1418 1419 sc->sc_txfree -= txs->txs_ndesc; 1420 sc->sc_txnext = nexttx; 1421 sc->sc_txsfree--; 1422 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1423 /* 1424 * Pass the packet to any BPF listeners. 1425 */ 1426 bpf_mtap(ifp, m0, BPF_D_OUT); 1427 } 1428 1429 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1430 /* No more slots left; notify upper layer. */ 1431 ifp->if_flags |= IFF_OACTIVE; 1432 } 1433 if (sc->sc_txfree != ofree) { 1434 /* Set a watchdog timer in case the chip flakes out. */ 1435 ifp->if_timer = 5; 1436 } 1437 } 1438 1439 static void 1440 scx_watchdog(struct ifnet *ifp) 1441 { 1442 struct scx_softc *sc = ifp->if_softc; 1443 1444 /* 1445 * Since we're not interrupting every packet, sweep 1446 * up before we report an error. 1447 */ 1448 txreap(sc); 1449 1450 if (sc->sc_txfree != MD_NTXDESC) { 1451 aprint_error_dev(sc->sc_dev, 1452 "device timeout (txfree %d txsfree %d txnext %d)\n", 1453 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1454 if_statinc(ifp, if_oerrors); 1455 1456 /* Reset the interface. */ 1457 scx_init(ifp); 1458 } 1459 1460 scx_start(ifp); 1461 } 1462 1463 static int 1464 scx_intr(void *arg) 1465 { 1466 struct scx_softc *sc = arg; 1467 uint32_t enable, status; 1468 1469 status = CSR_READ(sc, xINTSR); /* not W1C */ 1470 enable = CSR_READ(sc, xINTAEN); 1471 if ((status & enable) == 0) 1472 return 0; 1473 if (status & (IRQ_TX | IRQ_RX)) { 1474 CSR_WRITE(sc, xINTAE_CLR, (IRQ_TX | IRQ_RX)); 1475 1476 status = CSR_READ(sc, RXISR); 1477 CSR_WRITE(sc, RXISR, status); 1478 if (status & RXI_RC_ERR) 1479 aprint_error_dev(sc->sc_dev, "Rx error\n"); 1480 if (status & (RXI_PKTCNT | RXI_TMREXP)) { 1481 rxintr(sc); 1482 (void)CSR_READ(sc, RXDONECNT); /* clear RXI_RXDONE */ 1483 } 1484 1485 status = CSR_READ(sc, TXISR); 1486 CSR_WRITE(sc, TXISR, status); 1487 if (status & TXI_TR_ERR) 1488 aprint_error_dev(sc->sc_dev, "Tx error\n"); 1489 if (status & (TXI_TXDONE | TXI_TMREXP)) { 1490 txreap(sc); 1491 (void)CSR_READ(sc, TXDONECNT); /* clear TXI_TXDONE */ 1492 } 1493 1494 CSR_WRITE(sc, xINTAE_SET, (IRQ_TX | IRQ_RX)); 1495 } 1496 return 1; 1497 } 1498 1499 static void 1500 txreap(struct scx_softc *sc) 1501 { 1502 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1503 struct scx_txsoft *txs; 1504 uint32_t txstat; 1505 int i; 1506 1507 ifp->if_flags &= ~IFF_OACTIVE; 1508 1509 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1510 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1511 txs = &sc->sc_txsoft[i]; 1512 1513 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1514 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1515 1516 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].t0); 1517 if (txstat & T0_OWN) /* desc is still in use */ 1518 break; 1519 1520 /* There is no way to tell transmission status per frame */ 1521 1522 if_statinc(ifp, if_opackets); 1523 1524 sc->sc_txfree += txs->txs_ndesc; 1525 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1526 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1527 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1528 m_freem(txs->txs_mbuf); 1529 txs->txs_mbuf = NULL; 1530 } 1531 sc->sc_txsdirty = i; 1532 if (sc->sc_txsfree == MD_TXQUEUELEN) 1533 ifp->if_timer = 0; 1534 } 1535 1536 static void 1537 rxintr(struct scx_softc *sc) 1538 { 1539 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1540 struct scx_rxsoft *rxs; 1541 struct mbuf *m; 1542 uint32_t rxstat; 1543 int i, len; 1544 1545 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1546 rxs = &sc->sc_rxsoft[i]; 1547 1548 SCX_CDRXSYNC(sc, i, 1549 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1550 1551 rxstat = le32toh(sc->sc_rxdescs[i].r0); 1552 if (rxstat & R0_OWN) /* desc is left empty */ 1553 break; 1554 1555 /* R0_FS | R0_LS must have been marked for this desc */ 1556 1557 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1558 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1559 1560 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1561 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1562 m = rxs->rxs_mbuf; 1563 1564 if (add_rxbuf(sc, i) != 0) { 1565 if_statinc(ifp, if_ierrors); 1566 SCX_INIT_RXDESC(sc, i); 1567 bus_dmamap_sync(sc->sc_dmat, 1568 rxs->rxs_dmamap, 0, 1569 rxs->rxs_dmamap->dm_mapsize, 1570 BUS_DMASYNC_PREREAD); 1571 continue; 1572 } 1573 1574 m_set_rcvif(m, ifp); 1575 m->m_pkthdr.len = m->m_len = len; 1576 1577 if (rxstat & R0_CSUM) { 1578 uint32_t csum = M_CSUM_IPv4; 1579 if (rxstat & R0_CERR) 1580 csum |= M_CSUM_IPv4_BAD; 1581 m->m_pkthdr.csum_flags |= csum; 1582 } 1583 if_percpuq_enqueue(ifp->if_percpuq, m); 1584 } 1585 sc->sc_rxptr = i; 1586 } 1587 1588 static int 1589 add_rxbuf(struct scx_softc *sc, int i) 1590 { 1591 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1592 struct mbuf *m; 1593 int error; 1594 1595 MGETHDR(m, M_DONTWAIT, MT_DATA); 1596 if (m == NULL) 1597 return ENOBUFS; 1598 1599 MCLGET(m, M_DONTWAIT); 1600 if ((m->m_flags & M_EXT) == 0) { 1601 m_freem(m); 1602 return ENOBUFS; 1603 } 1604 1605 if (rxs->rxs_mbuf != NULL) 1606 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1607 1608 rxs->rxs_mbuf = m; 1609 1610 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1611 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1612 if (error) { 1613 aprint_error_dev(sc->sc_dev, 1614 "can't load rx DMA map %d, error = %d\n", i, error); 1615 panic("add_rxbuf"); 1616 } 1617 1618 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1619 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1620 SCX_INIT_RXDESC(sc, i); 1621 1622 return 0; 1623 } 1624 1625 static void 1626 rxdrain(struct scx_softc *sc) 1627 { 1628 struct scx_rxsoft *rxs; 1629 int i; 1630 1631 for (i = 0; i < MD_NRXDESC; i++) { 1632 rxs = &sc->sc_rxsoft[i]; 1633 if (rxs->rxs_mbuf != NULL) { 1634 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1635 m_freem(rxs->rxs_mbuf); 1636 rxs->rxs_mbuf = NULL; 1637 } 1638 } 1639 } 1640 1641 void 1642 mii_statchg(struct ifnet *ifp) 1643 { 1644 struct scx_softc *sc = ifp->if_softc; 1645 struct mii_data *mii = &sc->sc_mii; 1646 const int Mbps[4] = { 10, 100, 1000, 0 }; 1647 uint32_t miisr, mcr, fcr; 1648 int spd; 1649 1650 /* decode MIISR register value */ 1651 miisr = mac_read(sc, GMACMIISR); 1652 spd = Mbps[(miisr & MIISR_SPD) >> 1]; 1653 #if 1 1654 static uint32_t oldmiisr = 0; 1655 if (miisr != oldmiisr) { 1656 printf("MII link status (0x%x) %s", 1657 miisr, (miisr & MIISR_LUP) ? "up" : "down"); 1658 if (miisr & MIISR_LUP) { 1659 printf(" spd%d", spd); 1660 if (miisr & MIISR_FDX) 1661 printf(",full-duplex"); 1662 } 1663 printf("\n"); 1664 } 1665 #endif 1666 /* Get flow control negotiation result. */ 1667 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1668 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1669 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1670 1671 /* Adjust speed 1000/100/10. */ 1672 mcr = mac_read(sc, GMACMCR); 1673 if (spd == 1000) 1674 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1675 else { 1676 if (spd == 100 && sc->sc_100mii) 1677 mcr |= MCR_SPD100; 1678 mcr |= MCR_USEMII; 1679 } 1680 mcr |= MCR_CST | MCR_JE; 1681 if (sc->sc_100mii == 0) 1682 mcr |= MCR_IBN; 1683 1684 /* Adjust duplexity and PAUSE flow control. */ 1685 mcr &= ~MCR_USEFDX; 1686 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1687 if (miisr & MIISR_FDX) { 1688 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1689 fcr |= FCR_TFE; 1690 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1691 fcr |= FCR_RFE; 1692 mcr |= MCR_USEFDX; 1693 } 1694 mac_write(sc, GMACMCR, mcr); 1695 mac_write(sc, GMACFCR, fcr); 1696 1697 #if 1 1698 if (miisr != oldmiisr) { 1699 printf("%ctxfe, %crxfe\n", 1700 (fcr & FCR_TFE) ? '+' : '-', 1701 (fcr & FCR_RFE) ? '+' : '-'); 1702 } 1703 oldmiisr = miisr; 1704 #endif 1705 } 1706 1707 static void 1708 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1709 { 1710 struct scx_softc *sc = ifp->if_softc; 1711 struct mii_data *mii = &sc->sc_mii; 1712 1713 mii_pollstat(mii); 1714 ifmr->ifm_status = mii->mii_media_status; 1715 ifmr->ifm_active = sc->sc_flowflags | 1716 (mii->mii_media_active & ~IFM_ETH_FMASK); 1717 } 1718 1719 static int 1720 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1721 { 1722 struct scx_softc *sc = device_private(self); 1723 uint32_t miia; 1724 int ntries; 1725 1726 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1727 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1728 for (ntries = 0; ntries < 1000; ntries++) { 1729 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1730 goto unbusy; 1731 DELAY(1); 1732 } 1733 return ETIMEDOUT; 1734 unbusy: 1735 *val = mac_read(sc, GMACGDR); 1736 return 0; 1737 } 1738 1739 static int 1740 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1741 { 1742 struct scx_softc *sc = device_private(self); 1743 uint32_t miia; 1744 uint16_t dummy; 1745 int ntries; 1746 1747 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1748 mac_write(sc, GMACGDR, val); 1749 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1750 for (ntries = 0; ntries < 1000; ntries++) { 1751 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1752 goto unbusy; 1753 DELAY(1); 1754 } 1755 return ETIMEDOUT; 1756 unbusy: 1757 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1758 return 0; 1759 } 1760 1761 static void 1762 phy_tick(void *arg) 1763 { 1764 struct scx_softc *sc = arg; 1765 struct mii_data *mii = &sc->sc_mii; 1766 int s; 1767 1768 s = splnet(); 1769 mii_tick(mii); 1770 splx(s); 1771 #ifdef GMAC_EVENT_COUNTERS 1772 /* 80 event counters exist */ 1773 #endif 1774 callout_schedule(&sc->sc_callout, hz); 1775 } 1776 1777 static void 1778 reset_hardware(struct scx_softc *sc) 1779 { 1780 1781 if (CSR_READ(sc, CORESTAT) != 0) { 1782 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP); 1783 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP); 1784 1785 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP, 0); 1786 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP, 0); 1787 } 1788 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 1789 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */ 1790 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS); 1791 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0); 1792 } 1793 1794 /* 1795 * 3 independent uengines exist to process host2media, media2host and 1796 * packet data flows. 1797 */ 1798 static void 1799 loaducode(struct scx_softc *sc) 1800 { 1801 uint32_t up, lo, sz; 1802 uint64_t addr; 1803 1804 reset_hardware(sc); 1805 CSR_WRITE(sc, xINTSR, IRQ_UCODE); 1806 1807 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1808 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1809 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1810 sz *= 4; 1811 addr = ((uint64_t)up << 32) | lo; 1812 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1813 injectucode(sc, UCODE_H2M, (bus_addr_t)addr, (bus_size_t)sz); 1814 1815 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1816 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1817 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1818 sz *= 4; 1819 addr = ((uint64_t)up << 32) | lo; 1820 injectucode(sc, UCODE_M2H, (bus_addr_t)addr, (bus_size_t)sz); 1821 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1822 1823 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1824 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1825 sz *= 4; 1826 injectucode(sc, UCODE_PKT, (bus_addr_t)lo, (bus_size_t)sz); 1827 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1828 1829 WAIT_FOR_SET(sc, xINTSR, IRQ_UCODE, 0); 1830 /* XXX may take long time to end ?! XXX */ 1831 CSR_WRITE(sc, xINTSR, IRQ_UCODE); 1832 } 1833 1834 static void 1835 injectucode(struct scx_softc *sc, int port, 1836 bus_addr_t addr, bus_size_t size) 1837 { 1838 bus_space_handle_t bsh; 1839 bus_size_t off; 1840 uint32_t ucode; 1841 1842 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1843 aprint_error_dev(sc->sc_dev, 1844 "eeprom map failure for ucode port 0x%x\n", port); 1845 return; 1846 } 1847 for (off = 0; off < size; off += 4) { 1848 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1849 CSR_WRITE(sc, port, ucode); 1850 } 1851 bus_space_unmap(sc->sc_st, bsh, size); 1852 } 1853 1854 /* GAR 5:2 MDIO frequency selection */ 1855 static int 1856 get_mdioclk(uint32_t freq) 1857 { 1858 1859 freq /= 1000 * 1000; 1860 if (freq < 35) 1861 return GAR_MDIO_25_35MHZ; 1862 if (freq < 60) 1863 return GAR_MDIO_35_60MHZ; 1864 if (freq < 100) 1865 return GAR_MDIO_60_100MHZ; 1866 if (freq < 150) 1867 return GAR_MDIO_100_150MHZ; 1868 if (freq < 250) 1869 return GAR_MDIO_150_250MHZ; 1870 return GAR_MDIO_250_300MHZ; 1871 } 1872
Indexes created Mon Sep 29 21:09:56 GMT 2025