if_scx.c revision 1.39
1 /* $NetBSD: if_scx.c,v 1.39 2022/09/27 06:36:43 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 /* 34 * Socionext SC2A11 SynQuacer NetSec GbE driver 35 * 36 * Multiple Tx and Rx queues exist inside and dedicated descriptor 37 * fields specifies which queue is to use. Three internal micro-processors 38 * to handle incoming frames, outgoing frames and packet data crypto 39 * processing. uP programs are stored in an external flash memory and 40 * have to be loaded by device driver. 41 * NetSec uses Synopsys DesignWare Core EMAC. DWC implementation 42 * register (0x20) is known to have 0x10.36 and feature register (0x1058) 43 * reports 0x11056f37. 44 * <24> exdesc 45 * <18> receive IP type 2 checksum offload 46 * <17> (no) receive IP type 1 checksum offload 47 * <16> transmit checksum offload 48 * <11> event counter (mac management counter, MMC) 49 */ 50 51 #define NOT_MP_SAFE 0 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.39 2022/09/27 06:36:43 skrll Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/bus.h> 58 #include <sys/intr.h> 59 #include <sys/device.h> 60 #include <sys/callout.h> 61 #include <sys/mbuf.h> 62 #include <sys/errno.h> 63 #include <sys/rndsource.h> 64 #include <sys/kernel.h> 65 #include <sys/systm.h> 66 67 #include <net/if.h> 68 #include <net/if_media.h> 69 #include <net/if_dl.h> 70 #include <net/if_ether.h> 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 #include <net/bpf.h> 74 75 #include <dev/fdt/fdtvar.h> 76 #include <dev/acpi/acpireg.h> 77 #include <dev/acpi/acpivar.h> 78 #include <dev/acpi/acpi_intr.h> 79 80 /* SC2A11 GbE 64-bit paddr descriptor */ 81 struct tdes { 82 uint32_t t0, t1, t2, t3; 83 }; 84 85 struct rdes { 86 uint32_t r0, r1, r2, r3; 87 }; 88 89 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 90 #define T0_EOD (1U<<30) /* end of descriptor array */ 91 #define T0_DRID (24) /* 29:24 desc ring id */ 92 #define T0_PT (1U<<21) /* 23:21 "pass-through" */ 93 #define T0_TDRID (16) /* 20:16 target desc ring id: GMAC=15 */ 94 #define T0_FS (1U<<9) /* first segment of frame */ 95 #define T0_LS (1U<<8) /* last segment of frame */ 96 #define T0_CSUM (1U<<7) /* enable check sum offload */ 97 #define T0_TSO (1U<<6) /* enable TCP segment offload */ 98 #define T0_TRS (1U<<4) /* 5:4 "TRS" */ 99 /* T1 frame segment address 63:32 */ 100 /* T2 frame segment address 31:0 */ 101 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */ 102 103 #define R0_OWN (1U<<31) /* desc is empty */ 104 #define R0_EOD (1U<<30) /* end of descriptor array */ 105 #define R0_SDRID (24) /* 29:24 source desc ring id */ 106 #define R0_FR (1U<<23) /* found fragmented */ 107 #define R0_ER (1U<<21) /* Rx error indication */ 108 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 109 #define R0_TDRID (12) /* 15:12 target desc ring id */ 110 #define R0_FS (1U<<9) /* first segment of frame */ 111 #define R0_LS (1U<<8) /* last segment of frame */ 112 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 113 #define R0_CERR (2U<<6) /* 0: undone, 1: found ok, 2: bad */ 114 /* R1 frame address 63:32 */ 115 /* R2 frame address 31:0 */ 116 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 117 118 /* 119 * SC2A11 registers. 0x100 - 1204 120 */ 121 #define SWRESET 0x104 122 #define SRST_RUN (1U<<31) /* instruct start, 0 to stop */ 123 #define COMINIT 0x120 124 #define INIT_DB (1U<<2) /* ???; self clear when done */ 125 #define INIT_CLS (1U<<1) /* ???; self clear when done */ 126 #define PKTCTRL 0x140 /* pkt engine control */ 127 #define MODENRM (1U<<28) /* change mode to normal */ 128 #define ENJUMBO (1U<<27) /* allow jumbo frame */ 129 #define RPTCSUMERR (1U<<3) /* log Rx checksum error */ 130 #define RPTHDCOMP (1U<<2) /* log HD incomplete condition */ 131 #define RPTHDERR (1U<<1) /* log HD error */ 132 #define DROPNOMATCH (1U<<0) /* drop no match frames */ 133 #define xINTSR 0x200 /* aggregated interrupt status */ 134 #define IRQ_RX (1U<<1) /* top level Rx interrupt */ 135 #define IRQ_TX (1U<<0) /* top level Rx interrupt */ 136 #define IRQ_UCODE (1U<<20) /* ucode load completed; W1C */ 137 #define xINTAEN 0x204 /* INT_A enable */ 138 #define xINTAE_SET 0x234 /* bit to set */ 139 #define xINTAE_CLR 0x238 /* bit to clr */ 140 #define xINTBEN 0x23c /* INT_B enable */ 141 #define xINTBE_SET 0x240 /* bit to set */ 142 #define xINTBE_CLR 0x244 /* bit to clr */ 143 #define TXISR 0x400 /* transmit status; W1C */ 144 #define TXIEN 0x404 /* tx interrupt enable */ 145 #define TXIE_SET 0x428 /* bit to set */ 146 #define TXIE_CLR 0x42c /* bit to clr */ 147 #define TXI_NTOWNR (1U<<17) /* ??? desc array got empty */ 148 #define TXI_TR_ERR (1U<<16) /* tx error */ 149 #define TXI_TXDONE (1U<<15) /* tx completed */ 150 #define TXI_TMREXP (1U<<14) /* coalesce timer expired */ 151 #define RXISR 0x440 /* receive status; W1C */ 152 #define RXIEN 0x444 /* rx interrupt enable */ 153 #define RXIE_SET 0x468 /* bit to set */ 154 #define RXIE_CLR 0x46c /* bit to clr */ 155 #define RXI_RC_ERR (1U<<16) /* rx error */ 156 #define RXI_PKTCNT (1U<<15) /* rx counter has new value */ 157 #define RXI_TMREXP (1U<<14) /* coalesce timer expired */ 158 /* 13 sets of special purpose desc interrupt handling register exist */ 159 #define TDBA_LO 0x408 /* tdes array base addr 31:0 */ 160 #define TDBA_HI 0x434 /* tdes array base addr 63:32 */ 161 #define RDBA_LO 0x448 /* rdes array base addr 31:0 */ 162 #define RDBA_HI 0x474 /* rdes array base addr 63:32 */ 163 /* 13 pairs of special purpose desc array base address register exist */ 164 #define TXCONF 0x430 165 #define RXCONF 0x470 166 #define DESCNF_UP (1U<<31) /* up-and-running */ 167 #define DESCNF_CHRST (1U<<30) /* channel reset */ 168 #define DESCNF_TMR (1U<<4) /* coalesce timer mode select */ 169 #define DESCNF_LE (1) /* little endian desc format */ 170 #define TXSUBMIT 0x410 /* submit frame(s) to transmit */ 171 #define TXCLSCMAX 0x418 /* tx intr coalesce upper bound */ 172 #define RXCLSCMAX 0x458 /* rx intr coalesce upper bound */ 173 #define TXITIMER 0x420 /* coalesce timer usec, MSB to use */ 174 #define RXITIMER 0x460 /* coalesce timer usec, MSB to use */ 175 #define TXDONECNT 0x414 /* tx completed count, auto-zero */ 176 #define RXDONECNT 0x454 /* rx available count, auto-zero */ 177 #define UCODE_H2M 0x210 /* host2media engine ucode port */ 178 #define UCODE_M2H 0x21c /* media2host engine ucode port */ 179 #define CORESTAT 0x218 /* engine run state */ 180 #define PKTSTOP (1U<<2) 181 #define M2HSTOP (1U<<1) 182 #define H2MSTOP (1U<<0) 183 #define DMACTL_H2M 0x214 /* host2media engine control */ 184 #define DMACTL_M2H 0x220 /* media2host engine control */ 185 #define DMACTL_STOP (1U<<0) /* instruct stop; self-clear */ 186 #define UCODE_PKT 0x0d0 /* packet engine ucode port */ 187 #define CLKEN 0x100 /* clock distribution enable */ 188 #define CLK_G (1U<<5) /* feed clk domain E */ 189 #define CLK_C (1U<<1) /* feed clk domain C */ 190 #define CLK_D (1U<<0) /* feed clk domain D */ 191 #define CLK_ALL 0x23 /* all above; 0x24 ??? 0x3f ??? */ 192 193 /* GMAC register indirect access. thru MACCMD/MACDATA operation */ 194 #define MACDATA 0x11c0 /* gmac register rd/wr data */ 195 #define MACCMD 0x11c4 /* gmac register operation */ 196 #define CMD_IOWR (1U<<28) /* write op */ 197 #define CMD_BUSY (1U<<31) /* busy bit */ 198 #define MACSTAT 0x1024 /* gmac status; ??? */ 199 #define MACINTE 0x1028 /* interrupt enable; ??? */ 200 201 #define FLOWTHR 0x11cc /* flow control threshold */ 202 /* 31:16 pause threshold, 15:0 resume threshold */ 203 #define INTF_SEL 0x11d4 /* ??? */ 204 205 #define DESC_INIT 0x11fc /* write 1 for desc init, SC */ 206 #define DESC_SRST 0x1204 /* write 1 for desc sw reset, SC */ 207 #define MODE_TRANS 0x500 /* mode change completion status */ 208 #define N2T_DONE (1U<<20) /* normal->taiki change completed */ 209 #define T2N_DONE (1U<<19) /* taiki->normal change completed */ 210 #define MACADRH 0x10c /* ??? */ 211 #define MACADRL 0x110 /* ??? */ 212 #define MCVER 0x22c /* micro controller version */ 213 #define HWVER 0x230 /* hardware version */ 214 215 /* 216 * GMAC registers are mostly identical to Synopsys DesignWare Core 217 * Ethernet. These must be handled by indirect access. 218 */ 219 #define GMACMCR 0x0000 /* MAC configuration */ 220 #define MCR_IBN (1U<<30) /* ??? */ 221 #define MCR_CST (1U<<25) /* strip CRC */ 222 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 223 #define MCR_WD (1U<<23) /* allow long >2048 tx frame */ 224 #define MCR_JE (1U<<20) /* allow ~9018 tx jumbo frame */ 225 #define MCR_IFG (7U<<17) /* 19:17 IFG value 0~7 */ 226 #define MCR_DRCS (1U<<16) /* ignore (G)MII HDX Tx error */ 227 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII (_PS) */ 228 #define MCR_SPD100 (1U<<14) /* force speed 100 (_FES) */ 229 #define MCR_DO (1U<<13) /* don't receive my own HDX Tx frames */ 230 #define MCR_LOOP (1U<<12) /* run loop back */ 231 #define MCR_USEFDX (1U<<11) /* force full duplex */ 232 #define MCR_IPCEN (1U<<10) /* handle checksum */ 233 #define MCR_DR (1U<<9) /* attempt no tx retry, send once */ 234 #define MCR_LUD (1U<<8) /* link condition report when RGMII */ 235 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 236 #define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */ 237 #define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */ 238 #define MCR_PREA (3U) /* 1:0 preamble len. 0~2 */ 239 #define _MCR_FDX 0x0000280c /* XXX TBD */ 240 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 241 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 242 #define AFR_RA (1U<<31) /* accept all irrespective of filt. */ 243 #define AFR_HPF (1U<<10) /* hash+perfect filter, or hash only */ 244 #define AFR_SAF (1U<<9) /* source address filter */ 245 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 246 #define AFR_PCF (2U<<6) /* ??? */ 247 #define AFR_DBF (1U<<5) /* reject broadcast frame */ 248 #define AFR_PM (1U<<4) /* accept all multicast frame */ 249 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 250 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 251 #define AFR_UHTE (1U<<1) /* use hash table for unicast */ 252 #define AFR_PR (1U<<0) /* run promisc mode */ 253 #define GMACGAR 0x0010 /* MDIO operation */ 254 #define GAR_PHY (11) /* 15:11 mii phy */ 255 #define GAR_REG (6) /* 10:6 mii reg */ 256 #define GAR_CLK (2) /* 5:2 mdio clock tick ratio */ 257 #define GAR_IOWR (1U<<1) /* MDIO write op */ 258 #define GAR_BUSY (1U<<0) /* busy bit */ 259 #define GAR_MDIO_25_35MHZ 2 260 #define GAR_MDIO_35_60MHZ 3 261 #define GAR_MDIO_60_100MHZ 0 262 #define GAR_MDIO_100_150MHZ 1 263 #define GAR_MDIO_150_250MHZ 4 264 #define GAR_MDIO_250_300MHZ 5 265 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 266 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 267 /* 31:16 pause timer value, 5:4 pause timer threshold */ 268 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 269 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 270 #define GMACIMPL 0x0020 /* implementation id XX.YY (no use) */ 271 #define GMACISR 0x0038 /* interrupt status indication */ 272 #define GMACIMR 0x003c /* interrupt mask to inhibit */ 273 #define ISR_TS (1U<<9) /* time stamp operation detected */ 274 #define ISR_CO (1U<<7) /* Rx checksum offload completed */ 275 #define ISR_TX (1U<<6) /* Tx completed */ 276 #define ISR_RX (1U<<5) /* Rx completed */ 277 #define ISR_ANY (1U<<4) /* any of above 5-7 report */ 278 #define ISR_LC (1U<<0) /* link status change detected */ 279 #define GMACMAH0 0x0040 /* my own MAC address 47:32 */ 280 #define GMACMAL0 0x0044 /* my own MAC address 31:0 */ 281 #define GMACMAH(i) ((i)*8+0x40) /* supplemental MAC addr 1-15 */ 282 #define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */ 283 /* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */ 284 #define GMACAMAH(i) ((i)*8+0x800) /* supplemental MAC addr 16-31 */ 285 #define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */ 286 /* supplimental MAH bit-31: slot in use, no other bit is effective */ 287 #define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */ 288 #define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */ 289 #define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */ 290 #define EMACVTAG 0x001c /* VLAN tag control */ 291 #define VTAG_HASH (1U<<19) /* use VLAN tag hash table */ 292 #define VTAG_SVLAN (1U<<18) /* handle type 0x88A8 SVLAN frame */ 293 #define VTAG_INV (1U<<17) /* run inverse match logic */ 294 #define VTAG_ETV (1U<<16) /* use only 12bit VID field to match */ 295 /* 15:0 concat of PRIO+CFI+VID */ 296 #define GMACVHT 0x0588 /* 16-bit VLAN tag hash */ 297 #define GMACMIISR 0x00d8 /* resolved xMII link status */ 298 #define MIISR_LUP (1U<<3) /* link up(1)/down(0) report */ 299 #define MIISR_SPD (3U<<1) /* 2:1 speed 10(0)/100(1)/1000(2) */ 300 #define MIISR_FDX (1U<<0) /* fdx detected */ 301 302 #define GMACLPIS 0x0030 /* LPI control & status */ 303 #define LPIS_TXA (1U<<19) /* complete Tx in progress and LPI */ 304 #define LPIS_PLS (1U<<17) 305 #define LPIS_EN (1U<<16) /* 1: enter LPI mode, 0: exit */ 306 #define LPIS_TEN (1U<<0) /* Tx LPI report */ 307 #define GMACLPIC 0x0034 /* LPI timer control */ 308 #define LPIC_LST (5) /* 16:5 ??? */ 309 #define LPIC_TWT (0) /* 15:0 ??? */ 310 #define GMACTSC 0x0700 /* timestamp control */ 311 #define GMACSTM 0x071c /* start time */ 312 #define GMACTGT 0x0720 /* target time */ 313 #define GMACTSS 0x0728 /* timestamp status */ 314 #define GMACPPS 0x072c /* PPS control */ 315 #define GMACPPS0 0x0764 /* PPS0 width */ 316 317 #define GMACBMR 0x1000 /* DMA bus mode control */ 318 /* 24 multiply by x8 for RPBL & PBL values 319 * 23 use RPBL for Rx DMA 320 * 22:17 RPBL 321 * 16 fixed burst 322 * 15:14 priority between Rx and Tx 323 * 3 rxtx ratio 41 324 * 2 rxtx ratio 31 325 * 1 rxtx ratio 21 326 * 0 rxtx ratio 11 327 * 13:8 PBL possible DMA burst length 328 * 7 select alternative 32-byte descriptor format for new features 329 * 6:2 descriptor spacing. 0 for adjuscent 330 * 0 GMAC reset op. self-clear 331 */ 332 #define _BMR 0x00412080 /* XXX TBD */ 333 #define _BMR0 0x00020181 /* XXX TBD */ 334 #define BMR_RST (1) /* reset op. self clear when done */ 335 #define GMACTPD 0x1004 /* write any to resume tdes */ 336 #define GMACRPD 0x1008 /* write any to resume rdes */ 337 #define GMACRDLA 0x100c /* rdes base address 32bit paddr */ 338 #define GMACTDLA 0x1010 /* tdes base address 32bit paddr */ 339 #define _RDLA 0x18000 /* system RAM for GMAC rdes */ 340 #define _TDLA 0x1c000 /* system RAM for GMAC tdes */ 341 #define GMACDSR 0x1014 /* DMA status detail report; W1C */ 342 #define GMACDIE 0x101c /* DMA interrupt enable */ 343 #define DMAI_LPI (1U<<30) /* LPI interrupt */ 344 #define DMAI_TTI (1U<<29) /* timestamp trigger interrupt */ 345 #define DMAI_GMI (1U<<27) /* management counter interrupt */ 346 #define DMAI_GLI (1U<<26) /* xMII link change detected */ 347 #define DMAI_EB (23) /* 25:23 DMA bus error detected */ 348 #define DMAI_TS (20) /* 22:20 Tx DMA state report */ 349 #define DMAI_RS (17) /* 29:17 Rx DMA state report */ 350 #define DMAI_NIS (1U<<16) /* normal interrupt summary; W1C */ 351 #define DMAI_AIS (1U<<15) /* abnormal interrupt summary; W1C */ 352 #define DMAI_ERI (1U<<14) /* the first Rx buffer is filled */ 353 #define DMAI_FBI (1U<<13) /* DMA bus error detected */ 354 #define DMAI_ETI (1U<<10) /* single frame Tx completed */ 355 #define DMAI_RWT (1U<<9) /* longer than 2048 frame received */ 356 #define DMAI_RPS (1U<<8) /* Rx process is now stopped */ 357 #define DMAI_RU (1U<<7) /* Rx descriptor not available */ 358 #define DMAI_RI (1U<<6) /* frame Rx completed by !R1_DIC */ 359 #define DMAI_UNF (1U<<5) /* Tx underflow detected */ 360 #define DMAI_OVF (1U<<4) /* receive buffer overflow detected */ 361 #define DMAI_TJT (1U<<3) /* longer than 2048 frame sent */ 362 #define DMAI_TU (1U<<2) /* Tx descriptor not available */ 363 #define DMAI_TPS (1U<<1) /* transmission is stopped */ 364 #define DMAI_TI (1U<<0) /* frame Tx completed by T0_IC */ 365 #define GMACOMR 0x1018 /* DMA operation mode */ 366 #define OMR_RSF (1U<<25) /* 1: Rx store&forward, 0: immed. */ 367 #define OMR_TSF (1U<<21) /* 1: Tx store&forward, 0: immed. */ 368 #define OMR_TTC (14) /* 16:14 Tx threshold */ 369 #define OMR_ST (1U<<13) /* run Tx DMA engine, 0 to stop */ 370 #define OMR_RFD (11) /* 12:11 Rx FIFO fill level */ 371 #define OMR_EFC (1U<<8) /* transmit PAUSE to throttle Rx lvl. */ 372 #define OMR_FEF (1U<<7) /* allow to receive error frames */ 373 #define OMR_SR (1U<<1) /* run Rx DMA engine, 0 to stop */ 374 #define GMACEVCS 0x1020 /* missed frame or ovf detected */ 375 #define GMACRWDT 0x1024 /* enable rx watchdog timer interrupt */ 376 #define GMACAXIB 0x1028 /* AXI bus mode control */ 377 #define GMACAXIS 0x102c /* AXI status report */ 378 /* 0x1048 current tx desc address */ 379 /* 0x104c current rx desc address */ 380 /* 0x1050 current tx buffer address */ 381 /* 0x1054 current rx buffer address */ 382 #define HWFEA 0x1058 /* DWC feature report */ 383 #define FEA_EXDESC (1U<<24) /* new desc layout */ 384 #define FEA_2COE (1U<<18) /* Rx type 2 IP checksum offload */ 385 #define FEA_1COE (1U<<17) /* Rx type 1 IP checksum offload */ 386 #define FEA_TXOE (1U<<16) /* Tx checksum offload */ 387 #define FEA_MMC (1U<<11) /* RMON event counter */ 388 389 #define GMACEVCTL 0x0100 /* event counter control */ 390 #define EVC_FHP (1U<<5) /* full-half preset */ 391 #define EVC_CP (1U<<4) /* counter preset */ 392 #define EVC_MCF (1U<<3) /* counter freeze */ 393 #define EVC_ROR (1U<<2) /* auto-zero on counter read */ 394 #define EVC_CSR (1U<<1) /* counter stop rollover */ 395 #define EVC_CR (1U<<0) /* reset counters */ 396 #define GMACEVCNT(i) ((i)*4+0x114) /* 80 event counters 0x114 - 0x284 */ 397 398 /* 399 * flash memory layout 400 * 0x00 - 07 48-bit MAC station address. 4 byte wise in BE order. 401 * 0x08 - 0b H->MAC xfer engine program start addr 63:32. 402 * 0x0c - 0f H2M program addr 31:0 (these are absolute addr, not offset) 403 * 0x10 - 13 H2M program length in 4 byte count. 404 * 0x14 - 0b M->HOST xfer engine program start addr 63:32. 405 * 0x18 - 0f M2H program addr 31:0 (absolute addr, not relative) 406 * 0x1c - 13 M2H program length in 4 byte count. 407 * 0x20 - 23 packet engine program addr 31:0, (absolute addr, not offset) 408 * 0x24 - 27 packet program length in 4 byte count. 409 * 410 * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0. 411 */ 412 413 /* 414 * all below are software constraction. 415 */ 416 #define MD_NTXSEGS 16 /* fixed */ 417 #define MD_TXQUEUELEN 8 /* tunable */ 418 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 419 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 420 #define MD_NTXDESC 128 421 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 422 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 423 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 424 425 #define MD_NRXDESC 64 /* tunable */ 426 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 427 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 428 429 struct control_data { 430 struct tdes cd_txdescs[MD_NTXDESC]; 431 struct rdes cd_rxdescs[MD_NRXDESC]; 432 }; 433 #define SCX_CDOFF(x) offsetof(struct control_data, x) 434 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 435 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 436 437 struct scx_txsoft { 438 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 439 bus_dmamap_t txs_dmamap; /* our DMA map */ 440 int txs_firstdesc; /* first descriptor in packet */ 441 int txs_lastdesc; /* last descriptor in packet */ 442 int txs_ndesc; /* # of descriptors used */ 443 }; 444 445 struct scx_rxsoft { 446 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 447 bus_dmamap_t rxs_dmamap; /* our DMA map */ 448 }; 449 450 struct scx_softc { 451 device_t sc_dev; /* generic device information */ 452 bus_space_tag_t sc_st; /* bus space tag */ 453 bus_space_handle_t sc_sh; /* bus space handle */ 454 bus_size_t sc_sz; /* csr map size */ 455 bus_space_handle_t sc_eesh; /* eeprom section handle */ 456 bus_size_t sc_eesz; /* eeprom map size */ 457 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 458 struct ethercom sc_ethercom; /* Ethernet common data */ 459 struct mii_data sc_mii; /* MII */ 460 callout_t sc_callout; /* PHY monitor callout */ 461 bus_dma_segment_t sc_seg; /* descriptor store seg */ 462 int sc_nseg; /* descriptor store nseg */ 463 void *sc_ih; /* interrupt cookie */ 464 int sc_phy_id; /* PHY address */ 465 int sc_flowflags; /* 802.3x PAUSE flow control */ 466 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 467 uint32_t sc_t0cotso; /* T0_CSUM | T0_TSO to run */ 468 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 469 int sc_phandle; /* fdt phandle */ 470 uint64_t sc_freq; 471 472 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 473 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 474 475 struct control_data *sc_control_data; 476 #define sc_txdescs sc_control_data->cd_txdescs 477 #define sc_rxdescs sc_control_data->cd_rxdescs 478 479 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 480 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 481 int sc_txfree; /* number of free Tx descriptors */ 482 int sc_txnext; /* next ready Tx descriptor */ 483 int sc_txsfree; /* number of free Tx jobs */ 484 int sc_txsnext; /* next ready Tx job */ 485 int sc_txsdirty; /* dirty Tx jobs */ 486 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 487 488 krndsource_t rnd_source; /* random source */ 489 #ifdef GMAC_EVENT_COUNTERS 490 /* 80 event counters exist */ 491 #endif 492 }; 493 494 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 495 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 496 497 #define SCX_CDTXSYNC(sc, x, n, ops) \ 498 do { \ 499 int __x, __n; \ 500 \ 501 __x = (x); \ 502 __n = (n); \ 503 \ 504 /* If it will wrap around, sync to the end of the ring. */ \ 505 if ((__x + __n) > MD_NTXDESC) { \ 506 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 507 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 508 (MD_NTXDESC - __x), (ops)); \ 509 __n -= (MD_NTXDESC - __x); \ 510 __x = 0; \ 511 } \ 512 \ 513 /* Now sync whatever is left. */ \ 514 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 515 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 516 } while (/*CONSTCOND*/0) 517 518 #define SCX_CDRXSYNC(sc, x, ops) \ 519 do { \ 520 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 521 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 522 } while (/*CONSTCOND*/0) 523 524 #define SCX_INIT_RXDESC(sc, x) \ 525 do { \ 526 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 527 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 528 struct mbuf *__m = __rxs->rxs_mbuf; \ 529 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 530 __m->m_data = __m->m_ext.ext_buf; \ 531 __rxd->r3 = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_len); \ 532 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 533 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 534 __rxd->r0 = htole32(R0_OWN | R0_FS | R0_LS); \ 535 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= htole32(R0_EOD); \ 536 } while (/*CONSTCOND*/0) 537 538 /* memory mapped CSR register access */ 539 #define CSR_READ(sc,off) \ 540 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 541 #define CSR_WRITE(sc,off,val) \ 542 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 543 544 /* flash memory access */ 545 #define EE_READ(sc,off) \ 546 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 547 548 static int scx_fdt_match(device_t, cfdata_t, void *); 549 static void scx_fdt_attach(device_t, device_t, void *); 550 static int scx_acpi_match(device_t, cfdata_t, void *); 551 static void scx_acpi_attach(device_t, device_t, void *); 552 553 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 554 scx_fdt_match, scx_fdt_attach, NULL, NULL); 555 556 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 557 scx_acpi_match, scx_acpi_attach, NULL, NULL); 558 559 static void scx_attach_i(struct scx_softc *); 560 static void scx_reset(struct scx_softc *); 561 static int scx_init(struct ifnet *); 562 static void scx_stop(struct ifnet *, int); 563 static int scx_ioctl(struct ifnet *, u_long, void *); 564 static void scx_set_rcvfilt(struct scx_softc *); 565 static void scx_start(struct ifnet *); 566 static void scx_watchdog(struct ifnet *); 567 static int scx_intr(void *); 568 static void txreap(struct scx_softc *); 569 static void rxintr(struct scx_softc *); 570 static int add_rxbuf(struct scx_softc *, int); 571 static void rxdrain(struct scx_softc *sc); 572 static void mii_statchg(struct ifnet *); 573 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 574 static int mii_readreg(device_t, int, int, uint16_t *); 575 static int mii_writereg(device_t, int, int, uint16_t); 576 static void phy_tick(void *); 577 578 static void loaducode(struct scx_softc *); 579 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 580 581 static int get_mdioclk(uint32_t); 582 583 #define WAIT_FOR_SET(sc, reg, set, fail) \ 584 wait_for_bits(sc, reg, set, ~0, fail) 585 #define WAIT_FOR_CLR(sc, reg, clr, fail) \ 586 wait_for_bits(sc, reg, 0, clr, fail) 587 588 static int 589 wait_for_bits(struct scx_softc *sc, int reg, 590 uint32_t set, uint32_t clr, uint32_t fail) 591 { 592 uint32_t val; 593 int ntries; 594 595 for (ntries = 0; ntries < 1000; ntries++) { 596 val = CSR_READ(sc, reg); 597 if ((val & set) || !(val & clr)) 598 return 0; 599 if (val & fail) 600 return 1; 601 DELAY(1); 602 } 603 return 1; 604 } 605 606 /* GMAC register indirect access */ 607 static int 608 mac_read(struct scx_softc *sc, int reg) 609 { 610 611 CSR_WRITE(sc, MACCMD, reg | CMD_BUSY); 612 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 613 return CSR_READ(sc, MACDATA); 614 } 615 616 static void 617 mac_write(struct scx_softc *sc, int reg, int val) 618 { 619 620 CSR_WRITE(sc, MACDATA, val); 621 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY); 622 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0); 623 } 624 625 /* dig and decode "clock-frequency" value for a given clkname */ 626 static int 627 get_clk_freq(int phandle, const char *clkname) 628 { 629 u_int index, n, cells; 630 const u_int *p; 631 int err, len, resid; 632 unsigned int freq = 0; 633 634 err = fdtbus_get_index(phandle, "clock-names", clkname, &index); 635 if (err == -1) 636 return -1; 637 p = fdtbus_get_prop(phandle, "clocks", &len); 638 if (p == NULL) 639 return -1; 640 for (n = 0, resid = len; resid > 0; n++) { 641 const int cc_phandle = 642 fdtbus_get_phandle_from_native(be32toh(p[0])); 643 if (of_getprop_uint32(cc_phandle, "#clock-cells", &cells)) 644 return -1; 645 if (n == index) { 646 if (of_getprop_uint32(cc_phandle, 647 "clock-frequency", &freq)) 648 return -1; 649 return freq; 650 } 651 resid -= (cells + 1) * 4; 652 p += (cells + 1) * 4; 653 } 654 return -1; 655 } 656 657 static const struct device_compatible_entry compat_data[] = { 658 { .compat = "socionext,synquacer-netsec" }, 659 DEVICE_COMPAT_EOL 660 }; 661 static const struct device_compatible_entry compatible[] = { 662 { .compat = "SCX0001" }, 663 DEVICE_COMPAT_EOL 664 }; 665 666 static int 667 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 668 { 669 struct fdt_attach_args * const faa = aux; 670 671 return of_compatible_match(faa->faa_phandle, compat_data); 672 } 673 674 static void 675 scx_fdt_attach(device_t parent, device_t self, void *aux) 676 { 677 struct scx_softc * const sc = device_private(self); 678 struct fdt_attach_args * const faa = aux; 679 const int phandle = faa->faa_phandle; 680 bus_space_handle_t bsh; 681 bus_space_handle_t eebsh; 682 bus_addr_t addr[2]; 683 bus_size_t size[2]; 684 char intrstr[128]; 685 int phy_phandle; 686 bus_addr_t phy_id; 687 const char *phy_type; 688 long ref_clk; 689 690 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 691 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 692 aprint_error_dev(self, "unable to map device csr\n"); 693 return; 694 } 695 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 696 aprint_error_dev(self, "failed to decode interrupt\n"); 697 goto fail; 698 } 699 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 700 NOT_MP_SAFE, scx_intr, sc); 701 if (sc->sc_ih == NULL) { 702 aprint_error_dev(self, "couldn't establish interrupt\n"); 703 goto fail; 704 } 705 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 706 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 707 aprint_error_dev(self, "unable to map device eeprom\n"); 708 goto fail; 709 } 710 711 sc->sc_dev = self; 712 sc->sc_st = faa->faa_bst; 713 sc->sc_sh = bsh; 714 sc->sc_sz = size[0]; 715 sc->sc_eesh = eebsh; 716 sc->sc_eesz = size[1]; 717 sc->sc_dmat = faa->faa_dmat; 718 sc->sc_phandle = phandle; 719 720 phy_type = fdtbus_get_string(phandle, "phy-mode"); 721 if (phy_type == NULL) 722 aprint_error_dev(self, "missing 'phy-mode' property\n"); 723 phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 724 if (phy_phandle == -1 725 || fdtbus_get_reg(phy_phandle, 0, &phy_id, NULL) != 0) 726 phy_id = MII_PHY_ANY; 727 ref_clk = get_clk_freq(phandle, "phy_ref_clk"); 728 if (ref_clk == -1) 729 ref_clk = 250 * 1000 * 1000; 730 731 sc->sc_100mii = (phy_type && strncmp(phy_type, "rgmii", 5) != 0); 732 sc->sc_phy_id = phy_id; 733 sc->sc_freq = ref_clk; 734 735 aprint_normal("%s", device_xname(self)); 736 scx_attach_i(sc); 737 return; 738 fail: 739 if (sc->sc_eesz) 740 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 741 if (sc->sc_sz) 742 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 743 return; 744 } 745 746 static int 747 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 748 { 749 struct acpi_attach_args *aa = aux; 750 751 return acpi_compatible_match(aa, compatible); 752 } 753 754 static void 755 scx_acpi_attach(device_t parent, device_t self, void *aux) 756 { 757 struct scx_softc * const sc = device_private(self); 758 struct acpi_attach_args * const aa = aux; 759 ACPI_HANDLE handle = aa->aa_node->ad_handle; 760 bus_space_handle_t bsh, eebsh; 761 struct acpi_resources res; 762 struct acpi_mem *mem; 763 struct acpi_irq *irq; 764 ACPI_INTEGER phy_type, phy_id, ref_freq; 765 ACPI_STATUS rv; 766 767 rv = acpi_resource_parse(self, handle, "_CRS", 768 &res, &acpi_resource_parse_ops_default); 769 if (ACPI_FAILURE(rv)) 770 return; 771 772 mem = acpi_res_mem(&res, 0); 773 irq = acpi_res_irq(&res, 0); 774 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 775 aprint_error_dev(self, "incomplete crs resources\n"); 776 return; 777 } 778 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0, 779 &bsh) != 0) { 780 aprint_error_dev(self, "couldn't map registers\n"); 781 return; 782 } 783 sc->sc_sz = mem->ar_length; 784 sc->sc_ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)handle, 785 IPL_NET, NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 786 if (sc->sc_ih == NULL) { 787 aprint_error_dev(self, "couldn't establish interrupt\n"); 788 goto fail; 789 } 790 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 791 if (mem == NULL || mem->ar_length == 0) { 792 aprint_error_dev(self, "incomplete eeprom resources\n"); 793 goto fail; 794 } 795 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0, 796 &eebsh)) { 797 aprint_error_dev(self, "couldn't map registers\n"); 798 goto fail; 799 } 800 sc->sc_eesz = mem->ar_length; 801 802 rv = acpi_dsd_integer(handle, "max-speed", &phy_type); 803 if (ACPI_FAILURE(rv)) { 804 aprint_error_dev(self, "missing 'max-speed' property\n"); 805 phy_type = 1000; 806 } 807 rv = acpi_dsd_integer(handle, "phy-channel", &phy_id); 808 if (ACPI_FAILURE(rv)) 809 phy_id = MII_PHY_ANY; 810 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 811 &ref_freq); 812 if (ACPI_FAILURE(rv)) 813 ref_freq = 250 * 1000 * 1000; 814 815 sc->sc_dev = self; 816 sc->sc_st = aa->aa_memt; 817 sc->sc_sh = bsh; 818 sc->sc_eesh = eebsh; 819 sc->sc_dmat = aa->aa_dmat64; 820 sc->sc_100mii = (phy_type != 1000); 821 sc->sc_phy_id = (int)phy_id; 822 sc->sc_freq = ref_freq; 823 824 aprint_normal_dev(self, 825 "phy type %d, phy id %d, freq %ld\n", (int)phy_type, (int)phy_id, ref_freq); 826 827 aprint_normal("%s", device_xname(self)); 828 scx_attach_i(sc); 829 830 acpi_resource_cleanup(&res); 831 return; 832 fail: 833 if (sc->sc_eesz > 0) 834 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 835 if (sc->sc_sz > 0) 836 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 837 acpi_resource_cleanup(&res); 838 return; 839 } 840 841 static void 842 scx_attach_i(struct scx_softc *sc) 843 { 844 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 845 struct mii_data * const mii = &sc->sc_mii; 846 struct ifmedia * const ifm = &mii->mii_media; 847 uint32_t which, dwfea, dwimp; 848 uint8_t enaddr[ETHER_ADDR_LEN]; 849 bus_dma_segment_t seg; 850 uint32_t csr; 851 int i, nseg, error = 0; 852 853 aprint_naive("\n"); 854 aprint_normal(": Socionext Gigabit Ethernet controller\n"); 855 856 which = CSR_READ(sc, HWVER); /* Socionext version 5.00xx */ 857 dwfea = mac_read(sc, HWFEA); /* DWC feature bits */ 858 dwimp = mac_read(sc, GMACIMPL); /* DWC implementation XX.YY */ 859 aprint_normal_dev(sc->sc_dev, 860 "NetSec %x.%x (feature 0x%x imp 0x%0x)\n", 861 which >> 16, which & 0xffff, dwfea, dwimp); 862 863 /* fetch MAC address in flash 0:7, stored in big endian order */ 864 csr = EE_READ(sc, 0x00); 865 enaddr[0] = csr >> 24; 866 enaddr[1] = csr >> 16; 867 enaddr[2] = csr >> 8; 868 enaddr[3] = csr; 869 csr = EE_READ(sc, 0x04); 870 enaddr[4] = csr >> 24; 871 enaddr[5] = csr >> 16; 872 aprint_normal_dev(sc->sc_dev, 873 "Ethernet address %s\n", ether_sprintf(enaddr)); 874 875 sc->sc_mdclk = get_mdioclk(sc->sc_freq) << GAR_CLK; /* 5:2 clk ratio */ 876 877 loaducode(sc); 878 879 mii->mii_ifp = ifp; 880 mii->mii_readreg = mii_readreg; 881 mii->mii_writereg = mii_writereg; 882 mii->mii_statchg = mii_statchg; 883 884 sc->sc_ethercom.ec_mii = mii; 885 ifmedia_init(ifm, 0, ether_mediachange, scx_ifmedia_sts); 886 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 887 MII_OFFSET_ANY, MIIF_DOPAUSE); 888 if (LIST_FIRST(&mii->mii_phys) == NULL) { 889 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 890 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 891 } else 892 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 893 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 894 895 /* 896 * Allocate the control data structures, and create and load the 897 * DMA map for it. 898 */ 899 error = bus_dmamem_alloc(sc->sc_dmat, 900 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 901 if (error != 0) { 902 aprint_error_dev(sc->sc_dev, 903 "unable to allocate control data, error = %d\n", error); 904 goto fail_0; 905 } 906 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 907 sizeof(struct control_data), (void **)&sc->sc_control_data, 908 BUS_DMA_COHERENT); 909 if (error != 0) { 910 aprint_error_dev(sc->sc_dev, 911 "unable to map control data, error = %d\n", error); 912 goto fail_1; 913 } 914 error = bus_dmamap_create(sc->sc_dmat, 915 sizeof(struct control_data), 1, 916 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 917 if (error != 0) { 918 aprint_error_dev(sc->sc_dev, 919 "unable to create control data DMA map, " 920 "error = %d\n", error); 921 goto fail_2; 922 } 923 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 924 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 925 if (error != 0) { 926 aprint_error_dev(sc->sc_dev, 927 "unable to load control data DMA map, error = %d\n", 928 error); 929 goto fail_3; 930 } 931 for (i = 0; i < MD_TXQUEUELEN; i++) { 932 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 933 MD_NTXSEGS, MCLBYTES, 0, 0, 934 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 935 aprint_error_dev(sc->sc_dev, 936 "unable to create tx DMA map %d, error = %d\n", 937 i, error); 938 goto fail_4; 939 } 940 } 941 for (i = 0; i < MD_NRXDESC; i++) { 942 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 943 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 944 aprint_error_dev(sc->sc_dev, 945 "unable to create rx DMA map %d, error = %d\n", 946 i, error); 947 goto fail_5; 948 } 949 sc->sc_rxsoft[i].rxs_mbuf = NULL; 950 } 951 sc->sc_seg = seg; 952 sc->sc_nseg = nseg; 953 #if 0 954 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 955 #endif 956 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 957 ifp->if_softc = sc; 958 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 959 ifp->if_ioctl = scx_ioctl; 960 ifp->if_start = scx_start; 961 ifp->if_watchdog = scx_watchdog; 962 ifp->if_init = scx_init; 963 ifp->if_stop = scx_stop; 964 IFQ_SET_READY(&ifp->if_snd); 965 966 sc->sc_flowflags = 0; 967 968 if_attach(ifp); 969 if_deferred_start_init(ifp, NULL); 970 ether_ifattach(ifp, enaddr); 971 972 callout_init(&sc->sc_callout, 0); 973 callout_setfunc(&sc->sc_callout, phy_tick, sc); 974 975 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 976 RND_TYPE_NET, RND_FLAG_DEFAULT); 977 978 return; 979 980 fail_5: 981 for (i = 0; i < MD_NRXDESC; i++) { 982 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 983 bus_dmamap_destroy(sc->sc_dmat, 984 sc->sc_rxsoft[i].rxs_dmamap); 985 } 986 fail_4: 987 for (i = 0; i < MD_TXQUEUELEN; i++) { 988 if (sc->sc_txsoft[i].txs_dmamap != NULL) 989 bus_dmamap_destroy(sc->sc_dmat, 990 sc->sc_txsoft[i].txs_dmamap); 991 } 992 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 993 fail_3: 994 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 995 fail_2: 996 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 997 sizeof(struct control_data)); 998 fail_1: 999 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 1000 fail_0: 1001 if (sc->sc_phandle) 1002 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 1003 else 1004 acpi_intr_disestablish(sc->sc_ih); 1005 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 1006 return; 1007 } 1008 1009 static void 1010 scx_reset(struct scx_softc *sc) 1011 { 1012 int loop = 0, busy; 1013 1014 mac_write(sc, GMACOMR, 0); 1015 mac_write(sc, GMACBMR, BMR_RST); 1016 do { 1017 DELAY(1); 1018 busy = mac_read(sc, GMACBMR) & BMR_RST; 1019 } while (++loop < 3000 && busy); 1020 mac_write(sc, GMACBMR, _BMR); 1021 mac_write(sc, GMACAFR, 0); 1022 1023 CSR_WRITE(sc, CLKEN, CLK_ALL); /* distribute clock sources */ 1024 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 1025 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */ 1026 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS); 1027 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0); 1028 1029 CSR_WRITE(sc, TXISR, ~0); 1030 CSR_WRITE(sc, xINTAE_CLR, ~0); 1031 1032 /* clear event counters, auto-zero after every read */ 1033 mac_write(sc, GMACEVCTL, EVC_CR | EVC_ROR); 1034 } 1035 1036 static int 1037 scx_init(struct ifnet *ifp) 1038 { 1039 struct scx_softc *sc = ifp->if_softc; 1040 const uint8_t *ea = CLLADDR(ifp->if_sadl); 1041 paddr_t paddr; 1042 uint32_t csr; 1043 int i, error; 1044 1045 /* Cancel pending I/O. */ 1046 scx_stop(ifp, 0); 1047 1048 /* Reset the chip to a known state. */ 1049 scx_reset(sc); 1050 1051 /* build sane Tx */ 1052 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 1053 sc->sc_txdescs[MD_NTXDESC - 1].t0 = T0_EOD; /* tie off the ring */ 1054 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 1055 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1056 sc->sc_txfree = MD_NTXDESC; 1057 sc->sc_txnext = 0; 1058 for (i = 0; i < MD_TXQUEUELEN; i++) 1059 sc->sc_txsoft[i].txs_mbuf = NULL; 1060 sc->sc_txsfree = MD_TXQUEUELEN; 1061 sc->sc_txsnext = 0; 1062 sc->sc_txsdirty = 0; 1063 1064 /* load Rx descriptors with fresh mbuf */ 1065 for (i = 0; i < MD_NRXDESC; i++) { 1066 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 1067 if ((error = add_rxbuf(sc, i)) != 0) { 1068 aprint_error_dev(sc->sc_dev, 1069 "unable to allocate or map rx " 1070 "buffer %d, error = %d\n", 1071 i, error); 1072 rxdrain(sc); 1073 goto out; 1074 } 1075 } 1076 else 1077 SCX_INIT_RXDESC(sc, i); 1078 } 1079 sc->sc_rxdescs[MD_NRXDESC - 1].r0 = R0_EOD; /* tie off the ring */ 1080 sc->sc_rxptr = 0; 1081 1082 paddr = SCX_CDTXADDR(sc, 0); /* tdes array (ring#0) */ 1083 mac_write(sc, TDBA_HI, BUS_ADDR_HI32(paddr)); 1084 mac_write(sc, TDBA_LO, BUS_ADDR_LO32(paddr)); 1085 paddr = SCX_CDRXADDR(sc, 0); /* rdes array (ring#1) */ 1086 mac_write(sc, RDBA_HI, BUS_ADDR_HI32(paddr)); 1087 mac_write(sc, RDBA_LO, BUS_ADDR_LO32(paddr)); 1088 1089 CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */ 1090 CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian */ 1091 1092 /* set my address in perfect match slot 0. little endian order */ 1093 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 1094 mac_write(sc, GMACMAL0, csr); 1095 csr = (ea[5] << 8) | ea[4]; 1096 mac_write(sc, GMACMAH0, csr); 1097 1098 /* accept multicast frame or run promisc mode */ 1099 scx_set_rcvfilt(sc); 1100 1101 /* set current media */ 1102 if ((error = ether_mediachange(ifp)) != 0) 1103 goto out; 1104 1105 CSR_WRITE(sc, DESC_SRST, 01); 1106 WAIT_FOR_CLR(sc, DESC_SRST, 01, 0); 1107 1108 CSR_WRITE(sc, DESC_INIT, 01); 1109 WAIT_FOR_CLR(sc, DESC_INIT, 01, 0); 1110 1111 mac_write(sc, GMACRDLA, _RDLA); /* GMAC rdes store */ 1112 mac_write(sc, GMACTDLA, _TDLA); /* GMAC tdes store */ 1113 1114 CSR_WRITE(sc, FLOWTHR, (48<<16) | 36); /* pause|resume threshold */ 1115 mac_write(sc, GMACFCR, 256 << 16); /* 31:16 pause value */ 1116 1117 CSR_WRITE(sc, RXIE_CLR, ~0); /* clear Rx interrupt enable */ 1118 CSR_WRITE(sc, TXIE_CLR, ~0); /* clear Tx interrupt enable */ 1119 1120 CSR_WRITE(sc, RXCLSCMAX, 8); /* Rx coalesce upper bound */ 1121 CSR_WRITE(sc, TXCLSCMAX, 8); /* Tx coalesce upper bound */ 1122 CSR_WRITE(sc, RXITIMER, 500); /* Rx co. timer usec */ 1123 CSR_WRITE(sc, TXITIMER, 500); /* Tx co. timer usec */ 1124 1125 CSR_WRITE(sc, RXIE_SET, RXI_RC_ERR | RXI_PKTCNT | RXI_TMREXP); 1126 CSR_WRITE(sc, TXIE_SET, TXI_TR_ERR | TXI_TXDONE | TXI_TMREXP); 1127 1128 CSR_WRITE(sc, xINTAE_SET, IRQ_RX | IRQ_TX); 1129 1130 /* kick to start GMAC engine */ 1131 csr = mac_read(sc, GMACOMR); 1132 mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST); 1133 1134 ifp->if_flags |= IFF_RUNNING; 1135 1136 /* start one second timer */ 1137 callout_schedule(&sc->sc_callout, hz); 1138 out: 1139 return error; 1140 } 1141 1142 static void 1143 scx_stop(struct ifnet *ifp, int disable) 1144 { 1145 struct scx_softc *sc = ifp->if_softc; 1146 1147 /* Stop the one second clock. */ 1148 callout_stop(&sc->sc_callout); 1149 1150 /* Down the MII. */ 1151 mii_down(&sc->sc_mii); 1152 1153 /* Mark the interface down and cancel the watchdog timer. */ 1154 ifp->if_flags &= ~IFF_RUNNING; 1155 ifp->if_timer = 0; 1156 1157 CSR_WRITE(sc, xINTAE_CLR, ~0); 1158 CSR_WRITE(sc, TXISR, ~0); 1159 CSR_WRITE(sc, RXISR, ~0); 1160 1161 if (CSR_READ(sc, CORESTAT) != 0) { 1162 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP); 1163 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP); 1164 1165 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP, 0); 1166 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP, 0); 1167 } 1168 } 1169 1170 static int 1171 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1172 { 1173 struct scx_softc *sc = ifp->if_softc; 1174 struct ifreq *ifr = (struct ifreq *)data; 1175 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1176 int s, error; 1177 1178 s = splnet(); 1179 1180 switch (cmd) { 1181 case SIOCSIFMEDIA: 1182 /* Flow control requires full-duplex mode. */ 1183 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1184 (ifr->ifr_media & IFM_FDX) == 0) 1185 ifr->ifr_media &= ~IFM_ETH_FMASK; 1186 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1187 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1188 /* We can do both TXPAUSE and RXPAUSE. */ 1189 ifr->ifr_media |= 1190 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1191 } 1192 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1193 } 1194 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 1195 break; 1196 default: 1197 error = ether_ioctl(ifp, cmd, data); 1198 if (error != ENETRESET) 1199 break; 1200 error = 0; 1201 if (cmd == SIOCSIFCAP) 1202 error = if_init(ifp); 1203 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1204 ; 1205 else if (ifp->if_flags & IFF_RUNNING) { 1206 /* 1207 * Multicast list has changed; set the hardware filter 1208 * accordingly. 1209 */ 1210 scx_set_rcvfilt(sc); 1211 } 1212 break; 1213 } 1214 1215 splx(s); 1216 return error; 1217 } 1218 1219 static uint32_t 1220 bit_reverse_32(uint32_t x) 1221 { 1222 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 1223 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 1224 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 1225 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 1226 return (x >> 16) | (x << 16); 1227 } 1228 1229 static void 1230 scx_set_rcvfilt(struct scx_softc *sc) 1231 { 1232 struct ethercom * const ec = &sc->sc_ethercom; 1233 struct ifnet * const ifp = &ec->ec_if; 1234 struct ether_multistep step; 1235 struct ether_multi *enm; 1236 uint32_t mchash[2]; /* 2x 32 = 64 bit */ 1237 uint32_t csr, crc; 1238 int i; 1239 1240 csr = mac_read(sc, GMACAFR); 1241 csr &= ~(AFR_PR | AFR_PM | AFR_MHTE | AFR_HPF); 1242 mac_write(sc, GMACAFR, csr); 1243 1244 /* clear 15 entry supplemental perfect match filter */ 1245 for (i = 1; i < 16; i++) 1246 mac_write(sc, GMACMAH(i), 0); 1247 /* build 64 bit multicast hash filter */ 1248 crc = mchash[1] = mchash[0] = 0; 1249 1250 ETHER_LOCK(ec); 1251 if (ifp->if_flags & IFF_PROMISC) { 1252 ec->ec_flags |= ETHER_F_ALLMULTI; 1253 ETHER_UNLOCK(ec); 1254 /* run promisc. mode */ 1255 csr |= AFR_PR; 1256 goto update; 1257 } 1258 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1259 ETHER_FIRST_MULTI(step, ec, enm); 1260 i = 1; /* slot 0 is occupied */ 1261 while (enm != NULL) { 1262 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1263 /* 1264 * We must listen to a range of multicast addresses. 1265 * For now, just accept all multicasts, rather than 1266 * trying to set only those filter bits needed to match 1267 * the range. (At this time, the only use of address 1268 * ranges is for IP multicast routing, for which the 1269 * range is big enough to require all bits set.) 1270 */ 1271 ec->ec_flags |= ETHER_F_ALLMULTI; 1272 ETHER_UNLOCK(ec); 1273 /* accept all multi */ 1274 csr |= AFR_PM; 1275 goto update; 1276 } 1277 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 1278 if (i < 16) { 1279 /* use 15 entry perfect match filter */ 1280 uint32_t addr; 1281 uint8_t *ep = enm->enm_addrlo; 1282 addr = (ep[3] << 24) | (ep[2] << 16) 1283 | (ep[1] << 8) | ep[0]; 1284 mac_write(sc, GMACMAL(i), addr); 1285 addr = (ep[5] << 8) | ep[4]; 1286 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1287 } else { 1288 /* use hash table when too many */ 1289 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1290 crc = bit_reverse_32(~crc); 1291 /* 1(31) 5(30:26) bit sampling */ 1292 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 1293 } 1294 ETHER_NEXT_MULTI(step, enm); 1295 i++; 1296 } 1297 ETHER_UNLOCK(ec); 1298 if (crc) 1299 csr |= AFR_MHTE; 1300 csr |= AFR_HPF; /* use hash+perfect */ 1301 mac_write(sc, GMACMHTH, mchash[1]); 1302 mac_write(sc, GMACMHTL, mchash[0]); 1303 update: 1304 /* With PR or PM, MHTE/MHTL/MHTH are never consulted. really? */ 1305 mac_write(sc, GMACAFR, csr); 1306 return; 1307 } 1308 1309 static void 1310 scx_start(struct ifnet *ifp) 1311 { 1312 struct scx_softc *sc = ifp->if_softc; 1313 struct mbuf *m0; 1314 struct scx_txsoft *txs; 1315 bus_dmamap_t dmamap; 1316 int error, nexttx, lasttx, ofree, seg; 1317 uint32_t tdes0; 1318 1319 if ((ifp->if_flags & IFF_RUNNING) == 0) 1320 return; 1321 1322 /* Remember the previous number of free descriptors. */ 1323 ofree = sc->sc_txfree; 1324 1325 /* 1326 * Loop through the send queue, setting up transmit descriptors 1327 * until we drain the queue, or use up all available transmit 1328 * descriptors. 1329 */ 1330 for (;;) { 1331 IFQ_POLL(&ifp->if_snd, m0); 1332 if (m0 == NULL) 1333 break; 1334 1335 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1336 txreap(sc); 1337 if (sc->sc_txsfree == 0) 1338 break; 1339 } 1340 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1341 dmamap = txs->txs_dmamap; 1342 1343 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1344 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1345 if (error) { 1346 if (error == EFBIG) { 1347 aprint_error_dev(sc->sc_dev, 1348 "Tx packet consumes too many " 1349 "DMA segments, dropping...\n"); 1350 IFQ_DEQUEUE(&ifp->if_snd, m0); 1351 m_freem(m0); 1352 continue; 1353 } 1354 /* Short on resources, just stop for now. */ 1355 break; 1356 } 1357 1358 if (dmamap->dm_nsegs > sc->sc_txfree) { 1359 /* 1360 * Not enough free descriptors to transmit this 1361 * packet. We haven't committed anything yet, 1362 * so just unload the DMA map, put the packet 1363 * back on the queue, and punt. 1364 */ 1365 bus_dmamap_unload(sc->sc_dmat, dmamap); 1366 break; 1367 } 1368 1369 IFQ_DEQUEUE(&ifp->if_snd, m0); 1370 1371 /* 1372 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1373 */ 1374 1375 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1376 BUS_DMASYNC_PREWRITE); 1377 1378 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1379 lasttx = -1; 1380 for (nexttx = sc->sc_txnext, seg = 0; 1381 seg < dmamap->dm_nsegs; 1382 seg++, nexttx = MD_NEXTTX(nexttx)) { 1383 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1384 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1385 /* 1386 * If this is the first descriptor we're 1387 * enqueueing, don't set the OWN bit just 1388 * yet. That could cause a race condition. 1389 * We'll do it below. 1390 */ 1391 tdes->t3 = htole32(dmamap->dm_segs[seg].ds_len); 1392 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1393 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1394 tdes->t0 = htole32(tdes0 | (tdes->t0 & T0_EOD) | 1395 (15 << T0_TDRID) | T0_PT | 1396 sc->sc_t0cotso | T0_TRS); 1397 tdes0 = T0_OWN; /* 2nd and other segments */ 1398 /* NB; t0 DRID field contains zero */ 1399 lasttx = nexttx; 1400 } 1401 1402 /* Write deferred 1st segment T0_OWN at the final stage */ 1403 sc->sc_txdescs[lasttx].t0 |= htole32(T0_LS); 1404 sc->sc_txdescs[sc->sc_txnext].t0 |= htole32(T0_FS | T0_OWN); 1405 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1406 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1407 1408 /* submit one frame to xmit */ 1409 CSR_WRITE(sc, TXSUBMIT, 1); 1410 1411 txs->txs_mbuf = m0; 1412 txs->txs_firstdesc = sc->sc_txnext; 1413 txs->txs_lastdesc = lasttx; 1414 txs->txs_ndesc = dmamap->dm_nsegs; 1415 1416 sc->sc_txfree -= txs->txs_ndesc; 1417 sc->sc_txnext = nexttx; 1418 sc->sc_txsfree--; 1419 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1420 /* 1421 * Pass the packet to any BPF listeners. 1422 */ 1423 bpf_mtap(ifp, m0, BPF_D_OUT); 1424 } 1425 1426 if (sc->sc_txfree != ofree) { 1427 /* Set a watchdog timer in case the chip flakes out. */ 1428 ifp->if_timer = 5; 1429 } 1430 } 1431 1432 static void 1433 scx_watchdog(struct ifnet *ifp) 1434 { 1435 struct scx_softc *sc = ifp->if_softc; 1436 1437 /* 1438 * Since we're not interrupting every packet, sweep 1439 * up before we report an error. 1440 */ 1441 txreap(sc); 1442 1443 if (sc->sc_txfree != MD_NTXDESC) { 1444 aprint_error_dev(sc->sc_dev, 1445 "device timeout (txfree %d txsfree %d txnext %d)\n", 1446 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1447 if_statinc(ifp, if_oerrors); 1448 1449 /* Reset the interface. */ 1450 scx_init(ifp); 1451 } 1452 1453 scx_start(ifp); 1454 } 1455 1456 static int 1457 scx_intr(void *arg) 1458 { 1459 struct scx_softc *sc = arg; 1460 uint32_t enable, status; 1461 1462 status = CSR_READ(sc, xINTSR); /* not W1C */ 1463 enable = CSR_READ(sc, xINTAEN); 1464 if ((status & enable) == 0) 1465 return 0; 1466 if (status & (IRQ_TX | IRQ_RX)) { 1467 CSR_WRITE(sc, xINTAE_CLR, (IRQ_TX | IRQ_RX)); 1468 1469 status = CSR_READ(sc, RXISR); 1470 CSR_WRITE(sc, RXISR, status); 1471 if (status & RXI_RC_ERR) 1472 aprint_error_dev(sc->sc_dev, "Rx error\n"); 1473 if (status & (RXI_PKTCNT | RXI_TMREXP)) { 1474 rxintr(sc); 1475 (void)CSR_READ(sc, RXDONECNT); /* clear RXI_RXDONE */ 1476 } 1477 1478 status = CSR_READ(sc, TXISR); 1479 CSR_WRITE(sc, TXISR, status); 1480 if (status & TXI_TR_ERR) 1481 aprint_error_dev(sc->sc_dev, "Tx error\n"); 1482 if (status & (TXI_TXDONE | TXI_TMREXP)) { 1483 txreap(sc); 1484 (void)CSR_READ(sc, TXDONECNT); /* clear TXI_TXDONE */ 1485 } 1486 1487 CSR_WRITE(sc, xINTAE_SET, (IRQ_TX | IRQ_RX)); 1488 } 1489 return 1; 1490 } 1491 1492 static void 1493 txreap(struct scx_softc *sc) 1494 { 1495 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1496 struct scx_txsoft *txs; 1497 uint32_t txstat; 1498 int i; 1499 1500 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1501 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1502 txs = &sc->sc_txsoft[i]; 1503 1504 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1505 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1506 1507 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].t0); 1508 if (txstat & T0_OWN) /* desc is still in use */ 1509 break; 1510 1511 /* There is no way to tell transmission status per frame */ 1512 1513 if_statinc(ifp, if_opackets); 1514 1515 sc->sc_txfree += txs->txs_ndesc; 1516 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1517 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1518 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1519 m_freem(txs->txs_mbuf); 1520 txs->txs_mbuf = NULL; 1521 } 1522 sc->sc_txsdirty = i; 1523 if (sc->sc_txsfree == MD_TXQUEUELEN) 1524 ifp->if_timer = 0; 1525 } 1526 1527 static void 1528 rxintr(struct scx_softc *sc) 1529 { 1530 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1531 struct scx_rxsoft *rxs; 1532 struct mbuf *m; 1533 uint32_t rxstat; 1534 int i, len; 1535 1536 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1537 rxs = &sc->sc_rxsoft[i]; 1538 1539 SCX_CDRXSYNC(sc, i, 1540 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1541 1542 rxstat = le32toh(sc->sc_rxdescs[i].r0); 1543 if (rxstat & R0_OWN) /* desc is left empty */ 1544 break; 1545 1546 /* R0_FS | R0_LS must have been marked for this desc */ 1547 1548 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1549 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1550 1551 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1552 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1553 m = rxs->rxs_mbuf; 1554 1555 if (add_rxbuf(sc, i) != 0) { 1556 if_statinc(ifp, if_ierrors); 1557 SCX_INIT_RXDESC(sc, i); 1558 bus_dmamap_sync(sc->sc_dmat, 1559 rxs->rxs_dmamap, 0, 1560 rxs->rxs_dmamap->dm_mapsize, 1561 BUS_DMASYNC_PREREAD); 1562 continue; 1563 } 1564 1565 m_set_rcvif(m, ifp); 1566 m->m_pkthdr.len = m->m_len = len; 1567 1568 if (rxstat & R0_CSUM) { 1569 uint32_t csum = M_CSUM_IPv4; 1570 if (rxstat & R0_CERR) 1571 csum |= M_CSUM_IPv4_BAD; 1572 m->m_pkthdr.csum_flags |= csum; 1573 } 1574 if_percpuq_enqueue(ifp->if_percpuq, m); 1575 } 1576 sc->sc_rxptr = i; 1577 } 1578 1579 static int 1580 add_rxbuf(struct scx_softc *sc, int i) 1581 { 1582 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1583 struct mbuf *m; 1584 int error; 1585 1586 MGETHDR(m, M_DONTWAIT, MT_DATA); 1587 if (m == NULL) 1588 return ENOBUFS; 1589 1590 MCLGET(m, M_DONTWAIT); 1591 if ((m->m_flags & M_EXT) == 0) { 1592 m_freem(m); 1593 return ENOBUFS; 1594 } 1595 1596 if (rxs->rxs_mbuf != NULL) 1597 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1598 1599 rxs->rxs_mbuf = m; 1600 1601 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1602 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1603 if (error) { 1604 aprint_error_dev(sc->sc_dev, 1605 "can't load rx DMA map %d, error = %d\n", i, error); 1606 panic("add_rxbuf"); 1607 } 1608 1609 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1610 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1611 SCX_INIT_RXDESC(sc, i); 1612 1613 return 0; 1614 } 1615 1616 static void 1617 rxdrain(struct scx_softc *sc) 1618 { 1619 struct scx_rxsoft *rxs; 1620 int i; 1621 1622 for (i = 0; i < MD_NRXDESC; i++) { 1623 rxs = &sc->sc_rxsoft[i]; 1624 if (rxs->rxs_mbuf != NULL) { 1625 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1626 m_freem(rxs->rxs_mbuf); 1627 rxs->rxs_mbuf = NULL; 1628 } 1629 } 1630 } 1631 1632 void 1633 mii_statchg(struct ifnet *ifp) 1634 { 1635 struct scx_softc *sc = ifp->if_softc; 1636 struct mii_data *mii = &sc->sc_mii; 1637 const int Mbps[4] = { 10, 100, 1000, 0 }; 1638 uint32_t miisr, mcr, fcr; 1639 int spd; 1640 1641 /* decode MIISR register value */ 1642 miisr = mac_read(sc, GMACMIISR); 1643 spd = Mbps[(miisr & MIISR_SPD) >> 1]; 1644 #if 1 1645 static uint32_t oldmiisr = 0; 1646 if (miisr != oldmiisr) { 1647 printf("MII link status (0x%x) %s", 1648 miisr, (miisr & MIISR_LUP) ? "up" : "down"); 1649 if (miisr & MIISR_LUP) { 1650 printf(" spd%d", spd); 1651 if (miisr & MIISR_FDX) 1652 printf(",full-duplex"); 1653 } 1654 printf("\n"); 1655 } 1656 #endif 1657 /* Get flow control negotiation result. */ 1658 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1659 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1660 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1661 1662 /* Adjust speed 1000/100/10. */ 1663 mcr = mac_read(sc, GMACMCR); 1664 if (spd == 1000) 1665 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 1666 else { 1667 if (spd == 100 && sc->sc_100mii) 1668 mcr |= MCR_SPD100; 1669 mcr |= MCR_USEMII; 1670 } 1671 mcr |= MCR_CST | MCR_JE; 1672 if (sc->sc_100mii == 0) 1673 mcr |= MCR_IBN; 1674 1675 /* Adjust duplexity and PAUSE flow control. */ 1676 mcr &= ~MCR_USEFDX; 1677 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1678 if (miisr & MIISR_FDX) { 1679 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1680 fcr |= FCR_TFE; 1681 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1682 fcr |= FCR_RFE; 1683 mcr |= MCR_USEFDX; 1684 } 1685 mac_write(sc, GMACMCR, mcr); 1686 mac_write(sc, GMACFCR, fcr); 1687 1688 #if 1 1689 if (miisr != oldmiisr) { 1690 printf("%ctxfe, %crxfe\n", 1691 (fcr & FCR_TFE) ? '+' : '-', 1692 (fcr & FCR_RFE) ? '+' : '-'); 1693 } 1694 oldmiisr = miisr; 1695 #endif 1696 } 1697 1698 static void 1699 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1700 { 1701 struct scx_softc *sc = ifp->if_softc; 1702 struct mii_data *mii = &sc->sc_mii; 1703 1704 mii_pollstat(mii); 1705 ifmr->ifm_status = mii->mii_media_status; 1706 ifmr->ifm_active = sc->sc_flowflags | 1707 (mii->mii_media_active & ~IFM_ETH_FMASK); 1708 } 1709 1710 static int 1711 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1712 { 1713 struct scx_softc *sc = device_private(self); 1714 uint32_t miia; 1715 int ntries; 1716 1717 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1718 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1719 for (ntries = 0; ntries < 1000; ntries++) { 1720 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1721 goto unbusy; 1722 DELAY(1); 1723 } 1724 return ETIMEDOUT; 1725 unbusy: 1726 *val = mac_read(sc, GMACGDR); 1727 return 0; 1728 } 1729 1730 static int 1731 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1732 { 1733 struct scx_softc *sc = device_private(self); 1734 uint32_t miia; 1735 uint16_t dummy; 1736 int ntries; 1737 1738 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1739 mac_write(sc, GMACGDR, val); 1740 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1741 for (ntries = 0; ntries < 1000; ntries++) { 1742 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1743 goto unbusy; 1744 DELAY(1); 1745 } 1746 return ETIMEDOUT; 1747 unbusy: 1748 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1749 return 0; 1750 } 1751 1752 static void 1753 phy_tick(void *arg) 1754 { 1755 struct scx_softc *sc = arg; 1756 struct mii_data *mii = &sc->sc_mii; 1757 int s; 1758 1759 s = splnet(); 1760 mii_tick(mii); 1761 splx(s); 1762 #ifdef GMAC_EVENT_COUNTERS 1763 /* 80 event counters exist */ 1764 #endif 1765 callout_schedule(&sc->sc_callout, hz); 1766 } 1767 1768 static void 1769 reset_hardware(struct scx_softc *sc) 1770 { 1771 1772 if (CSR_READ(sc, CORESTAT) != 0) { 1773 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP); 1774 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP); 1775 1776 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP, 0); 1777 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP, 0); 1778 } 1779 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 1780 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */ 1781 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS); 1782 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0); 1783 } 1784 1785 /* 1786 * 3 independent uengines exist to process host2media, media2host and 1787 * packet data flows. 1788 */ 1789 static void 1790 loaducode(struct scx_softc *sc) 1791 { 1792 uint32_t up, lo, sz; 1793 uint64_t addr; 1794 1795 reset_hardware(sc); 1796 CSR_WRITE(sc, xINTSR, IRQ_UCODE); 1797 1798 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1799 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1800 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1801 sz *= 4; 1802 addr = ((uint64_t)up << 32) | lo; 1803 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1804 injectucode(sc, UCODE_H2M, (bus_addr_t)addr, (bus_size_t)sz); 1805 1806 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1807 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1808 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1809 sz *= 4; 1810 addr = ((uint64_t)up << 32) | lo; 1811 injectucode(sc, UCODE_M2H, (bus_addr_t)addr, (bus_size_t)sz); 1812 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1813 1814 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1815 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1816 sz *= 4; 1817 injectucode(sc, UCODE_PKT, (bus_addr_t)lo, (bus_size_t)sz); 1818 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1819 1820 WAIT_FOR_SET(sc, xINTSR, IRQ_UCODE, 0); 1821 /* XXX may take long time to end ?! XXX */ 1822 CSR_WRITE(sc, xINTSR, IRQ_UCODE); 1823 } 1824 1825 static void 1826 injectucode(struct scx_softc *sc, int port, 1827 bus_addr_t addr, bus_size_t size) 1828 { 1829 bus_space_handle_t bsh; 1830 bus_size_t off; 1831 uint32_t ucode; 1832 1833 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1834 aprint_error_dev(sc->sc_dev, 1835 "eeprom map failure for ucode port 0x%x\n", port); 1836 return; 1837 } 1838 for (off = 0; off < size; off += 4) { 1839 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1840 CSR_WRITE(sc, port, ucode); 1841 } 1842 bus_space_unmap(sc->sc_st, bsh, size); 1843 } 1844 1845 /* GAR 5:2 MDIO frequency selection */ 1846 static int 1847 get_mdioclk(uint32_t freq) 1848 { 1849 1850 freq /= 1000 * 1000; 1851 if (freq < 35) 1852 return GAR_MDIO_25_35MHZ; 1853 if (freq < 60) 1854 return GAR_MDIO_35_60MHZ; 1855 if (freq < 100) 1856 return GAR_MDIO_60_100MHZ; 1857 if (freq < 150) 1858 return GAR_MDIO_100_150MHZ; 1859 if (freq < 250) 1860 return GAR_MDIO_150_250MHZ; 1861 return GAR_MDIO_250_300MHZ; 1862 } 1863
Indexes created Mon Oct 13 16:09:52 GMT 2025