if_scx.c revision 1.41
1 /* $NetBSD: if_scx.c,v 1.41 2023/06/13 00:15:52 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * Multiple Tx and Rx queues exist inside and dedicated descriptor 38 * fields specifies which queue is to use. Three internal micro-processors 39 * to handle incoming frames, outgoing frames and packet data crypto 40 * processing. uP programs are stored in an external flash memory and 41 * have to be loaded by device driver. 42 * NetSec uses Synopsys DesignWare Core EMAC. DWC implementation 43 * register (0x20) is known to have 0x10.36 and feature register (0x1058) 44 * reports 0x11056f37. 45 * <24> alternative/enhanced desc format 46 * <18> receive IP type 2 checksum offload 47 * <16> transmit checksum offload 48 * <11> event counter (mac management counter, MMC) 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.41 2023/06/13 00:15:52 nisimura Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/bus.h> 56 #include <sys/intr.h> 57 #include <sys/device.h> 58 #include <sys/callout.h> 59 #include <sys/mbuf.h> 60 #include <sys/errno.h> 61 #include <sys/rndsource.h> 62 #include <sys/kernel.h> 63 #include <sys/systm.h> 64 65 #include <net/if.h> 66 #include <net/if_media.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <net/bpf.h> 72 73 #include <dev/fdt/fdtvar.h> 74 #include <dev/acpi/acpireg.h> 75 #include <dev/acpi/acpivar.h> 76 #include <dev/acpi/acpi_intr.h> 77 78 /* SC2A11 GbE has 64-bit paddr descriptor */ 79 struct tdes { 80 uint32_t t0, t1, t2, t3; 81 }; 82 struct rdes { 83 uint32_t r0, r1, r2, r3; 84 }; 85 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 86 #define T0_LD (1U<<30) /* last descriptor in array */ 87 #define T0_DRID (24) /* 29:24 desc ring id */ 88 #define T0_PT (1U<<21) /* 23:21 "pass-through" */ 89 #define T0_TDRID (16) /* 20:16 target desc ring id: GMAC=15 */ 90 #define T0_CC (1U<<15) /* ??? */ 91 #define T0_FS (1U<<9) /* first segment of frame */ 92 #define T0_LS (1U<<8) /* last segment of frame */ 93 #define T0_CSUM (1U<<7) /* enable check sum offload */ 94 #define T0_TSO (1U<<6) /* enable TCP segment offload */ 95 #define T0_TRS (1U<<4) /* 5:4 "TRS" ??? */ 96 /* T1 frame segment address 63:32 */ 97 /* T2 frame segment address 31:0 */ 98 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */ 99 #define R0_OWN (1U<<31) /* desc is empty */ 100 #define R0_LD (1U<<30) /* last descriptor in array */ 101 #define R0_SDRID (24) /* 29:24 source desc ring id */ 102 #define R0_FR (1U<<23) /* found fragmented */ 103 #define R0_ER (1U<<21) /* Rx error indication */ 104 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 105 #define R0_TDRID (12) /* 15:12 target desc ring id */ 106 #define R0_FS (1U<<9) /* first segment of frame */ 107 #define R0_LS (1U<<8) /* last segment of frame */ 108 #define R0_CSUM (3U<<6) /* 7:6 checksum status, 0: undone */ 109 #define R0_CERR (2U<<6) /* 2: found bad */ 110 #define R0_COK (1U<<6) /* 1: found ok */ 111 /* R1 frame address 63:32 */ 112 /* R2 frame address 31:0 */ 113 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 114 115 /* 116 * SC2A11 registers. 0x100 - 1204 117 */ 118 #define SWRESET 0x104 119 #define SRST_RUN (1U<<31) /* instruct start, 0 to stop */ 120 #define COMINIT 0x120 121 #define INIT_DB (1U<<2) /* ???; self clear when done */ 122 #define INIT_CLS (1U<<1) /* ???; self clear when done */ 123 #define PKTCTRL 0x140 /* pkt engine control */ 124 #define MODENRM (1U<<28) /* set operational mode to 'normal' */ 125 #define ENJUMBO (1U<<27) /* allow jumbo frame */ 126 #define RPTCSUMERR (1U<<3) /* log Rx checksum error */ 127 #define RPTHDCOMP (1U<<2) /* log header incomplete condition */ 128 #define RPTHDERR (1U<<1) /* log header error */ 129 #define DROPNOMATCH (1U<<0) /* drop no match frames */ 130 #define xINTSR 0x200 /* aggregated interrupt status */ 131 #define IRQ_UCODE (1U<<20) /* ucode load completed; W1C */ 132 #define IRQ_MAC (1U<<19) /* ??? */ 133 #define IRQ_PKT (1U<<18) /* ??? */ 134 #define IRQ_BOOTCODE (1U<<5) /* ??? */ 135 #define IRQ_XDONE (1U<<4) /* ??? mode change completed */ 136 #define IRQ_RX (1U<<1) /* top level Rx interrupt */ 137 #define IRQ_TX (1U<<0) /* top level Tx interrupt */ 138 #define xINTAEN 0x204 /* INT_A enable */ 139 #define xINTAE_SET 0x234 /* bit to set */ 140 #define xINTAE_CLR 0x238 /* bit to clr */ 141 #define xINTBEN 0x23c /* INT_B enable */ 142 #define xINTBE_SET 0x240 /* bit to set */ 143 #define xINTBE_CLR 0x244 /* bit to clr */ 144 #define TXISR 0x400 /* transmit status; W1C */ 145 #define TXIEN 0x404 /* tx interrupt enable */ 146 #define TXIE_SET 0x428 /* bit to set */ 147 #define TXIE_CLR 0x42c /* bit to clr */ 148 #define TXI_NTOWNR (1U<<17) /* ??? desc array got empty */ 149 #define TXI_TR_ERR (1U<<16) /* xmit error */ 150 #define TXI_TXDONE (1U<<15) /* xmit completed */ 151 #define TXI_TMREXP (1U<<14) /* coalesce guard timer expired */ 152 #define RXISR 0x440 /* receive status; W1C */ 153 #define RXIEN 0x444 /* rx interrupt enable */ 154 #define RXIE_SET 0x468 /* bit to set */ 155 #define RXIE_CLR 0x46c /* bit to clr */ 156 #define RXI_RC_ERR (1U<<16) /* recv error */ 157 #define RXI_PKTCNT (1U<<15) /* recv counter has new value */ 158 #define RXI_TMREXP (1U<<14) /* coalesce guard timer expired */ 159 /* 13 sets of special purpose desc interrupt handling register exist */ 160 #define TDBA_LO 0x408 /* tdes array base addr 31:0 */ 161 #define TDBA_HI 0x434 /* tdes array base addr 63:32 */ 162 #define RDBA_LO 0x448 /* rdes array base addr 31:0 */ 163 #define RDBA_HI 0x474 /* rdes array base addr 63:32 */ 164 /* 13 pairs of special purpose desc array base address register exist */ 165 #define TXCONF 0x430 166 #define RXCONF 0x470 167 #define DESCNF_UP (1U<<31) /* 'up-and-running' */ 168 #define DESCNF_CHRST (1U<<30) /* channel reset */ 169 #define DESCNF_TMR (1U<<4) /* coalesce timer mode select */ 170 #define DESCNF_LE (1) /* little endian desc format */ 171 #define TXSUBMIT 0x410 /* submit frame(s) to transmit */ 172 #define TXCOALESC 0x418 /* tx intr coalesce upper bound */ 173 #define RXCOALESC 0x458 /* rx intr coalesce upper bound */ 174 #define TCLSCTIME 0x420 /* tintr guard time usec, MSB to on */ 175 #define RCLSCTIME 0x460 /* rintr guard time usec, MSB to on */ 176 #define TXDONECNT 0x414 /* tx completed count, auto-zero */ 177 #define RXAVAILCNT 0x454 /* rx available count, auto-zero */ 178 #define DMACTL_TMR 0x20c /* engine DMA timer value */ 179 #define UCODE_H2M 0x210 /* host2media engine ucode port */ 180 #define UCODE_M2H 0x21c /* media2host engine ucode port */ 181 #define CORESTAT 0x218 /* engine run state */ 182 #define PKTSTOP (1U<<2) /* pkt engine stopped */ 183 #define M2HSTOP (1U<<1) /* M2H engine stopped */ 184 #define H2MSTOP (1U<<0) /* H2M engine stopped */ 185 #define DMACTL_H2M 0x214 /* host2media engine control */ 186 #define DMACTL_M2H 0x220 /* media2host engine control */ 187 #define DMACTL_STOP (1U<<0) /* instruct stop; self-clear */ 188 #define M2H_MODE_TRANS (1U<<20) /* initiate M2H mode change */ 189 #define UCODE_PKT 0x0d0 /* packet engine ucode port */ 190 #define CLKEN 0x100 /* clock distribution enable */ 191 #define CLK_G (1U<<5) /* feed clk domain G */ 192 #define CLK_C (1U<<1) /* feed clk domain C */ 193 #define CLK_D (1U<<0) /* feed clk domain D */ 194 195 /* GMAC register indirect access. thru MACCMD/MACDATA operation */ 196 #define MACDATA 0x11c0 /* gmac register rd/wr data */ 197 #define MACCMD 0x11c4 /* gmac register operation */ 198 #define CMD_IOWR (1U<<28) /* write op */ 199 #define CMD_BUSY (1U<<31) /* busy bit */ 200 #define MACSTAT 0x1024 /* gmac status; ??? */ 201 #define MACINTE 0x1028 /* interrupt enable; ??? */ 202 203 #define FLOWTHR 0x11cc /* flow control threshold */ 204 /* 31:16 pause threshold, 15:0 resume threshold */ 205 #define INTF_SEL 0x11d4 /* phy interface type */ 206 #define INTF_GMII 0 207 #define INTF_RGMII 1 208 #define INTF_RMII 4 209 210 #define DESC_INIT 0x11fc /* write 1 for desc init, SC */ 211 #define DESC_SRST 0x1204 /* write 1 for desc sw reset, SC */ 212 #define MODE_TRANS 0x500 /* mode change completion status */ 213 #define N2T_DONE (1U<<20) /* normal->taiki change completed */ 214 #define T2N_DONE (1U<<19) /* taiki->normal change completed */ 215 #define MACADRH 0x10c /* ??? */ 216 #define MACADRL 0x110 /* ??? */ 217 #define MCVER 0x22c /* micro controller version */ 218 #define HWVER 0x230 /* hardware version */ 219 220 /* 221 * GMAC registers are mostly identical to Synopsys DesignWare Core 222 * Ethernet. These must be handled by indirect access. 223 */ 224 #define GMACMCR 0x0000 /* MAC configuration */ 225 #define MCR_IBN (1U<<30) /* watch in-band-signal */ 226 #define MCR_CST (1U<<25) /* strip CRC */ 227 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 228 #define MCR_WD (1U<<23) /* allow long >2048 tx frame */ 229 #define MCR_JE (1U<<20) /* allow ~9018 tx jumbo frame */ 230 #define MCR_IFG (7U<<17) /* 19:17 IFG value 0~7 */ 231 #define MCR_DCRS (1U<<16) /* ignore (G)MII HDX Tx error */ 232 #define MCR_PS (1U<<15) /* 1: MII 10/100, 0: GMII 1000 */ 233 #define MCR_FES (1U<<14) /* force speed 100 */ 234 #define MCR_DO (1U<<13) /* don't receive my own HDX Tx frames */ 235 #define MCR_LOOP (1U<<12) /* run loop back */ 236 #define MCR_USEFDX (1U<<11) /* force full duplex */ 237 #define MCR_IPCEN (1U<<10) /* handle checksum */ 238 #define MCR_DR (1U<<9) /* attempt no tx retry, send once */ 239 #define MCR_LUD (1U<<8) /* link condition report when RGMII */ 240 #define MCR_ACS (1U<<7) /* auto pad auto strip CRC */ 241 #define MCR_DC (1U<<4) /* report excessive tx deferral */ 242 #define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */ 243 #define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */ 244 #define MCR_PREA (3U) /* 1:0 preamble len. 0~2 */ 245 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 246 #define AFR_RA (1U<<31) /* accept all irrespective of filt. */ 247 #define AFR_HPF (1U<<10) /* hash+perfect filter, or hash only */ 248 #define AFR_SAF (1U<<9) /* source address filter */ 249 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 250 #define AFR_PCF (2U<<6) /* ??? */ 251 #define AFR_DBF (1U<<5) /* reject broadcast frame */ 252 #define AFR_PM (1U<<4) /* accept all multicast frame */ 253 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 254 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 255 #define AFR_UHTE (1U<<1) /* use hash table for unicast */ 256 #define AFR_PR (1U<<0) /* run promisc mode */ 257 #define GMACGAR 0x0010 /* MDIO operation */ 258 #define GAR_PHY (11) /* 15:11 mii phy */ 259 #define GAR_REG (6) /* 10:6 mii reg */ 260 #define GAR_CLK (2) /* 5:2 mdio clock tick ratio */ 261 #define GAR_IOWR (1U<<1) /* MDIO write op */ 262 #define GAR_BUSY (1U<<0) /* busy bit */ 263 #define GAR_MDIO_25_35MHZ 2 264 #define GAR_MDIO_35_60MHZ 3 265 #define GAR_MDIO_60_100MHZ 0 266 #define GAR_MDIO_100_150MHZ 1 267 #define GAR_MDIO_150_250MHZ 4 268 #define GAR_MDIO_250_300MHZ 5 269 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 270 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 271 /* 31:16 pause timer value, 5:4 pause timer threshold */ 272 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 273 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 274 #define GMACIMPL 0x0020 /* implementation id */ 275 #define GMACISR 0x0038 /* interrupt status indication */ 276 #define GMACIMR 0x003c /* interrupt mask to inhibit */ 277 #define ISR_TS (1U<<9) /* time stamp operation detected */ 278 #define ISR_CO (1U<<7) /* Rx checksum offload completed */ 279 #define ISR_TX (1U<<6) /* Tx completed */ 280 #define ISR_RX (1U<<5) /* Rx completed */ 281 #define ISR_ANY (1U<<4) /* any of above 5-7 report */ 282 #define ISR_LC (1U<<0) /* link status change detected */ 283 #define GMACMAH0 0x0040 /* my own MAC address 47:32 */ 284 #define GMACMAL0 0x0044 /* my own MAC address 31:0 */ 285 #define GMACMAH(i) ((i)*8+0x40) /* supplemental MAC addr 1-15 */ 286 #define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */ 287 /* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */ 288 #define GMACAMAH(i) ((i)*8+0x800) /* supplemental MAC addr 16-31 */ 289 #define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */ 290 /* supplimental MAH bit-31: slot in use, no other bit is effective */ 291 #define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */ 292 #define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */ 293 #define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */ 294 #define GMACVTAG 0x001c /* VLAN tag control */ 295 #define VTAG_HASH (1U<<19) /* use VLAN tag hash table */ 296 #define VTAG_SVLAN (1U<<18) /* handle type 0x88A8 SVLAN frame */ 297 #define VTAG_INV (1U<<17) /* run inverse match logic */ 298 #define VTAG_ETV (1U<<16) /* use only 12bit VID field to match */ 299 /* 15:0 concat of PRIO+CFI+VID */ 300 #define GMACVHT 0x0588 /* 16-bit VLAN tag hash */ 301 #define GMACMIISR 0x00d8 /* resolved RGMII/SGMII link status */ 302 #define MIISR_LUP (1U<<3) /* link up(1)/down(0) report */ 303 #define MIISR_SPD (3U<<1) /* 2:1 speed 10(0)/100(1)/1000(2) */ 304 #define MIISR_FDX (1U<<0) /* fdx detected */ 305 306 #define GMACLPIS 0x0030 /* LPI control & status */ 307 #define LPIS_TXA (1U<<19) /* complete Tx in progress and LPI */ 308 #define LPIS_PLS (1U<<17) 309 #define LPIS_EN (1U<<16) /* 1: enter LPI mode, 0: exit */ 310 #define LPIS_TEN (1U<<0) /* Tx LPI report */ 311 #define GMACLPIC 0x0034 /* LPI timer control */ 312 #define LPIC_LST (5) /* 16:5 ??? */ 313 #define LPIC_TWT (0) /* 15:0 ??? */ 314 /* 0x700-764 Time Stamp control */ 315 316 #define GMACBMR 0x1000 /* DMA bus mode control */ 317 /* 24 8xPBL multiply by 8 for RPBL & PBL values 318 * 23 USP 1 to use RPBL for Rx DMA burst, 0 to share PBL by Rx and Tx 319 * 22:17 RPBL 320 * 16 FB fixed burst 321 * 15:14 priority between Rx and Tx 322 * 3 rxtx ratio 41 323 * 2 rxtx ratio 31 324 * 1 rxtx ratio 21 325 * 0 rxtx ratio 11 326 * 13:8 PBL possible DMA burst length 327 * 7 ATDS select 32-byte descriptor format for advanced features 328 * 6:2 DSL descriptor skip length, 0 for adjuscent, counted on bus width 329 * 0 MAC reset op. self-clear 330 */ 331 #define BMR_RST (1) /* reset op. self clear when done */ 332 #define GMACTPD 0x1004 /* write any to resume tdes */ 333 #define GMACRPD 0x1008 /* write any to resume rdes */ 334 #define GMACRDLA 0x100c /* rdes base address 32bit paddr */ 335 #define GMACTDLA 0x1010 /* tdes base address 32bit paddr */ 336 #define GMACDSR 0x1014 /* DMA status detail report; W1C */ 337 #define GMACDIE 0x101c /* DMA interrupt enable */ 338 #define DMAI_LPI (1U<<30) /* LPI interrupt */ 339 #define DMAI_TTI (1U<<29) /* timestamp trigger interrupt */ 340 #define DMAI_GMI (1U<<27) /* management counter interrupt */ 341 #define DMAI_GLI (1U<<26) /* xMII link change detected */ 342 #define DMAI_EB (23) /* 25:23 DMA bus error detected */ 343 #define DMAI_TS (20) /* 22:20 Tx DMA state report */ 344 #define DMAI_RS (17) /* 29:17 Rx DMA state report */ 345 #define DMAI_NIS (1U<<16) /* normal interrupt summary; W1C */ 346 #define DMAI_AIS (1U<<15) /* abnormal interrupt summary; W1C */ 347 #define DMAI_ERI (1U<<14) /* the first Rx buffer is filled */ 348 #define DMAI_FBI (1U<<13) /* DMA bus error detected */ 349 #define DMAI_ETI (1U<<10) /* single frame Tx completed */ 350 #define DMAI_RWT (1U<<9) /* longer than 2048 frame received */ 351 #define DMAI_RPS (1U<<8) /* Rx process is now stopped */ 352 #define DMAI_RU (1U<<7) /* Rx descriptor not available */ 353 #define DMAI_RI (1U<<6) /* frame Rx completed by !R1_DIC */ 354 #define DMAI_UNF (1U<<5) /* Tx underflow detected */ 355 #define DMAI_OVF (1U<<4) /* receive buffer overflow detected */ 356 #define DMAI_TJT (1U<<3) /* longer than 2048 frame sent */ 357 #define DMAI_TU (1U<<2) /* Tx descriptor not available */ 358 #define DMAI_TPS (1U<<1) /* transmission is stopped */ 359 #define DMAI_TI (1U<<0) /* frame Tx completed by T0_IC */ 360 #define GMACOMR 0x1018 /* DMA operation mode */ 361 #define OMR_RSF (1U<<25) /* 1: Rx store&forward, 0: immed. */ 362 #define OMR_TSF (1U<<21) /* 1: Tx store&forward, 0: immed. */ 363 #define OMR_TTC (14) /* 16:14 Tx threshold */ 364 #define OMR_ST (1U<<13) /* run Tx DMA engine, 0 to stop */ 365 #define OMR_RFD (11) /* 12:11 Rx FIFO fill level */ 366 #define OMR_EFC (1U<<8) /* transmit PAUSE to throttle Rx lvl. */ 367 #define OMR_FEF (1U<<7) /* allow to receive error frames */ 368 #define OMR_SR (1U<<1) /* run Rx DMA engine, 0 to stop */ 369 #define GMACEVCS 0x1020 /* missed frame or ovf detected */ 370 #define GMACRWDT 0x1024 /* enable rx watchdog timer interrupt */ 371 #define GMACAXIB 0x1028 /* AXI bus mode control */ 372 #define GMACAXIS 0x102c /* AXI status report */ 373 /* 0x1048 current tx desc address */ 374 /* 0x104c current rx desc address */ 375 /* 0x1050 current tx buffer address */ 376 /* 0x1054 current rx buffer address */ 377 #define HWFEA 0x1058 /* DWC feature report */ 378 #define FEA_EXDESC (1U<<24) /* alternative/enhanced desc layout */ 379 #define FEA_2COE (1U<<18) /* Rx type 2 IP checksum offload */ 380 #define FEA_1COE (1U<<17) /* Rx type 1 IP checksum offload */ 381 #define FEA_TXOE (1U<<16) /* Tx checksum offload */ 382 #define FEA_MMC (1U<<11) /* RMON event counter */ 383 384 #define GMACEVCTL 0x0100 /* event counter control */ 385 #define EVC_FHP (1U<<5) /* full-half preset */ 386 #define EVC_CP (1U<<4) /* counter preset */ 387 #define EVC_MCF (1U<<3) /* counter freeze */ 388 #define EVC_ROR (1U<<2) /* auto-zero on counter read */ 389 #define EVC_CSR (1U<<1) /* counter stop rollover */ 390 #define EVC_CR (1U<<0) /* reset counters */ 391 #define GMACEVCNT(i) ((i)*4+0x114) /* 80 event counters 0x114 - 0x284 */ 392 393 /* 0x400-4ac L3/L4 control */ 394 395 /* 396 * flash memory layout 397 * 0x00 - 07 48-bit MAC station address. 4 byte wise in BE order. 398 * 0x08 - 0b H->MAC xfer engine program start addr 63:32. 399 * 0x0c - 0f H2M program addr 31:0 (these are absolute addr, not offset) 400 * 0x10 - 13 H2M program length in 4 byte count. 401 * 0x14 - 0b M->HOST xfer engine program start addr 63:32. 402 * 0x18 - 0f M2H program addr 31:0 (absolute addr, not relative) 403 * 0x1c - 13 M2H program length in 4 byte count. 404 * 0x20 - 23 packet engine program addr 31:0, (absolute addr, not offset) 405 * 0x24 - 27 packet program length in 4 byte count. 406 * 407 * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0. 408 */ 409 410 #define _BMR 0x00412080 /* XXX TBD */ 411 /* NetSec uses local RAM to handle GMAC desc arrays */ 412 #define _RDLA 0x18000 413 #define _TDLA 0x1c000 414 /* lower address region is used for intermediate frame data buffers */ 415 416 /* 417 * all below are software construction. 418 */ 419 #define MD_NTXDESC 128 420 #define MD_NRXDESC 64 421 422 #define MD_NTXSEGS 16 423 #define MD_TXQUEUELEN 8 424 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 425 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 426 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 427 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 428 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 429 430 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 431 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 432 433 struct control_data { 434 struct tdes cd_txdescs[MD_NTXDESC]; 435 struct rdes cd_rxdescs[MD_NRXDESC]; 436 }; 437 #define SCX_CDOFF(x) offsetof(struct control_data, x) 438 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 439 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 440 441 struct scx_txsoft { 442 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 443 bus_dmamap_t txs_dmamap; /* our DMA map */ 444 int txs_firstdesc; /* first descriptor in packet */ 445 int txs_lastdesc; /* last descriptor in packet */ 446 int txs_ndesc; /* # of descriptors used */ 447 }; 448 449 struct scx_rxsoft { 450 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 451 bus_dmamap_t rxs_dmamap; /* our DMA map */ 452 }; 453 454 struct scx_softc { 455 device_t sc_dev; /* generic device information */ 456 bus_space_tag_t sc_st; /* bus space tag */ 457 bus_space_handle_t sc_sh; /* bus space handle */ 458 bus_size_t sc_sz; /* csr map size */ 459 bus_space_handle_t sc_eesh; /* eeprom section handle */ 460 bus_size_t sc_eesz; /* eeprom map size */ 461 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 462 struct ethercom sc_ethercom; /* Ethernet common data */ 463 struct mii_data sc_mii; /* MII */ 464 callout_t sc_callout; /* PHY monitor callout */ 465 bus_dma_segment_t sc_seg; /* descriptor store seg */ 466 int sc_nseg; /* descriptor store nseg */ 467 void *sc_ih; /* interrupt cookie */ 468 int sc_phy_id; /* PHY address */ 469 int sc_flowflags; /* 802.3x PAUSE flow control */ 470 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 471 uint32_t sc_t0cotso; /* T0_CSUM | T0_TSO to run */ 472 int sc_miigmii; /* 1: MII/GMII, 0: RGMII */ 473 int sc_phandle; /* fdt phandle */ 474 uint64_t sc_freq; 475 uint32_t sc_maxsize; 476 477 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 478 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 479 480 struct control_data *sc_control_data; 481 #define sc_txdescs sc_control_data->cd_txdescs 482 #define sc_rxdescs sc_control_data->cd_rxdescs 483 484 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 485 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 486 int sc_txfree; /* number of free Tx descriptors */ 487 int sc_txnext; /* next ready Tx descriptor */ 488 int sc_txsfree; /* number of free Tx jobs */ 489 int sc_txsnext; /* next ready Tx job */ 490 int sc_txsdirty; /* dirty Tx jobs */ 491 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 492 493 krndsource_t rnd_source; /* random source */ 494 #ifdef GMAC_EVENT_COUNTERS 495 /* 80 event counters exist */ 496 #endif 497 }; 498 499 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 500 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 501 502 #define SCX_CDTXSYNC(sc, x, n, ops) \ 503 do { \ 504 int __x, __n; \ 505 \ 506 __x = (x); \ 507 __n = (n); \ 508 \ 509 /* If it will wrap around, sync to the end of the ring. */ \ 510 if ((__x + __n) > MD_NTXDESC) { \ 511 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 512 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 513 (MD_NTXDESC - __x), (ops)); \ 514 __n -= (MD_NTXDESC - __x); \ 515 __x = 0; \ 516 } \ 517 \ 518 /* Now sync whatever is left. */ \ 519 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 520 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 521 } while (/*CONSTCOND*/0) 522 523 #define SCX_CDRXSYNC(sc, x, ops) \ 524 do { \ 525 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 526 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 527 } while (/*CONSTCOND*/0) 528 529 #define SCX_INIT_RXDESC(sc, x) \ 530 do { \ 531 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 532 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 533 struct mbuf *__m = __rxs->rxs_mbuf; \ 534 bus_addr_t __p = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 535 bus_size_t __z = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 536 __m->m_data = __m->m_ext.ext_buf; \ 537 __rxd->r3 = htole32(__z - 4); \ 538 __rxd->r2 = htole32(BUS_ADDR_LO32(__p)); \ 539 __rxd->r1 = htole32(BUS_ADDR_HI32(__p)); \ 540 __rxd->r0 &= htole32(R0_LD); \ 541 __rxd->r0 |= htole32(R0_OWN); \ 542 } while (/*CONSTCOND*/0) 543 544 /* memory mapped CSR register access */ 545 #define CSR_READ(sc,off) \ 546 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 547 #define CSR_WRITE(sc,off,val) \ 548 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 549 550 /* flash memory access */ 551 #define EE_READ(sc,off) \ 552 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 553 554 static int scx_fdt_match(device_t, cfdata_t, void *); 555 static void scx_fdt_attach(device_t, device_t, void *); 556 static int scx_acpi_match(device_t, cfdata_t, void *); 557 static void scx_acpi_attach(device_t, device_t, void *); 558 559 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 560 scx_fdt_match, scx_fdt_attach, NULL, NULL); 561 562 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 563 scx_acpi_match, scx_acpi_attach, NULL, NULL); 564 565 static void scx_attach_i(struct scx_softc *); 566 static void scx_reset(struct scx_softc *); 567 static void scx_stop(struct ifnet *, int); 568 static int scx_init(struct ifnet *); 569 static int scx_ioctl(struct ifnet *, u_long, void *); 570 static void scx_set_rcvfilt(struct scx_softc *); 571 static void scx_start(struct ifnet *); 572 static void scx_watchdog(struct ifnet *); 573 static int scx_intr(void *); 574 static void txreap(struct scx_softc *); 575 static void rxfill(struct scx_softc *); 576 static int add_rxbuf(struct scx_softc *, int); 577 static void rxdrain(struct scx_softc *sc); 578 static void mii_statchg(struct ifnet *); 579 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 580 static int mii_readreg(device_t, int, int, uint16_t *); 581 static int mii_writereg(device_t, int, int, uint16_t); 582 static void phy_tick(void *); 583 static void dump_hwfeature(struct scx_softc *); 584 585 static void resetuengine(struct scx_softc *); 586 static void loaducode(struct scx_softc *); 587 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 588 589 static int get_mdioclk(uint32_t); 590 591 #define WAIT_FOR_SET(sc, reg, set) \ 592 wait_for_bits(sc, reg, set, ~0, 0) 593 #define WAIT_FOR_CLR(sc, reg, clr) \ 594 wait_for_bits(sc, reg, 0, clr, 0) 595 596 static int 597 wait_for_bits(struct scx_softc *sc, int reg, 598 uint32_t set, uint32_t clr, uint32_t fail) 599 { 600 uint32_t val; 601 int ntries; 602 603 for (ntries = 0; ntries < 1000; ntries++) { 604 val = CSR_READ(sc, reg); 605 if ((val & set) || !(val & clr)) 606 return 0; 607 if (val & fail) 608 return 1; 609 DELAY(1); 610 } 611 return 1; 612 } 613 614 /* GMAC register indirect access */ 615 static int 616 mac_read(struct scx_softc *sc, int reg) 617 { 618 619 CSR_WRITE(sc, MACCMD, reg | CMD_BUSY); 620 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY); 621 return CSR_READ(sc, MACDATA); 622 } 623 624 static void 625 mac_write(struct scx_softc *sc, int reg, int val) 626 { 627 628 CSR_WRITE(sc, MACDATA, val); 629 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY); 630 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY); 631 } 632 633 /* dig and decode "clock-frequency" value for a given clkname */ 634 static int 635 get_clk_freq(int phandle, const char *clkname) 636 { 637 u_int index, n, cells; 638 const u_int *p; 639 int err, len, resid; 640 unsigned int freq = 0; 641 642 err = fdtbus_get_index(phandle, "clock-names", clkname, &index); 643 if (err == -1) 644 return -1; 645 p = fdtbus_get_prop(phandle, "clocks", &len); 646 if (p == NULL) 647 return -1; 648 for (n = 0, resid = len; resid > 0; n++) { 649 const int cc_phandle = 650 fdtbus_get_phandle_from_native(be32toh(p[0])); 651 if (of_getprop_uint32(cc_phandle, "#clock-cells", &cells)) 652 return -1; 653 if (n == index) { 654 if (of_getprop_uint32(cc_phandle, 655 "clock-frequency", &freq)) 656 return -1; 657 return freq; 658 } 659 resid -= (cells + 1) * 4; 660 p += (cells + 1) * 4; 661 } 662 return -1; 663 } 664 665 #define ATTACH_DEBUG 1 666 667 static const struct device_compatible_entry compat_data[] = { 668 { .compat = "socionext,synquacer-netsec" }, 669 DEVICE_COMPAT_EOL 670 }; 671 static const struct device_compatible_entry compatible[] = { 672 { .compat = "SCX0001" }, 673 DEVICE_COMPAT_EOL 674 }; 675 676 static int 677 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 678 { 679 struct fdt_attach_args * const faa = aux; 680 681 return of_compatible_match(faa->faa_phandle, compat_data); 682 } 683 684 static void 685 scx_fdt_attach(device_t parent, device_t self, void *aux) 686 { 687 struct scx_softc * const sc = device_private(self); 688 struct fdt_attach_args * const faa = aux; 689 const int phandle = faa->faa_phandle; 690 bus_space_handle_t bsh; 691 bus_space_handle_t eebsh; 692 bus_addr_t addr[2]; 693 bus_size_t size[2]; 694 void *intrh; 695 char intrstr[128]; 696 int phy_phandle; 697 const char *phy_mode; 698 bus_addr_t phy_id; 699 long ref_clk; 700 701 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 702 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 703 aprint_error(": unable to map registers\n"); 704 return; 705 } 706 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 707 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) { 708 aprint_error(": unable to map device eeprom\n"); 709 goto fail; 710 } 711 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 712 aprint_error(": failed to decode interrupt\n"); 713 goto fail; 714 } 715 716 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 717 if (phy_mode == NULL) 718 aprint_error(": missing 'phy-mode' property\n"); 719 phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 720 if (phy_phandle == -1 721 || fdtbus_get_reg(phy_phandle, 0, &phy_id, NULL) != 0) 722 phy_id = MII_PHY_ANY; 723 ref_clk = get_clk_freq(phandle, "phy_ref_clk"); 724 if (ref_clk == -1) 725 ref_clk = 250 * 1000 * 1000; 726 727 #if ATTACH_DEBUG == 1 728 aprint_normal("\n"); 729 aprint_normal_dev(self, 730 "[FDT] phy mode %s, phy id %d, freq %ld\n", 731 phy_mode, (int)phy_id, ref_clk); 732 aprint_normal("%s", device_xname(self)); 733 #endif 734 735 intrh = fdtbus_intr_establish(phandle, 0, IPL_NET, 736 NOT_MP_SAFE, scx_intr, sc); 737 if (intrh == NULL) { 738 aprint_error(": couldn't establish interrupt\n"); 739 goto fail; 740 } 741 aprint_normal(" interrupt on %s", intrstr); 742 743 sc->sc_dev = self; 744 sc->sc_st = faa->faa_bst; 745 sc->sc_sh = bsh; 746 sc->sc_sz = size[0]; 747 sc->sc_eesh = eebsh; 748 sc->sc_eesz = size[1]; 749 sc->sc_ih = intrh; 750 sc->sc_dmat = faa->faa_dmat; 751 sc->sc_phandle = phandle; 752 sc->sc_phy_id = phy_id; 753 sc->sc_freq = ref_clk; 754 755 scx_attach_i(sc); 756 757 return; 758 fail: 759 if (sc->sc_eesz) 760 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 761 if (sc->sc_sz) 762 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 763 return; 764 } 765 766 static int 767 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 768 { 769 struct acpi_attach_args *aa = aux; 770 771 return acpi_compatible_match(aa, compatible); 772 } 773 774 #define HWFEA_DEBUG 1 775 776 static void 777 scx_acpi_attach(device_t parent, device_t self, void *aux) 778 { 779 struct scx_softc * const sc = device_private(self); 780 struct acpi_attach_args * const aa = aux; 781 ACPI_HANDLE handle = aa->aa_node->ad_handle; 782 bus_space_handle_t bsh, eebsh; 783 struct acpi_resources res; 784 struct acpi_mem *mem, *mem1; 785 struct acpi_irq *irq; 786 ACPI_INTEGER max_spd, max_frame, phy_id, phy_freq; 787 ACPI_STATUS rv; 788 void *intrh; 789 790 rv = acpi_resource_parse(self, handle, "_CRS", 791 &res, &acpi_resource_parse_ops_default); 792 if (ACPI_FAILURE(rv)) 793 return; 794 mem = acpi_res_mem(&res, 0); 795 irq = acpi_res_irq(&res, 0); 796 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 797 aprint_error(": incomplete crs resources\n"); 798 goto done; 799 } 800 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0, 801 &bsh) != 0) { 802 aprint_error(": unable to map registers\n"); 803 goto done; 804 } 805 mem1 = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 806 if (mem1 == NULL || mem1->ar_length == 0) { 807 aprint_error(": incomplete eeprom resources\n"); 808 goto fail_0; 809 } 810 if (bus_space_map(aa->aa_memt, mem1->ar_base, mem1->ar_length, 0, 811 &eebsh)) { 812 aprint_error(": unable to map device eeprom\n"); 813 goto fail_0; 814 } 815 rv = acpi_dsd_integer(handle, "max-speed", &max_spd); 816 if (ACPI_FAILURE(rv)) 817 max_spd = 1000; 818 rv = acpi_dsd_integer(handle, "max-frame-size", &max_frame); 819 if (ACPI_FAILURE(rv)) 820 max_frame = 2048; 821 rv = acpi_dsd_integer(handle, "phy-channel", &phy_id); 822 if (ACPI_FAILURE(rv)) 823 phy_id = MII_PHY_ANY; 824 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency", 825 &phy_freq); 826 if (ACPI_FAILURE(rv)) 827 phy_freq = 250 * 1000 * 1000; 828 829 #if ATTACH_DEBUG == 1 830 aprint_normal_dev(self, 831 "[ACPI] max-speed %d, phy id %d, freq %ld\n", 832 (int)max_spd, (int)phy_id, phy_freq); 833 aprint_normal("%s", device_xname(self)); 834 #endif 835 836 intrh = acpi_intr_establish(self, (uint64_t)(uintptr_t)handle, 837 IPL_NET, NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 838 if (intrh == NULL) { 839 aprint_error(": couldn't establish interrupt\n"); 840 goto fail_1; 841 } 842 843 sc->sc_dev = self; 844 sc->sc_st = aa->aa_memt; 845 sc->sc_sh = bsh; 846 sc->sc_sz = mem->ar_length; 847 sc->sc_eesh = eebsh; 848 sc->sc_eesz = mem1->ar_length; 849 sc->sc_ih = intrh; 850 sc->sc_dmat = 851 BUS_DMA_TAG_VALID(aa->aa_dmat64) ? aa->aa_dmat64 : aa->aa_dmat; 852 sc->sc_phy_id = (int)phy_id; 853 sc->sc_freq = phy_freq; 854 sc->sc_maxsize = max_frame; 855 856 scx_attach_i(sc); 857 done: 858 acpi_resource_cleanup(&res); 859 return; 860 fail_1: 861 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 862 fail_0: 863 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 864 acpi_resource_cleanup(&res); 865 return; 866 } 867 868 static void 869 scx_attach_i(struct scx_softc *sc) 870 { 871 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 872 struct mii_data * const mii = &sc->sc_mii; 873 struct ifmedia * const ifm = &mii->mii_media; 874 uint32_t which, dwimp, dwfea; 875 uint8_t enaddr[ETHER_ADDR_LEN]; 876 bus_dma_segment_t seg; 877 paddr_t p, q; 878 uint32_t csr; 879 int i, nseg, error = 0; 880 881 which = CSR_READ(sc, HWVER); /* Socionext version 5.xx */ 882 dwimp = mac_read(sc, GMACIMPL); /* DWC implementation XX.YY */ 883 dwfea = mac_read(sc, HWFEA); /* DWC feature bits */ 884 885 aprint_naive("\n"); 886 aprint_normal(": Socionext NetSec Gigabit Ethernet controller " 887 "%x.%x\n", which >> 16, which & 0xffff); 888 889 aprint_normal_dev(sc->sc_dev, 890 "DesignWare EMAC ver 0x%x (0x%x) hw feature %08x\n", 891 dwimp & 0xff, dwimp >> 8, dwfea); 892 dump_hwfeature(sc); 893 894 /* detected PHY type */ 895 sc->sc_miigmii = ((dwfea & __BITS(30,28) >> 28) == 0); 896 897 /* fetch MAC address in flash 0:7, stored in big endian order */ 898 csr = EE_READ(sc, 0x00); 899 enaddr[0] = csr >> 24; 900 enaddr[1] = csr >> 16; 901 enaddr[2] = csr >> 8; 902 enaddr[3] = csr; 903 csr = EE_READ(sc, 0x04); 904 enaddr[4] = csr >> 24; 905 enaddr[5] = csr >> 16; 906 aprint_normal_dev(sc->sc_dev, 907 "Ethernet address %s\n", ether_sprintf(enaddr)); 908 909 sc->sc_mdclk = get_mdioclk(sc->sc_freq) << GAR_CLK; /* 5:2 clk ratio */ 910 911 mii->mii_ifp = ifp; 912 mii->mii_readreg = mii_readreg; 913 mii->mii_writereg = mii_writereg; 914 mii->mii_statchg = mii_statchg; 915 916 sc->sc_ethercom.ec_mii = mii; 917 ifmedia_init(ifm, 0, ether_mediachange, scx_ifmedia_sts); 918 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 919 MII_OFFSET_ANY, MIIF_DOPAUSE); 920 if (LIST_FIRST(&mii->mii_phys) == NULL) { 921 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 922 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 923 } else 924 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 925 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 926 927 /* 928 * Allocate the control data structures, and create and load the 929 * DMA map for it. 930 */ 931 error = bus_dmamem_alloc(sc->sc_dmat, 932 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 933 if (error != 0) { 934 aprint_error_dev(sc->sc_dev, 935 "unable to allocate control data, error = %d\n", error); 936 goto fail_0; 937 } 938 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 939 sizeof(struct control_data), (void **)&sc->sc_control_data, 940 BUS_DMA_COHERENT); 941 if (error != 0) { 942 aprint_error_dev(sc->sc_dev, 943 "unable to map control data, error = %d\n", error); 944 goto fail_1; 945 } 946 error = bus_dmamap_create(sc->sc_dmat, 947 sizeof(struct control_data), 1, 948 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 949 if (error != 0) { 950 aprint_error_dev(sc->sc_dev, 951 "unable to create control data DMA map, " 952 "error = %d\n", error); 953 goto fail_2; 954 } 955 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 956 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 957 if (error != 0) { 958 aprint_error_dev(sc->sc_dev, 959 "unable to load control data DMA map, error = %d\n", 960 error); 961 goto fail_3; 962 } 963 for (i = 0; i < MD_TXQUEUELEN; i++) { 964 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 965 MD_NTXSEGS, MCLBYTES, 0, 0, 966 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 967 aprint_error_dev(sc->sc_dev, 968 "unable to create tx DMA map %d, error = %d\n", 969 i, error); 970 goto fail_4; 971 } 972 } 973 for (i = 0; i < MD_NRXDESC; i++) { 974 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 975 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 976 aprint_error_dev(sc->sc_dev, 977 "unable to create rx DMA map %d, error = %d\n", 978 i, error); 979 goto fail_5; 980 } 981 sc->sc_rxsoft[i].rxs_mbuf = NULL; 982 } 983 sc->sc_seg = seg; 984 sc->sc_nseg = nseg; 985 #if 0 986 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 987 #endif 988 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 989 ifp->if_softc = sc; 990 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 991 ifp->if_ioctl = scx_ioctl; 992 ifp->if_start = scx_start; 993 ifp->if_watchdog = scx_watchdog; 994 ifp->if_init = scx_init; 995 ifp->if_stop = scx_stop; 996 IFQ_SET_READY(&ifp->if_snd); 997 998 /* 802.1Q VLAN-sized frames, and 9000 jumbo frame are supported */ 999 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1000 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1001 1002 sc->sc_flowflags = 0; /* track PAUSE flow caps */ 1003 1004 if_attach(ifp); 1005 if_deferred_start_init(ifp, NULL); 1006 ether_ifattach(ifp, enaddr); 1007 1008 callout_init(&sc->sc_callout, 0); 1009 callout_setfunc(&sc->sc_callout, phy_tick, sc); 1010 1011 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1012 RND_TYPE_NET, RND_FLAG_DEFAULT); 1013 1014 resetuengine(sc); 1015 loaducode(sc); 1016 1017 /* feed NetSec descriptor array base addresses and timer value */ 1018 p = SCX_CDTXADDR(sc, 0); /* tdes array (ring#0) */ 1019 q = SCX_CDRXADDR(sc, 0); /* rdes array (ring#1) */ 1020 CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(p)); 1021 CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(p)); 1022 CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(q)); 1023 CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(q)); 1024 CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */ 1025 CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian */ 1026 CSR_WRITE(sc, DMACTL_TMR, sc->sc_freq / 1000000 - 1); 1027 1028 CSR_WRITE(sc, DMACTL_M2H, M2H_MODE_TRANS); 1029 CSR_WRITE(sc, PKTCTRL, MODENRM); /* change to use normal mode */ 1030 WAIT_FOR_SET(sc, MODE_TRANS, T2N_DONE); 1031 /* do { 1032 csr = CSR_READ(sc, MODE_TRANS); 1033 } while ((csr & T2N_DONE) == 0); */ 1034 1035 CSR_WRITE(sc, TXISR, ~0); /* clear pending emtpry/error irq */ 1036 CSR_WRITE(sc, xINTAE_CLR, ~0); /* disable tx / rx interrupts */ 1037 1038 return; 1039 1040 fail_5: 1041 for (i = 0; i < MD_NRXDESC; i++) { 1042 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1043 bus_dmamap_destroy(sc->sc_dmat, 1044 sc->sc_rxsoft[i].rxs_dmamap); 1045 } 1046 fail_4: 1047 for (i = 0; i < MD_TXQUEUELEN; i++) { 1048 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1049 bus_dmamap_destroy(sc->sc_dmat, 1050 sc->sc_txsoft[i].txs_dmamap); 1051 } 1052 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1053 fail_3: 1054 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1055 fail_2: 1056 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1057 sizeof(struct control_data)); 1058 fail_1: 1059 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 1060 fail_0: 1061 if (sc->sc_phandle) 1062 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 1063 else 1064 acpi_intr_disestablish(sc->sc_ih); 1065 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 1066 return; 1067 } 1068 1069 static void 1070 scx_reset(struct scx_softc *sc) 1071 { 1072 int loop = 0, busy; 1073 1074 mac_write(sc, GMACOMR, 0); 1075 mac_write(sc, GMACBMR, BMR_RST); 1076 do { 1077 DELAY(1); 1078 busy = mac_read(sc, GMACBMR) & BMR_RST; 1079 } while (++loop < 3000 && busy); 1080 mac_write(sc, GMACBMR, _BMR); 1081 mac_write(sc, GMACAFR, 0); 1082 } 1083 1084 static void 1085 scx_stop(struct ifnet *ifp, int disable) 1086 { 1087 struct scx_softc *sc = ifp->if_softc; 1088 uint32_t csr; 1089 1090 /* Stop the one second clock. */ 1091 callout_stop(&sc->sc_callout); 1092 1093 /* Down the MII. */ 1094 mii_down(&sc->sc_mii); 1095 1096 /* Mark the interface down and cancel the watchdog timer. */ 1097 ifp->if_flags &= ~IFF_RUNNING; 1098 ifp->if_timer = 0; 1099 1100 CSR_WRITE(sc, RXIE_CLR, ~0); 1101 CSR_WRITE(sc, TXIE_CLR, ~0); 1102 CSR_WRITE(sc, xINTAE_CLR, ~0); 1103 CSR_WRITE(sc, TXISR, ~0); 1104 CSR_WRITE(sc, RXISR, ~0); 1105 1106 csr = mac_read(sc, GMACOMR); 1107 mac_write(sc, GMACOMR, csr &~ (OMR_SR | OMR_ST)); 1108 } 1109 1110 static int 1111 scx_init(struct ifnet *ifp) 1112 { 1113 struct scx_softc *sc = ifp->if_softc; 1114 const uint8_t *ea = CLLADDR(ifp->if_sadl); 1115 uint32_t csr; 1116 int i, error; 1117 1118 /* Cancel pending I/O. */ 1119 scx_stop(ifp, 0); 1120 1121 /* Reset the chip to a known state. */ 1122 scx_reset(sc); 1123 1124 /* build sane Tx */ 1125 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC); 1126 sc->sc_txdescs[MD_NTXDESC - 1].t0 = T0_LD; /* tie off the ring */ 1127 SCX_CDTXSYNC(sc, 0, MD_NTXDESC, 1128 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1129 sc->sc_txfree = MD_NTXDESC; 1130 sc->sc_txnext = 0; 1131 for (i = 0; i < MD_TXQUEUELEN; i++) 1132 sc->sc_txsoft[i].txs_mbuf = NULL; 1133 sc->sc_txsfree = MD_TXQUEUELEN; 1134 sc->sc_txsnext = 0; 1135 sc->sc_txsdirty = 0; 1136 1137 /* load Rx descriptors with fresh mbuf */ 1138 for (i = 0; i < MD_NRXDESC; i++) { 1139 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 1140 if ((error = add_rxbuf(sc, i)) != 0) { 1141 aprint_error_dev(sc->sc_dev, 1142 "unable to allocate or map rx " 1143 "buffer %d, error = %d\n", 1144 i, error); 1145 rxdrain(sc); 1146 goto out; 1147 } 1148 } 1149 else 1150 SCX_INIT_RXDESC(sc, i); 1151 } 1152 sc->sc_rxdescs[MD_NRXDESC - 1].r0 = R0_LD; /* tie off the ring */ 1153 sc->sc_rxptr = 0; 1154 1155 /* set my address in perfect match slot 0. little endian order */ 1156 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 1157 mac_write(sc, GMACMAL0, csr); 1158 csr = (ea[5] << 8) | ea[4]; 1159 mac_write(sc, GMACMAH0, csr); 1160 1161 /* accept multicast frame or run promisc mode */ 1162 scx_set_rcvfilt(sc); 1163 1164 /* set current media */ 1165 if ((error = ether_mediachange(ifp)) != 0) 1166 goto out; 1167 1168 CSR_WRITE(sc, DESC_SRST, 01); 1169 WAIT_FOR_CLR(sc, DESC_SRST, 01); 1170 1171 CSR_WRITE(sc, DESC_INIT, 01); 1172 WAIT_FOR_CLR(sc, DESC_INIT, 01); 1173 1174 /* feed local memory descriptor array base addresses */ 1175 mac_write(sc, GMACRDLA, _RDLA); /* GMAC rdes store */ 1176 mac_write(sc, GMACTDLA, _TDLA); /* GMAC tdes store */ 1177 1178 CSR_WRITE(sc, FLOWTHR, (48<<16) | 36); /* pause|resume threshold */ 1179 mac_write(sc, GMACFCR, 256 << 16); /* 31:16 pause value */ 1180 1181 CSR_WRITE(sc, INTF_SEL, sc->sc_miigmii ? INTF_GMII : INTF_RGMII); 1182 1183 CSR_WRITE(sc, RXCOALESC, 8); /* Rx coalesce bound */ 1184 CSR_WRITE(sc, TXCOALESC, 8); /* Tx coalesce bound */ 1185 CSR_WRITE(sc, RCLSCTIME, 500|(1U<<31)); /* Rx co. guard time usec */ 1186 CSR_WRITE(sc, TCLSCTIME, 500|(1U<<31)); /* Tx co. guard time usec */ 1187 1188 CSR_WRITE(sc, RXIE_SET, RXI_RC_ERR | RXI_PKTCNT | RXI_TMREXP); 1189 CSR_WRITE(sc, TXIE_SET, TXI_TR_ERR | TXI_TXDONE | TXI_TMREXP); 1190 CSR_WRITE(sc, xINTAE_SET, IRQ_RX | IRQ_TX); 1191 #if 1 1192 /* clear event counters, auto-zero after every read */ 1193 mac_write(sc, GMACEVCTL, EVC_CR | EVC_ROR); 1194 #endif 1195 /* kick to start GMAC engine */ 1196 csr = mac_read(sc, GMACOMR); 1197 mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST); 1198 1199 ifp->if_flags |= IFF_RUNNING; 1200 1201 /* start one second timer */ 1202 callout_schedule(&sc->sc_callout, hz); 1203 out: 1204 return error; 1205 } 1206 1207 static int 1208 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1209 { 1210 struct scx_softc *sc = ifp->if_softc; 1211 struct ifreq *ifr = (struct ifreq *)data; 1212 struct ifmedia *ifm = &sc->sc_mii.mii_media; 1213 int s, error; 1214 1215 s = splnet(); 1216 1217 switch (cmd) { 1218 case SIOCSIFMEDIA: 1219 /* Flow control requires full-duplex mode. */ 1220 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1221 (ifr->ifr_media & IFM_FDX) == 0) 1222 ifr->ifr_media &= ~IFM_ETH_FMASK; 1223 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1224 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1225 /* We can do both TXPAUSE and RXPAUSE. */ 1226 ifr->ifr_media |= 1227 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1228 } 1229 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1230 } 1231 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 1232 break; 1233 default: 1234 error = ether_ioctl(ifp, cmd, data); 1235 if (error != ENETRESET) 1236 break; 1237 error = 0; 1238 if (cmd == SIOCSIFCAP) 1239 error = if_init(ifp); 1240 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1241 ; 1242 else if (ifp->if_flags & IFF_RUNNING) { 1243 /* 1244 * Multicast list has changed; set the hardware filter 1245 * accordingly. 1246 */ 1247 scx_set_rcvfilt(sc); 1248 } 1249 break; 1250 } 1251 1252 splx(s); 1253 return error; 1254 } 1255 1256 static uint32_t 1257 bit_reverse_32(uint32_t x) 1258 { 1259 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 1260 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 1261 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 1262 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 1263 return (x >> 16) | (x << 16); 1264 } 1265 1266 #define MCAST_DEBUG 0 1267 1268 static void 1269 scx_set_rcvfilt(struct scx_softc *sc) 1270 { 1271 struct ethercom * const ec = &sc->sc_ethercom; 1272 struct ifnet * const ifp = &ec->ec_if; 1273 struct ether_multistep step; 1274 struct ether_multi *enm; 1275 uint32_t mchash[2]; /* 2x 32 = 64 bit */ 1276 uint32_t csr, crc; 1277 int i; 1278 1279 csr = mac_read(sc, GMACAFR); 1280 csr &= ~(AFR_PR | AFR_PM | AFR_MHTE | AFR_HPF); 1281 mac_write(sc, GMACAFR, csr); 1282 1283 /* clear 15 entry supplemental perfect match filter */ 1284 for (i = 1; i < 16; i++) 1285 mac_write(sc, GMACMAH(i), 0); 1286 /* build 64 bit multicast hash filter */ 1287 crc = mchash[1] = mchash[0] = 0; 1288 1289 ETHER_LOCK(ec); 1290 if (ifp->if_flags & IFF_PROMISC) { 1291 ec->ec_flags |= ETHER_F_ALLMULTI; 1292 ETHER_UNLOCK(ec); 1293 /* run promisc. mode */ 1294 csr |= AFR_PR; 1295 goto update; 1296 } 1297 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1298 ETHER_FIRST_MULTI(step, ec, enm); 1299 i = 1; /* slot 0 is occupied */ 1300 while (enm != NULL) { 1301 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1302 /* 1303 * We must listen to a range of multicast addresses. 1304 * For now, just accept all multicasts, rather than 1305 * trying to set only those filter bits needed to match 1306 * the range. (At this time, the only use of address 1307 * ranges is for IP multicast routing, for which the 1308 * range is big enough to require all bits set.) 1309 */ 1310 ec->ec_flags |= ETHER_F_ALLMULTI; 1311 ETHER_UNLOCK(ec); 1312 /* accept all multi */ 1313 csr |= AFR_PM; 1314 goto update; 1315 } 1316 #if MCAST_DEBUG == 1 1317 aprint_normal_dev(sc->sc_dev, "[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 1318 #endif 1319 if (i < 16) { 1320 /* use 15 entry perfect match filter */ 1321 uint32_t addr; 1322 uint8_t *ep = enm->enm_addrlo; 1323 addr = (ep[3] << 24) | (ep[2] << 16) 1324 | (ep[1] << 8) | ep[0]; 1325 mac_write(sc, GMACMAL(i), addr); 1326 addr = (ep[5] << 8) | ep[4]; 1327 mac_write(sc, GMACMAH(i), addr | 1U<<31); 1328 } else { 1329 /* use hash table when too many */ 1330 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1331 crc = bit_reverse_32(~crc); 1332 /* 1(31) 5(30:26) bit sampling */ 1333 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 1334 } 1335 ETHER_NEXT_MULTI(step, enm); 1336 i++; 1337 } 1338 ETHER_UNLOCK(ec); 1339 if (crc) 1340 csr |= AFR_MHTE; /* use mchash[] */ 1341 csr |= AFR_HPF; /* use perfect match as well */ 1342 update: 1343 mac_write(sc, GMACMHTH, mchash[1]); 1344 mac_write(sc, GMACMHTL, mchash[0]); 1345 mac_write(sc, GMACAFR, csr); 1346 return; 1347 } 1348 1349 static void 1350 scx_start(struct ifnet *ifp) 1351 { 1352 struct scx_softc *sc = ifp->if_softc; 1353 struct mbuf *m0; 1354 struct scx_txsoft *txs; 1355 bus_dmamap_t dmamap; 1356 int error, nexttx, lasttx, ofree, seg; 1357 uint32_t tdes0; 1358 1359 if ((ifp->if_flags & IFF_RUNNING) == 0) 1360 return; 1361 1362 /* Remember the previous number of free descriptors. */ 1363 ofree = sc->sc_txfree; 1364 /* 1365 * Loop through the send queue, setting up transmit descriptors 1366 * until we drain the queue, or use up all available transmit 1367 * descriptors. 1368 */ 1369 for (;;) { 1370 IFQ_POLL(&ifp->if_snd, m0); 1371 if (m0 == NULL) 1372 break; 1373 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1374 txreap(sc); 1375 if (sc->sc_txsfree == 0) 1376 break; 1377 } 1378 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1379 dmamap = txs->txs_dmamap; 1380 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1381 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1382 if (error) { 1383 if (error == EFBIG) { 1384 aprint_error_dev(sc->sc_dev, 1385 "Tx packet consumes too many " 1386 "DMA segments, dropping...\n"); 1387 IFQ_DEQUEUE(&ifp->if_snd, m0); 1388 m_freem(m0); 1389 if_statinc_ref(ifp, if_oerrors); 1390 continue; 1391 } 1392 /* Short on resources, just stop for now. */ 1393 break; 1394 } 1395 if (dmamap->dm_nsegs > sc->sc_txfree) { 1396 /* 1397 * Not enough free descriptors to transmit this 1398 * packet. We haven't committed anything yet, 1399 * so just unload the DMA map, put the packet 1400 * back on the queue, and punt. 1401 */ 1402 bus_dmamap_unload(sc->sc_dmat, dmamap); 1403 break; 1404 } 1405 1406 IFQ_DEQUEUE(&ifp->if_snd, m0); 1407 /* 1408 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1409 */ 1410 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1411 BUS_DMASYNC_PREWRITE); 1412 1413 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1414 lasttx = -1; 1415 for (nexttx = sc->sc_txnext, seg = 0; 1416 seg < dmamap->dm_nsegs; 1417 seg++, nexttx = MD_NEXTTX(nexttx)) { 1418 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1419 bus_addr_t p = dmamap->dm_segs[seg].ds_addr; 1420 bus_size_t z = dmamap->dm_segs[seg].ds_len; 1421 /* 1422 * If this is the first descriptor we're 1423 * enqueueing, don't set the OWN bit just 1424 * yet. That could cause a race condition. 1425 * We'll do it below. 1426 */ 1427 tdes->t3 = htole32(z); 1428 tdes->t2 = htole32(BUS_ADDR_LO32(p)); 1429 tdes->t1 = htole32(BUS_ADDR_HI32(p)); 1430 tdes->t0 &= htole32(T0_LD); 1431 tdes->t0 |= htole32(tdes0 | 1432 (15 << T0_TDRID) | T0_PT | 1433 sc->sc_t0cotso | T0_TRS); 1434 tdes0 = T0_OWN; /* 2nd and other segments */ 1435 /* NB; t0 DRID field contains zero */ 1436 lasttx = nexttx; 1437 } 1438 1439 /* HW lacks of per-frame xmit done interrupt control */ 1440 1441 /* Write deferred 1st segment T0_OWN at the final stage */ 1442 sc->sc_txdescs[lasttx].t0 |= htole32(T0_LS); 1443 sc->sc_txdescs[sc->sc_txnext].t0 |= htole32(T0_FS | T0_OWN); 1444 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1445 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1446 1447 /* submit one frame to xmit */ 1448 CSR_WRITE(sc, TXSUBMIT, 1); 1449 1450 txs->txs_mbuf = m0; 1451 txs->txs_firstdesc = sc->sc_txnext; 1452 txs->txs_lastdesc = lasttx; 1453 txs->txs_ndesc = dmamap->dm_nsegs; 1454 sc->sc_txfree -= txs->txs_ndesc; 1455 sc->sc_txnext = nexttx; 1456 sc->sc_txsfree--; 1457 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1458 /* 1459 * Pass the packet to any BPF listeners. 1460 */ 1461 bpf_mtap(ifp, m0, BPF_D_OUT); 1462 } 1463 if (sc->sc_txfree != ofree) { 1464 /* Set a watchdog timer in case the chip flakes out. */ 1465 ifp->if_timer = 5; 1466 } 1467 } 1468 1469 #define EVENT_DEBUG 1 1470 1471 static void 1472 scx_watchdog(struct ifnet *ifp) 1473 { 1474 struct scx_softc *sc = ifp->if_softc; 1475 1476 /* 1477 * Since we're not interrupting every packet, sweep 1478 * up before we report an error. 1479 */ 1480 txreap(sc); 1481 1482 if (sc->sc_txfree != MD_NTXDESC) { 1483 aprint_error_dev(sc->sc_dev, 1484 "device timeout (txfree %d txsfree %d txnext %d)\n", 1485 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1486 if_statinc(ifp, if_oerrors); 1487 #if EVENT_DEBUG == 1 1488 aprint_error_dev(sc->sc_dev, 1489 "tx frames %d, octects %d, bcast %d, mcast %d\n", 1490 mac_read(sc, GMACEVCNT(1)), 1491 mac_read(sc, GMACEVCNT(0)), 1492 mac_read(sc, GMACEVCNT(2)), 1493 mac_read(sc, GMACEVCNT(3))); 1494 aprint_error_dev(sc->sc_dev, 1495 "rx frames %d, octects %d, bcast %d, mcast %d\n", 1496 mac_read(sc, GMACEVCNT(27)), 1497 mac_read(sc, GMACEVCNT(28)), 1498 mac_read(sc, GMACEVCNT(30)), 1499 mac_read(sc, GMACEVCNT(31))); 1500 aprint_error_dev(sc->sc_dev, 1501 "current tdes addr %x, buf addr %x\n", 1502 mac_read(sc, 0x1048), mac_read(sc, 0x1050)); 1503 aprint_error_dev(sc->sc_dev, 1504 "current rdes addr %x, buf addr %x\n", 1505 mac_read(sc, 0x104c), mac_read(sc, 0x1054)); 1506 #endif 1507 /* Reset the interface. */ 1508 scx_init(ifp); 1509 } 1510 1511 scx_start(ifp); 1512 } 1513 1514 static int 1515 scx_intr(void *arg) 1516 { 1517 struct scx_softc *sc = arg; 1518 uint32_t enable, status; 1519 1520 status = CSR_READ(sc, xINTSR); /* not W1C */ 1521 enable = CSR_READ(sc, xINTAEN); 1522 if ((status & enable) == 0) 1523 return 0; 1524 if (status & (IRQ_TX | IRQ_RX)) { 1525 CSR_WRITE(sc, xINTAE_CLR, (IRQ_TX | IRQ_RX)); 1526 1527 status = CSR_READ(sc, RXISR); 1528 CSR_WRITE(sc, RXISR, status); 1529 if (status & RXI_RC_ERR) 1530 aprint_error_dev(sc->sc_dev, "Rx error\n"); 1531 if (status & (RXI_PKTCNT | RXI_TMREXP)) { 1532 rxfill(sc); 1533 (void)CSR_READ(sc, RXAVAILCNT); /* clear RXI_PKTCNT */ 1534 } 1535 1536 status = CSR_READ(sc, TXISR); 1537 CSR_WRITE(sc, TXISR, status); 1538 if (status & TXI_TR_ERR) 1539 aprint_error_dev(sc->sc_dev, "Tx error\n"); 1540 if (status & (TXI_TXDONE | TXI_TMREXP)) { 1541 txreap(sc); 1542 (void)CSR_READ(sc, TXDONECNT); /* clear TXI_TXDONE */ 1543 } 1544 1545 CSR_WRITE(sc, xINTAE_SET, (IRQ_TX | IRQ_RX)); 1546 } 1547 return 1; 1548 } 1549 1550 static void 1551 txreap(struct scx_softc *sc) 1552 { 1553 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1554 struct scx_txsoft *txs; 1555 uint32_t txstat; 1556 int i; 1557 1558 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1559 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1560 txs = &sc->sc_txsoft[i]; 1561 1562 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1563 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1564 1565 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].t0); 1566 if (txstat & T0_OWN) /* desc is still in use */ 1567 break; 1568 1569 /* There is no way to tell transmission status per frame */ 1570 1571 if_statinc(ifp, if_opackets); 1572 1573 sc->sc_txfree += txs->txs_ndesc; 1574 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1575 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1576 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1577 m_freem(txs->txs_mbuf); 1578 txs->txs_mbuf = NULL; 1579 } 1580 sc->sc_txsdirty = i; 1581 if (sc->sc_txsfree == MD_TXQUEUELEN) 1582 ifp->if_timer = 0; 1583 } 1584 1585 static void 1586 rxfill(struct scx_softc *sc) 1587 { 1588 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1589 struct scx_rxsoft *rxs; 1590 struct mbuf *m; 1591 uint32_t rxstat, rlen; 1592 int i; 1593 1594 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1595 SCX_CDRXSYNC(sc, i, 1596 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1597 1598 rxstat = le32toh(sc->sc_rxdescs[i].r0); 1599 if (rxstat & R0_OWN) /* desc is left empty */ 1600 break; 1601 1602 /* received frame length in R3 31:16 */ 1603 rlen = le32toh(sc->sc_rxdescs[i].r3) >> 16; 1604 1605 /* R0_FS | R0_LS must have been marked for this desc */ 1606 rxs = &sc->sc_rxsoft[i]; 1607 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1608 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1609 1610 /* dispense new storage to receive frame */ 1611 m = rxs->rxs_mbuf; 1612 if (add_rxbuf(sc, i) != 0) { 1613 if_statinc(ifp, if_ierrors); /* resource shortage */ 1614 SCX_INIT_RXDESC(sc, i); /* then reuse */ 1615 bus_dmamap_sync(sc->sc_dmat, 1616 rxs->rxs_dmamap, 0, 1617 rxs->rxs_dmamap->dm_mapsize, 1618 BUS_DMASYNC_PREREAD); 1619 continue; 1620 } 1621 /* complete mbuf */ 1622 m_set_rcvif(m, ifp); 1623 m->m_pkthdr.len = m->m_len = rlen; 1624 m->m_flags |= M_HASFCS; 1625 if (rxstat & R0_CSUM) { 1626 uint32_t csum = M_CSUM_IPv4; 1627 if (rxstat & R0_CERR) 1628 csum |= M_CSUM_IPv4_BAD; 1629 m->m_pkthdr.csum_flags |= csum; 1630 } 1631 /* and pass to upper layer */ 1632 if_percpuq_enqueue(ifp->if_percpuq, m); 1633 } 1634 sc->sc_rxptr = i; 1635 } 1636 1637 static int 1638 add_rxbuf(struct scx_softc *sc, int i) 1639 { 1640 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1641 struct mbuf *m; 1642 int error; 1643 1644 MGETHDR(m, M_DONTWAIT, MT_DATA); 1645 if (m == NULL) 1646 return ENOBUFS; 1647 MCLGET(m, M_DONTWAIT); 1648 if ((m->m_flags & M_EXT) == 0) { 1649 m_freem(m); 1650 return ENOBUFS; 1651 } 1652 if (rxs->rxs_mbuf != NULL) 1653 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1654 rxs->rxs_mbuf = m; 1655 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1656 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1657 if (error) { 1658 aprint_error_dev(sc->sc_dev, 1659 "can't load rx DMA map %d, error = %d\n", i, error); 1660 panic("add_rxbuf"); 1661 } 1662 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1663 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1664 SCX_INIT_RXDESC(sc, i); 1665 1666 return 0; 1667 } 1668 1669 static void 1670 rxdrain(struct scx_softc *sc) 1671 { 1672 struct scx_rxsoft *rxs; 1673 int i; 1674 1675 for (i = 0; i < MD_NRXDESC; i++) { 1676 rxs = &sc->sc_rxsoft[i]; 1677 if (rxs->rxs_mbuf != NULL) { 1678 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1679 m_freem(rxs->rxs_mbuf); 1680 rxs->rxs_mbuf = NULL; 1681 } 1682 } 1683 } 1684 1685 #define LINK_DEBUG 0 1686 1687 static void 1688 mii_statchg(struct ifnet *ifp) 1689 { 1690 struct scx_softc *sc = ifp->if_softc; 1691 struct mii_data *mii = &sc->sc_mii; 1692 const int Mbps[4] = { 10, 100, 1000, 0 }; 1693 uint32_t miisr, mcr, fcr; 1694 int spd; 1695 1696 /* decode MIISR register value */ 1697 miisr = mac_read(sc, GMACMIISR); 1698 spd = Mbps[(miisr & MIISR_SPD) >> 1]; 1699 #if LINK_DEBUG == 1 1700 static uint32_t oldmiisr = 0; 1701 if (miisr != oldmiisr) { 1702 printf("MII link status (0x%x) %s", 1703 miisr, (miisr & MIISR_LUP) ? "up" : "down"); 1704 if (miisr & MIISR_LUP) { 1705 printf(" spd%d", spd); 1706 if (miisr & MIISR_FDX) 1707 printf(",full-duplex"); 1708 } 1709 printf("\n"); 1710 } 1711 #endif 1712 /* Get flow control negotiation result. */ 1713 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1714 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1715 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1716 1717 /* Adjust speed 1000/100/10. */ 1718 mcr = mac_read(sc, GMACMCR) &~ (MCR_PS | MCR_FES); 1719 if (sc->sc_miigmii) { 1720 if (spd != 1000) 1721 mcr |= MCR_PS; 1722 } else { 1723 if (spd == 100) 1724 mcr |= MCR_FES; 1725 } 1726 mcr |= MCR_CST | MCR_JE; 1727 if (sc->sc_miigmii == 0) 1728 mcr |= MCR_IBN; 1729 1730 /* Adjust duplexity and PAUSE flow control. */ 1731 mcr &= ~MCR_USEFDX; 1732 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1733 if (miisr & MIISR_FDX) { 1734 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1735 fcr |= FCR_TFE; 1736 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1737 fcr |= FCR_RFE; 1738 mcr |= MCR_USEFDX; 1739 } 1740 mac_write(sc, GMACMCR, mcr); 1741 mac_write(sc, GMACFCR, fcr); 1742 #if LINK_DEBUG == 1 1743 if (miisr != oldmiisr) { 1744 printf("%ctxfe, %crxfe\n", 1745 (fcr & FCR_TFE) ? '+' : '-', 1746 (fcr & FCR_RFE) ? '+' : '-'); 1747 } 1748 oldmiisr = miisr; 1749 #endif 1750 } 1751 1752 static void 1753 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1754 { 1755 struct scx_softc *sc = ifp->if_softc; 1756 struct mii_data *mii = &sc->sc_mii; 1757 1758 mii_pollstat(mii); 1759 ifmr->ifm_status = mii->mii_media_status; 1760 ifmr->ifm_active = sc->sc_flowflags | 1761 (mii->mii_media_active & ~IFM_ETH_FMASK); 1762 } 1763 1764 static int 1765 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1766 { 1767 struct scx_softc *sc = device_private(self); 1768 uint32_t miia; 1769 int ntries; 1770 1771 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1772 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1773 for (ntries = 0; ntries < 1000; ntries++) { 1774 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1775 goto unbusy; 1776 DELAY(1); 1777 } 1778 return ETIMEDOUT; 1779 unbusy: 1780 *val = mac_read(sc, GMACGDR); 1781 return 0; 1782 } 1783 1784 static int 1785 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1786 { 1787 struct scx_softc *sc = device_private(self); 1788 uint32_t miia; 1789 uint16_t dummy; 1790 int ntries; 1791 1792 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1793 mac_write(sc, GMACGDR, val); 1794 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1795 for (ntries = 0; ntries < 1000; ntries++) { 1796 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0) 1797 goto unbusy; 1798 DELAY(1); 1799 } 1800 return ETIMEDOUT; 1801 unbusy: 1802 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1803 return 0; 1804 } 1805 1806 static void 1807 phy_tick(void *arg) 1808 { 1809 struct scx_softc *sc = arg; 1810 struct mii_data *mii = &sc->sc_mii; 1811 int s; 1812 1813 s = splnet(); 1814 mii_tick(mii); 1815 splx(s); 1816 #ifdef GMAC_EVENT_COUNTERS 1817 /* 80 event counters exist */ 1818 #endif 1819 callout_schedule(&sc->sc_callout, hz); 1820 } 1821 1822 static void 1823 resetuengine(struct scx_softc *sc) 1824 { 1825 1826 if (CSR_READ(sc, CORESTAT) == 0) { 1827 /* make sure to stop */ 1828 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP); 1829 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP); 1830 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP); 1831 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP); 1832 } 1833 CSR_WRITE(sc, SWRESET, 0); /* reset operation */ 1834 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */ 1835 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS); 1836 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS)); 1837 } 1838 1839 #define UCODE_DEBUG 0 1840 1841 /* 1842 * 3 independent uengines exist to process host2media, media2host and 1843 * packet data flows. 1844 */ 1845 static void 1846 loaducode(struct scx_softc *sc) 1847 { 1848 uint32_t up, lo, sz; 1849 uint64_t addr; 1850 int err; 1851 1852 CSR_WRITE(sc, xINTSR, IRQ_UCODE); 1853 1854 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1855 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1856 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1857 sz *= 4; 1858 addr = ((uint64_t)up << 32) | lo; 1859 injectucode(sc, UCODE_H2M, (bus_addr_t)addr, (bus_size_t)sz); 1860 #if UCODE_DEBUG == 1 1861 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz); 1862 #endif 1863 1864 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1865 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1866 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1867 sz *= 4; 1868 addr = ((uint64_t)up << 32) | lo; 1869 injectucode(sc, UCODE_M2H, (bus_addr_t)addr, (bus_size_t)sz); 1870 #if UCODE_DEBUG == 1 1871 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz); 1872 #endif 1873 1874 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1875 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1876 sz *= 4; 1877 injectucode(sc, UCODE_PKT, (bus_addr_t)lo, (bus_size_t)sz); 1878 #if UCODE_DEBUG == 1 1879 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz); 1880 #endif 1881 1882 CSR_WRITE(sc, CORESTAT, 0); 1883 err = WAIT_FOR_SET(sc, xINTSR, IRQ_UCODE); 1884 if (err) { 1885 aprint_error_dev(sc->sc_dev, "uengine start failed\n"); 1886 } 1887 CSR_WRITE(sc, xINTSR, IRQ_UCODE); 1888 } 1889 1890 static void 1891 injectucode(struct scx_softc *sc, int port, 1892 bus_addr_t addr, bus_size_t size) 1893 { 1894 bus_space_handle_t bsh; 1895 bus_size_t off; 1896 uint32_t ucode; 1897 1898 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1899 aprint_error_dev(sc->sc_dev, 1900 "eeprom map failure for ucode port 0x%x\n", port); 1901 return; 1902 } 1903 for (off = 0; off < size; off += 4) { 1904 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1905 CSR_WRITE(sc, port, ucode); 1906 } 1907 bus_space_unmap(sc->sc_st, bsh, size); 1908 } 1909 1910 /* GAR 5:2 MDIO frequency selection */ 1911 static int 1912 get_mdioclk(uint32_t freq) 1913 { 1914 1915 freq /= 1000 * 1000; 1916 if (freq < 35) 1917 return GAR_MDIO_25_35MHZ; 1918 if (freq < 60) 1919 return GAR_MDIO_35_60MHZ; 1920 if (freq < 100) 1921 return GAR_MDIO_60_100MHZ; 1922 if (freq < 150) 1923 return GAR_MDIO_100_150MHZ; 1924 if (freq < 250) 1925 return GAR_MDIO_150_250MHZ; 1926 return GAR_MDIO_250_300MHZ; 1927 } 1928 1929 #define HWFEA_DEBUG 1 1930 1931 static void 1932 dump_hwfeature(struct scx_softc *sc) 1933 { 1934 #if HWFEA_DEBUG == 1 1935 struct { 1936 uint32_t bit; 1937 const char *des; 1938 } field[] = { 1939 { 27, "SA/VLAN insertion replacement enabled" }, 1940 { 26, "flexible PPS enabled" }, 1941 { 25, "time stamping with internal system enabled" }, 1942 { 24, "alternate/enhanced descriptor enabled" }, 1943 { 19, "rx FIFO >2048 enabled" }, 1944 { 18, "type 2 IP checksum offload enabled" }, 1945 { 17, "type 1 IP checksum offload enabled" }, 1946 { 16, "Tx checksum offload enabled" }, 1947 { 15, "AV feature enabled" }, 1948 { 14, "EEE energy save feature enabled" }, 1949 { 13, "1588-2008 version 2 advanced feature enabled" }, 1950 { 12, "only 1588-2002 version 1 feature enabled" }, 1951 { 11, "RMON event counter enabled" }, 1952 { 10, "PMT magic packet enabled" }, 1953 { 9, "PMT remote wakeup enabled" }, 1954 { 8, "MDIO enabled", }, 1955 { 7, "L3/L4 filter enabled" }, 1956 { 6, "TBI/SGMII/RTBI support enabled" }, 1957 { 5, "supplimental MAC address enabled" }, 1958 { 4, "receive hash filter enabled" }, 1959 { 3, "hash size is expanded" }, 1960 { 2, "Half Duplex enabled" }, 1961 { 1, "1000 Mbps enabled" }, 1962 { 0, "10/100 Mbps enabled" }, 1963 }; 1964 const char *nameofmii[] = { 1965 "GMII or MII", 1966 "RGMII", 1967 "SGMII", 1968 "TBI", 1969 "RMII", 1970 "RTBI", 1971 "SMII", 1972 "RevMII" 1973 }; 1974 uint32_t hwfea, mtype, txchan, rxchan; 1975 1976 hwfea = CSR_READ(sc, HWFEA); 1977 mtype = (hwfea & __BITS(30,28)) >> 28; 1978 aprint_normal("HWFEA 0x%08x\n", hwfea); 1979 aprint_normal("%s <30:28>\n", nameofmii[mtype]); 1980 for (unsigned i = 0; i < __arraycount(field); i++) { 1981 if ((hwfea & (1U << field[i].bit)) == 0) 1982 continue; 1983 aprint_normal("%s <%d>\n", field[i].des, field[i].bit); 1984 } 1985 if ((txchan = (hwfea & __BITS(23,22)) >> 22) != 0) 1986 aprint_normal("+%d tx channel available <23,22>\n", txchan); 1987 if ((rxchan = (hwfea & __BITS(21,20)) >> 20) != 0) 1988 aprint_normal("+%d rx channel available <21:20>\n", rxchan); 1989 return; 1990 #endif 1991 } 1992
Indexes created Fri Sep 26 20:09:58 GMT 2025