if_scx.c revision 1.7
1 /* $NetBSD: if_scx.c,v 1.7 2020/03/24 02:31:59 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 32 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~31 are for supplimental MAC addresses. Independently enabled 47 * for use. Good to catch multicast. Byte-wise selective match available. 48 * Use to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - The size of multicast hash filter store is unknown. Might be 256 bit. 50 * - Socionext/Linaro "NetSec" code makes many cut shorts. Some constants 51 * are left unexplained. The values should be handled via external 52 * controls like FDT descriptions. Fortunately, Intel/Altera CycloneV PDFs 53 * describe every detail of "such the instance of" DW EMAC IP and 54 * most of them are likely applicable to SC2A11 GbE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.7 2020/03/24 02:31:59 nisimura Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/bus.h> 62 #include <sys/intr.h> 63 #include <sys/device.h> 64 #include <sys/callout.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/errno.h> 68 #include <sys/rndsource.h> 69 #include <sys/kernel.h> 70 #include <sys/systm.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_dl.h> 75 #include <net/if_ether.h> 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <net/bpf.h> 79 80 #include <dev/fdt/fdtvar.h> 81 #include <dev/acpi/acpireg.h> 82 #include <dev/acpi/acpivar.h> 83 #include <dev/acpi/acpi_intr.h> 84 85 #define SWRESET 0x104 86 #define COMINIT 0x120 87 #define INTRST 0x200 88 #define IRQ_RX (1U<<1) 89 #define IRQ_TX (1U<<0) 90 #define INTREN 0x204 91 #define INTR_SET 0x234 92 #define INTR_CLR 0x238 93 #define TXINTST 0x400 94 #define TXINTEN 0x404 95 #define TXINT_SET 0x428 96 #define TXINT_CLR 0x42c 97 #define TXI_NTOWNR (1U<<17) 98 #define TXI_TR_ERR (1U<<16) 99 #define TXI_TXDONE (1U<<15) 100 #define TXI_TMREXP (1U<<14) 101 #define RXINTST 0x440 102 #define RXINTEN 0x444 103 #define RXINT_SET 0x468 104 #define RXINT_CLR 0x46c 105 #define RXI_RC_ERR (1U<<16) 106 #define RXI_PKTCNT (1U<<15) 107 #define RXI_TMREXP (1U<<14) 108 #define TXTIMER 0x41c 109 #define RXTIMER 0x45c 110 #define TXCOUNT 0x410 111 #define RXCOUNT 0x454 112 #define H2MENG 0x210 /* DMAC host2media ucode port */ 113 #define M2HENG 0x21c /* DMAC media2host ucode port */ 114 #define PKTENG 0x0d0 /* packet engine ucode port */ 115 #define HWVER0 0x22c 116 #define HWVER1 0x230 117 118 #define MACSTAT 0x1024 /* gmac status */ 119 #define MACDATA 0x11c0 /* gmac rd/wr data */ 120 #define MACCMD 0x11c4 /* gmac operation */ 121 #define CMD_IOWR (1U<<28) /* write op */ 122 #define CMD_BUSY (1U<<31) /* busy bit */ 123 #define DESCENG_INIT 0x11fc 124 #define DESCENG_SRST 0x1204 125 126 #define GMACMCR 0x0000 /* MAC configuration */ 127 #define MCR_IBN (1U<<30) /* */ 128 #define MCR_CST (1U<<25) /* strip CRC */ 129 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 130 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 131 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 132 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 133 #define MCR_USEFDX (1U<<11) /* force full duplex */ 134 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 135 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 136 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 137 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 138 #define _MCR_FDX 0x0000280c /* XXX TBD */ 139 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 140 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 141 #define AFR_RA (1U<<31) /* receive block all on */ 142 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 143 #define AFR_SAF (1U<<9) /* source address filter */ 144 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 145 #define AFR_PCF (3U<<6) /* */ 146 #define AFR_RB (1U<<5) /* reject broadcast frame */ 147 #define AFR_AM (1U<<4) /* accept all multicast frame */ 148 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 149 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 150 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 151 #define AFR_PM (1U<<0) /* run promisc mode */ 152 #define _AFR 0x80000001 /* XXX TBD */ 153 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 154 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 155 #define GMACGAR 0x0010 /* MDIO operation */ 156 #define GAR_PHY (11) /* mii phy 15:11 */ 157 #define GAR_REG (6) /* mii reg 10:6 */ 158 #define GAR_CTL (2) /* control 5:2 */ 159 #define GAR_IOWR (1U<<1) /* MDIO write op */ 160 #define GAR_BUSY (1U) /* busy bit */ 161 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 162 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 163 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 164 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 165 #define GMACIMPL 0x0020 /* implementation number XXXX.YYYY */ 166 #define GMACVTAG 0x001c /* VLAN tag control */ 167 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 168 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 169 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */ 170 #define GMACMAL(i) ((i)*8+0x44) 171 #define GMACMHT0 0x0500 /* multicast hash table 0 - 8*/ 172 173 #define GMACBMR 0x1000 /* DMA bus mode control 174 * 24 4PBL 175 * 22:17 RPBL 176 * 16 fix burst 177 * 15:14 priority between Rx and Tx 178 * 3 rxtx41 179 * 2 rxtx31 180 * 1 rxtx21 181 * 0 rxtx11 182 * 13:8 PBL possible DMA burst len 183 * 0 reset op. self clear 184 */ 185 #define _BMR 0x00412080 /* XXX TBD */ 186 #define _BMR0 0x00020181 /* XXX TBD */ 187 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 188 #define GMACRDLAR 0x100c /* */ 189 #define _RDLAR 0x18000 /* XXX TBD */ 190 #define GMACTDLAR 0x1010 /* */ 191 #define _TDLAR 0x1c000 /* XXX TBD */ 192 #define GMACOMR 0x1018 /* DMA operation */ 193 #define OMR_TXE (1U<<13) /* start Tx DMA engine, 0 to stop */ 194 #define OMR_RXE (1U<<1) /* start Rx DMA engine, 0 to stop */ 195 196 static int get_mdioclk(uint32_t); 197 198 /* descriptor format definition */ 199 struct tdes { 200 uint32_t t0, t1, t2, t3; 201 }; 202 203 struct rdes { 204 uint32_t r0, r1, r2, r3; 205 }; 206 207 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 208 #define T0_EOD (1U<<30) /* end of descriptor array */ 209 #define T0_DRID (24) /* 29:24 D-RID */ 210 #define T0_PT (1U<<21) /* 23:21 PT */ 211 #define T0_TRID (16) /* 20:16 T-RID */ 212 #define T0_FS (1U<<9) /* first segment of frame */ 213 #define T0_LS (1U<<8) /* last segment of frame */ 214 #define T0_CSUM (1U<<7) /* enable check sum offload */ 215 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 216 #define T0_TRS (1U<<4) /* 5:4 TRS */ 217 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 218 /* T1 segment address 63:32 */ 219 /* T2 segment address 31:0 */ 220 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 221 #define R0_OWN (1U<<31) /* desc is empty */ 222 #define R0_EOD (1U<<30) /* end of descriptor array */ 223 #define R0_SRID (24) /* 29:24 S-RID */ 224 #define R0_FR (1U<<23) /* FR */ 225 #define R0_ER (1U<<21) /* Rx error indication */ 226 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 227 #define R0_TDRID (14) /* 15:14 TD-RID */ 228 #define R0_FS (1U<<9) /* first segment of frame */ 229 #define R0_LS (1U<<8) /* last segment of frame */ 230 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 231 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 232 /* R1 frame address 63:32 */ 233 /* R2 frame address 31:0 */ 234 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 235 236 #define MD_NTXSEGS 16 /* fixed */ 237 #define MD_TXQUEUELEN 16 /* tunable */ 238 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 239 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 240 #define MD_NTXDESC (MD_TXQUEUELEN * MD_NTXSEGS) 241 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 242 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 243 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 244 245 #define MD_NRXDESC 64 /* tunable */ 246 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 247 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 248 249 #define SCX_INIT_RXDESC(sc, x) \ 250 do { \ 251 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 252 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 253 struct mbuf *__m = __rxs->rxs_mbuf; \ 254 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 255 __m->m_data = __m->m_ext.ext_buf; \ 256 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 257 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 258 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 259 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 260 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 261 } while (/*CONSTCOND*/0) 262 263 struct control_data { 264 struct tdes cd_txdescs[MD_NTXDESC]; 265 struct rdes cd_rxdescs[MD_NRXDESC]; 266 }; 267 #define SCX_CDOFF(x) offsetof(struct control_data, x) 268 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 269 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 270 271 struct scx_txsoft { 272 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 273 bus_dmamap_t txs_dmamap; /* our DMA map */ 274 int txs_firstdesc; /* first descriptor in packet */ 275 int txs_lastdesc; /* last descriptor in packet */ 276 int txs_ndesc; /* # of descriptors used */ 277 }; 278 279 struct scx_rxsoft { 280 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 281 bus_dmamap_t rxs_dmamap; /* our DMA map */ 282 }; 283 284 struct scx_softc { 285 device_t sc_dev; /* generic device information */ 286 bus_space_tag_t sc_st; /* bus space tag */ 287 bus_space_handle_t sc_sh; /* bus space handle */ 288 bus_size_t sc_sz; /* csr map size */ 289 bus_space_handle_t sc_eesh; /* eeprom section handle */ 290 bus_size_t sc_eesz; /* eeprom map size */ 291 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 292 struct ethercom sc_ethercom; /* Ethernet common data */ 293 struct mii_data sc_mii; /* MII */ 294 callout_t sc_tick_ch; /* PHY monitor callout */ 295 bus_dma_segment_t sc_seg; /* descriptor store seg */ 296 int sc_nseg; /* descriptor store nseg */ 297 void *sc_ih; /* interrupt cookie */ 298 int sc_phy_id; /* PHY address */ 299 int sc_flowflags; /* 802.3x PAUSE flow control */ 300 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 301 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 302 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 303 int sc_100mii; /* 1<<15 RMII/MII, 0 for RGMII */ 304 int sc_phandle; /* fdt phandle */ 305 306 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 307 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 308 309 struct control_data *sc_control_data; 310 #define sc_txdescs sc_control_data->cd_txdescs 311 #define sc_rxdescs sc_control_data->cd_rxdescs 312 313 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 314 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 315 int sc_txfree; /* number of free Tx descriptors */ 316 int sc_txnext; /* next ready Tx descriptor */ 317 int sc_txsfree; /* number of free Tx jobs */ 318 int sc_txsnext; /* next ready Tx job */ 319 int sc_txsdirty; /* dirty Tx jobs */ 320 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 321 322 krndsource_t rnd_source; /* random source */ 323 }; 324 325 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 326 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 327 328 #define SCX_CDTXSYNC(sc, x, n, ops) \ 329 do { \ 330 int __x, __n; \ 331 \ 332 __x = (x); \ 333 __n = (n); \ 334 \ 335 /* If it will wrap around, sync to the end of the ring. */ \ 336 if ((__x + __n) > MD_NTXDESC) { \ 337 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 338 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 339 (MD_NTXDESC - __x), (ops)); \ 340 __n -= (MD_NTXDESC - __x); \ 341 __x = 0; \ 342 } \ 343 \ 344 /* Now sync whatever is left. */ \ 345 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 346 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 347 } while (/*CONSTCOND*/0) 348 349 #define SCX_CDRXSYNC(sc, x, ops) \ 350 do { \ 351 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 352 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 353 } while (/*CONSTCOND*/0) 354 355 static int scx_fdt_match(device_t, cfdata_t, void *); 356 static void scx_fdt_attach(device_t, device_t, void *); 357 static int scx_acpi_match(device_t, cfdata_t, void *); 358 static void scx_acpi_attach(device_t, device_t, void *); 359 360 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 361 scx_fdt_match, scx_fdt_attach, NULL, NULL); 362 363 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 364 scx_acpi_match, scx_acpi_attach, NULL, NULL); 365 366 static void scx_attach_i(struct scx_softc *); 367 static void scx_reset(struct scx_softc *); 368 static int scx_init(struct ifnet *); 369 static void scx_start(struct ifnet *); 370 static void scx_stop(struct ifnet *, int); 371 static void scx_watchdog(struct ifnet *); 372 static int scx_ioctl(struct ifnet *, u_long, void *); 373 static void scx_set_rcvfilt(struct scx_softc *); 374 static int scx_ifmedia_upd(struct ifnet *); 375 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 376 static void mii_statchg(struct ifnet *); 377 static void phy_tick(void *); 378 static int mii_readreg(device_t, int, int, uint16_t *); 379 static int mii_writereg(device_t, int, int, uint16_t); 380 static int scx_intr(void *); 381 static void txreap(struct scx_softc *); 382 static void rxintr(struct scx_softc *); 383 static int add_rxbuf(struct scx_softc *, int); 384 static int spin_waitfor(struct scx_softc *, int, int); 385 static int mac_read(struct scx_softc *, int); 386 static void mac_write(struct scx_softc *, int, int); 387 static void loaducode(struct scx_softc *); 388 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 389 390 #define CSR_READ(sc,off) \ 391 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 392 #define CSR_WRITE(sc,off,val) \ 393 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 394 #define EE_READ(sc,off) \ 395 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 396 397 static int 398 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 399 { 400 static const char * compatible[] = { 401 "socionext,synquacer-netsec", 402 NULL 403 }; 404 struct fdt_attach_args * const faa = aux; 405 406 return of_match_compatible(faa->faa_phandle, compatible); 407 } 408 409 static void 410 scx_fdt_attach(device_t parent, device_t self, void *aux) 411 { 412 struct scx_softc * const sc = device_private(self); 413 struct fdt_attach_args * const faa = aux; 414 const int phandle = faa->faa_phandle; 415 bus_space_tag_t bst = faa->faa_bst; 416 bus_space_handle_t bsh; 417 bus_space_handle_t eebsh; 418 bus_addr_t addr[2]; 419 bus_size_t size[2]; 420 char intrstr[128]; 421 const char *phy_mode; 422 423 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 424 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 425 aprint_error(": unable to map device csr\n"); 426 return; 427 } 428 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 429 aprint_error(": failed to decode interrupt\n"); 430 goto fail; 431 } 432 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 433 NOT_MP_SAFE, scx_intr, sc); 434 if (sc->sc_ih == NULL) { 435 aprint_error_dev(self, "couldn't establish interrupt\n"); 436 goto fail; 437 } 438 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 439 || bus_space_map(faa->faa_bst, addr[0], size[1], 0, &eebsh) != 0) { 440 aprint_error(": unable to map device eeprom\n"); 441 goto fail; 442 } 443 444 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 445 if (phy_mode == NULL) { 446 aprint_error(": missing 'phy-mode' property\n"); 447 phy_mode = "rgmii"; 448 } 449 450 aprint_naive("\n"); 451 aprint_normal(": Gigabit Ethernet Controller\n"); 452 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 453 454 sc->sc_dev = self; 455 sc->sc_st = bst; 456 sc->sc_sh = bsh; 457 sc->sc_sz = size[0]; 458 sc->sc_eesh = eebsh; 459 sc->sc_eesz = size[1]; 460 sc->sc_dmat = faa->faa_dmat; 461 sc->sc_phandle = phandle; 462 sc->sc_100mii = (strcmp(phy_mode, "rgmii") != 0) ? MCR_USEMII : 0; 463 464 scx_attach_i(sc); 465 return; 466 fail: 467 if (sc->sc_eesz) 468 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 469 if (sc->sc_sz) 470 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 471 return; 472 } 473 474 static int 475 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 476 { 477 static const char * compatible[] = { 478 "SCX0001", 479 NULL 480 }; 481 struct acpi_attach_args *aa = aux; 482 483 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 484 return 0; 485 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 486 } 487 488 static void 489 scx_acpi_attach(device_t parent, device_t self, void *aux) 490 { 491 struct scx_softc * const sc = device_private(self); 492 struct acpi_attach_args * const aa = aux; 493 ACPI_HANDLE handle = aa->aa_node->ad_handle; 494 bus_space_tag_t bst = aa->aa_memt; 495 bus_space_handle_t bsh, eebsh; 496 struct acpi_resources res; 497 struct acpi_mem *mem; 498 struct acpi_irq *irq; 499 ACPI_STATUS rv; 500 501 rv = acpi_resource_parse(self, handle, "_CRS", 502 &res, &acpi_resource_parse_ops_default); 503 if (ACPI_FAILURE(rv)) 504 return; 505 mem = acpi_res_mem(&res, 0); 506 irq = acpi_res_irq(&res, 0); 507 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 508 aprint_error(": incomplete csr resources\n"); 509 return; 510 } 511 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 512 aprint_error(": couldn't map registers\n"); 513 return; 514 } 515 sc->sc_sz = mem->ar_length; 516 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 517 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 518 if (sc->sc_ih == NULL) { 519 aprint_error_dev(self, "couldn't establish interrupt\n"); 520 goto fail; 521 } 522 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 523 if (mem == NULL || mem->ar_length == 0) { 524 aprint_error(": incomplete eeprom resources\n"); 525 goto fail; 526 } 527 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 528 aprint_error(": couldn't map registers\n"); 529 goto fail; 530 } 531 sc->sc_eesz = mem->ar_length; 532 533 aprint_naive("\n"); 534 aprint_normal(": Gigabit Ethernet Controller\n"); 535 536 sc->sc_dev = self; 537 sc->sc_st = bst; 538 sc->sc_sh = bsh; 539 sc->sc_eesh = eebsh; 540 sc->sc_dmat = aa->aa_dmat64; 541 542 scx_attach_i(sc); 543 544 acpi_resource_cleanup(&res); 545 return; 546 fail: 547 if (sc->sc_eesz > 0) 548 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 549 if (sc->sc_sz > 0) 550 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 551 acpi_resource_cleanup(&res); 552 return; 553 } 554 555 static void 556 scx_attach_i(struct scx_softc *sc) 557 { 558 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 559 struct mii_data * const mii = &sc->sc_mii; 560 struct ifmedia * const ifm = &mii->mii_media; 561 uint32_t hwver, phyfreq; 562 uint8_t enaddr[ETHER_ADDR_LEN]; 563 bus_dma_segment_t seg; 564 uint32_t csr; 565 int i, nseg, error = 0; 566 567 hwver = CSR_READ(sc, HWVER1); 568 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 569 enaddr[0] = csr >> 24; 570 enaddr[1] = csr >> 16; 571 enaddr[2] = csr >> 8; 572 enaddr[3] = csr; 573 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 574 enaddr[4] = csr >> 24; 575 enaddr[5] = csr >> 16; 576 csr = CSR_READ(sc, GMACIMPL); 577 578 aprint_normal_dev(sc->sc_dev, "NetSec GbE (%d.%d) impl (%x.%x)\n", 579 hwver >> 16, hwver & 0xffff, csr >> 16, csr & 0xffff); 580 aprint_normal_dev(sc->sc_dev, 581 "Ethernet address %s\n", ether_sprintf(enaddr)); 582 583 phyfreq = 0; 584 sc->sc_phy_id = MII_PHY_ANY; 585 sc->sc_mdclk = get_mdioclk(phyfreq); /* 5:2 clk control */ 586 587 sc->sc_flowflags = 0; 588 589 if (sc->sc_ucodeloaded == 0) 590 loaducode(sc); 591 592 mii->mii_ifp = ifp; 593 mii->mii_readreg = mii_readreg; 594 mii->mii_writereg = mii_writereg; 595 mii->mii_statchg = mii_statchg; 596 597 sc->sc_ethercom.ec_mii = mii; 598 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 599 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 600 MII_OFFSET_ANY, MIIF_DOPAUSE); 601 if (LIST_FIRST(&mii->mii_phys) == NULL) { 602 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 603 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 604 } else 605 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 606 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 607 608 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 609 ifp->if_softc = sc; 610 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 611 ifp->if_ioctl = scx_ioctl; 612 ifp->if_start = scx_start; 613 ifp->if_watchdog = scx_watchdog; 614 ifp->if_init = scx_init; 615 ifp->if_stop = scx_stop; 616 IFQ_SET_READY(&ifp->if_snd); 617 618 if_attach(ifp); 619 if_deferred_start_init(ifp, NULL); 620 ether_ifattach(ifp, enaddr); 621 622 callout_init(&sc->sc_tick_ch, 0); 623 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 624 625 /* 626 * Allocate the control data structures, and create and load the 627 * DMA map for it. 628 */ 629 error = bus_dmamem_alloc(sc->sc_dmat, 630 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 631 if (error != 0) { 632 aprint_error_dev(sc->sc_dev, 633 "unable to allocate control data, error = %d\n", error); 634 goto fail_0; 635 } 636 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 637 sizeof(struct control_data), (void **)&sc->sc_control_data, 638 BUS_DMA_COHERENT); 639 if (error != 0) { 640 aprint_error_dev(sc->sc_dev, 641 "unable to map control data, error = %d\n", error); 642 goto fail_1; 643 } 644 error = bus_dmamap_create(sc->sc_dmat, 645 sizeof(struct control_data), 1, 646 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 647 if (error != 0) { 648 aprint_error_dev(sc->sc_dev, 649 "unable to create control data DMA map, " 650 "error = %d\n", error); 651 goto fail_2; 652 } 653 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 654 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 655 if (error != 0) { 656 aprint_error_dev(sc->sc_dev, 657 "unable to load control data DMA map, error = %d\n", 658 error); 659 goto fail_3; 660 } 661 for (i = 0; i < MD_TXQUEUELEN; i++) { 662 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 663 MD_NTXSEGS, MCLBYTES, 0, 0, 664 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 665 aprint_error_dev(sc->sc_dev, 666 "unable to create tx DMA map %d, error = %d\n", 667 i, error); 668 goto fail_4; 669 } 670 } 671 for (i = 0; i < MD_NRXDESC; i++) { 672 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 673 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 674 aprint_error_dev(sc->sc_dev, 675 "unable to create rx DMA map %d, error = %d\n", 676 i, error); 677 goto fail_5; 678 } 679 sc->sc_rxsoft[i].rxs_mbuf = NULL; 680 } 681 sc->sc_seg = seg; 682 sc->sc_nseg = nseg; 683 printf("bus_dmaseg ds_addr %08lx, ds_len %08lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 684 685 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 686 pmf_class_network_register(sc->sc_dev, ifp); 687 else 688 aprint_error_dev(sc->sc_dev, 689 "couldn't establish power handler\n"); 690 691 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 692 RND_TYPE_NET, RND_FLAG_DEFAULT); 693 694 return; 695 696 fail_5: 697 for (i = 0; i < MD_NRXDESC; i++) { 698 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 699 bus_dmamap_destroy(sc->sc_dmat, 700 sc->sc_rxsoft[i].rxs_dmamap); 701 } 702 fail_4: 703 for (i = 0; i < MD_TXQUEUELEN; i++) { 704 if (sc->sc_txsoft[i].txs_dmamap != NULL) 705 bus_dmamap_destroy(sc->sc_dmat, 706 sc->sc_txsoft[i].txs_dmamap); 707 } 708 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 709 fail_3: 710 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 711 fail_2: 712 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 713 sizeof(struct control_data)); 714 fail_1: 715 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 716 fail_0: 717 if (sc->sc_phandle) 718 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 719 else 720 acpi_intr_disestablish(sc->sc_ih); 721 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 722 return; 723 } 724 725 static void 726 scx_reset(struct scx_softc *sc) 727 { 728 729 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 730 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 731 732 CSR_WRITE(sc, DESCENG_SRST, 1); 733 CSR_WRITE(sc, DESCENG_INIT, 1); 734 mac_write(sc, GMACBMR, _BMR); 735 mac_write(sc, GMACRDLAR, _RDLAR); 736 mac_write(sc, GMACTDLAR, _TDLAR); 737 mac_write(sc, GMACAFR, _AFR); 738 } 739 740 static int 741 scx_init(struct ifnet *ifp) 742 { 743 struct scx_softc *sc = ifp->if_softc; 744 const uint8_t *ea = CLLADDR(ifp->if_sadl); 745 uint32_t csr; 746 int i; 747 748 /* Cancel pending I/O. */ 749 scx_stop(ifp, 0); 750 751 /* Reset the chip to a known state. */ 752 scx_reset(sc); 753 754 /* build sane Tx and load Rx descriptors with mbuf */ 755 for (i = 0; i < MD_NTXDESC; i++) 756 sc->sc_txdescs[i].t0 = T0_OWN; 757 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 758 for (i = 0; i < MD_NRXDESC; i++) 759 (void)add_rxbuf(sc, i); 760 761 /* set my address in perfect match slot 0 */ 762 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 763 CSR_WRITE(sc, GMACMAL0, csr); 764 csr = (ea[5] << 8) | ea[4]; 765 CSR_WRITE(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 766 767 /* accept multicast frame or run promisc mode */ 768 scx_set_rcvfilt(sc); 769 770 (void)scx_ifmedia_upd(ifp); 771 772 /* kick to start GMAC engine */ 773 csr = mac_read(sc, GMACOMR); 774 CSR_WRITE(sc, RXINT_CLR, ~0); 775 CSR_WRITE(sc, TXINT_CLR, ~0); 776 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 777 778 ifp->if_flags |= IFF_RUNNING; 779 ifp->if_flags &= ~IFF_OACTIVE; 780 781 /* start one second timer */ 782 callout_schedule(&sc->sc_tick_ch, hz); 783 784 return 0; 785 } 786 787 static void 788 scx_stop(struct ifnet *ifp, int disable) 789 { 790 struct scx_softc *sc = ifp->if_softc; 791 792 /* Stop the one second clock. */ 793 callout_stop(&sc->sc_tick_ch); 794 795 /* Down the MII. */ 796 mii_down(&sc->sc_mii); 797 798 /* Mark the interface down and cancel the watchdog timer. */ 799 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 800 ifp->if_timer = 0; 801 } 802 803 static void 804 scx_watchdog(struct ifnet *ifp) 805 { 806 struct scx_softc *sc = ifp->if_softc; 807 808 /* 809 * Since we're not interrupting every packet, sweep 810 * up before we report an error. 811 */ 812 txreap(sc); 813 814 if (sc->sc_txfree != MD_NTXDESC) { 815 aprint_error_dev(sc->sc_dev, 816 "device timeout (txfree %d txsfree %d txnext %d)\n", 817 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 818 if_statinc(ifp, if_oerrors); 819 820 /* Reset the interface. */ 821 scx_init(ifp); 822 } 823 824 scx_start(ifp); 825 } 826 827 static int 828 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 829 { 830 struct scx_softc *sc = ifp->if_softc; 831 struct ifreq *ifr = (struct ifreq *)data; 832 struct ifmedia *ifm; 833 int s, error; 834 835 s = splnet(); 836 837 switch (cmd) { 838 case SIOCSIFMEDIA: 839 /* Flow control requires full-duplex mode. */ 840 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 841 (ifr->ifr_media & IFM_FDX) == 0) 842 ifr->ifr_media &= ~IFM_ETH_FMASK; 843 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 844 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 845 /* We can do both TXPAUSE and RXPAUSE. */ 846 ifr->ifr_media |= 847 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 848 } 849 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 850 } 851 ifm = &sc->sc_mii.mii_media; 852 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 853 break; 854 default: 855 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 856 break; 857 858 error = 0; 859 860 if (cmd == SIOCSIFCAP) 861 error = (*ifp->if_init)(ifp); 862 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 863 ; 864 else if (ifp->if_flags & IFF_RUNNING) { 865 /* 866 * Multicast list has changed; set the hardware filter 867 * accordingly. 868 */ 869 scx_set_rcvfilt(sc); 870 } 871 break; 872 } 873 874 splx(s); 875 return error; 876 } 877 878 static void 879 scx_set_rcvfilt(struct scx_softc *sc) 880 { 881 struct ethercom * const ec = &sc->sc_ethercom; 882 struct ifnet * const ifp = &ec->ec_if; 883 struct ether_multistep step; 884 struct ether_multi *enm; 885 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 886 uint32_t csr, crc; 887 int i; 888 889 csr = CSR_READ(sc, GMACAFR); 890 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 891 CSR_WRITE(sc, GMACAFR, csr); 892 893 ETHER_LOCK(ec); 894 if (ifp->if_flags & IFF_PROMISC) { 895 ec->ec_flags |= ETHER_F_ALLMULTI; 896 ETHER_UNLOCK(ec); 897 goto update; 898 } 899 ec->ec_flags &= ~ETHER_F_ALLMULTI; 900 901 /* clear 15 entry supplimental perfect match filter */ 902 for (i = 1; i < 16; i++) 903 CSR_WRITE(sc, GMACMAH(i), 0); 904 /* build 256 bit multicast hash filter */ 905 memset(mchash, 0, sizeof(mchash)); 906 crc = 0; 907 908 ETHER_FIRST_MULTI(step, ec, enm); 909 i = 1; /* slot 0 is occupied */ 910 while (enm != NULL) { 911 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 912 /* 913 * We must listen to a range of multicast addresses. 914 * For now, just accept all multicasts, rather than 915 * trying to set only those filter bits needed to match 916 * the range. (At this time, the only use of address 917 * ranges is for IP multicast routing, for which the 918 * range is big enough to require all bits set.) 919 */ 920 ec->ec_flags |= ETHER_F_ALLMULTI; 921 ETHER_UNLOCK(ec); 922 goto update; 923 } 924 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 925 if (i < 16) { 926 /* use 31 entry perfect match filter */ 927 uint32_t addr; 928 uint8_t *ep = enm->enm_addrlo; 929 addr = (ep[3] << 24) | (ep[2] << 16) 930 | (ep[1] << 8) | ep[0]; 931 CSR_WRITE(sc, GMACMAL(i), addr); 932 addr = (ep[5] << 8) | ep[4]; 933 CSR_WRITE(sc, GMACMAH(i), addr | 1U<<31); 934 } else { 935 /* use hash table when too many */ 936 /* bit_reserve_32(~crc) !? */ 937 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 938 /* 3(31:29) 5(28:24) bit sampling */ 939 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 940 } 941 ETHER_NEXT_MULTI(step, enm); 942 i++; 943 } 944 ETHER_UNLOCK(ec); 945 946 if (crc) 947 csr |= AFR_MHTE; 948 for (i = 0; i < 8; i++) 949 CSR_WRITE(sc, GMACMHT0 + i * 4, mchash[i]); 950 CSR_WRITE(sc, GMACAFR, csr); 951 return; 952 953 update: 954 /* With PM or AM, MHTE/MHTL/MHTH are never consulted. really? */ 955 if (ifp->if_flags & IFF_PROMISC) 956 csr |= AFR_PM; /* run promisc. mode */ 957 else 958 csr |= AFR_AM; /* accept all multicast */ 959 CSR_WRITE(sc, GMACAFR, csr); 960 return; 961 } 962 963 static int 964 scx_ifmedia_upd(struct ifnet *ifp) 965 { 966 struct scx_softc *sc = ifp->if_softc; 967 struct ifmedia *ifm = &sc->sc_mii.mii_media; 968 969 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 970 ; /* restart AN */ 971 ; /* enable AN */ 972 ; /* advertise flow control pause */ 973 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 974 } else { 975 #if 1 /* XXX not sure to belong here XXX */ 976 uint32_t mcr = mac_read(sc, GMACMCR); 977 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 978 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 979 else { 980 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX 981 && sc->sc_100mii) 982 mcr |= MCR_SPD100; 983 mcr |= MCR_USEMII; 984 } 985 if (ifm->ifm_cur->ifm_media & IFM_FDX) 986 mcr |= MCR_USEFDX; 987 mcr |= MCR_CST | MCR_JE; 988 if (sc->sc_100mii == 0) 989 mcr |= MCR_IBN; 990 mac_write(sc, GMACMCR, mcr); 991 #endif 992 } 993 return 0; 994 } 995 996 static void 997 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 998 { 999 struct scx_softc *sc = ifp->if_softc; 1000 struct mii_data *mii = &sc->sc_mii; 1001 1002 mii_pollstat(mii); 1003 ifmr->ifm_status = mii->mii_media_status; 1004 ifmr->ifm_active = sc->sc_flowflags | 1005 (mii->mii_media_active & ~IFM_ETH_FMASK); 1006 } 1007 1008 void 1009 mii_statchg(struct ifnet *ifp) 1010 { 1011 struct scx_softc *sc = ifp->if_softc; 1012 struct mii_data *mii = &sc->sc_mii; 1013 uint32_t fcr; 1014 1015 /* Get flow control negotiation result. */ 1016 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1017 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1018 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1019 1020 /* Adjust PAUSE flow control. */ 1021 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1022 if (mii->mii_media_active & IFM_FDX) { 1023 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1024 fcr |= FCR_TFE; 1025 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1026 fcr |= FCR_RFE; 1027 } 1028 mac_write(sc, GMACFCR, fcr); 1029 1030 printf("%ctxfe, %crxfe\n", 1031 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1032 } 1033 1034 static void 1035 phy_tick(void *arg) 1036 { 1037 struct scx_softc *sc = arg; 1038 struct mii_data *mii = &sc->sc_mii; 1039 int s; 1040 1041 s = splnet(); 1042 mii_tick(mii); 1043 splx(s); 1044 1045 callout_schedule(&sc->sc_tick_ch, hz); 1046 } 1047 1048 static int 1049 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1050 { 1051 struct scx_softc *sc = device_private(self); 1052 uint32_t miia; 1053 int error; 1054 1055 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1056 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1057 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1058 if (error) 1059 return error; 1060 *val = mac_read(sc, GMACGDR); 1061 return 0; 1062 } 1063 1064 static int 1065 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1066 { 1067 struct scx_softc *sc = device_private(self); 1068 uint32_t miia; 1069 uint16_t dummy; 1070 int error; 1071 1072 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1073 mac_write(sc, GMACGDR, val); 1074 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1075 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1076 if (error) 1077 return error; 1078 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1079 return 0; 1080 } 1081 1082 static void 1083 scx_start(struct ifnet *ifp) 1084 { 1085 struct scx_softc *sc = ifp->if_softc; 1086 struct mbuf *m0, *m; 1087 struct scx_txsoft *txs; 1088 bus_dmamap_t dmamap; 1089 int error, nexttx, lasttx, ofree, seg; 1090 uint32_t tdes0; 1091 1092 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1093 return; 1094 1095 /* Remember the previous number of free descriptors. */ 1096 ofree = sc->sc_txfree; 1097 1098 /* 1099 * Loop through the send queue, setting up transmit descriptors 1100 * until we drain the queue, or use up all available transmit 1101 * descriptors. 1102 */ 1103 for (;;) { 1104 IFQ_POLL(&ifp->if_snd, m0); 1105 if (m0 == NULL) 1106 break; 1107 1108 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1109 txreap(sc); 1110 if (sc->sc_txsfree == 0) 1111 break; 1112 } 1113 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1114 dmamap = txs->txs_dmamap; 1115 1116 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1117 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1118 if (error) { 1119 if (error == EFBIG) { 1120 aprint_error_dev(sc->sc_dev, 1121 "Tx packet consumes too many " 1122 "DMA segments, dropping...\n"); 1123 IFQ_DEQUEUE(&ifp->if_snd, m0); 1124 m_freem(m0); 1125 continue; 1126 } 1127 /* Short on resources, just stop for now. */ 1128 break; 1129 } 1130 1131 if (dmamap->dm_nsegs > sc->sc_txfree) { 1132 /* 1133 * Not enough free descriptors to transmit this 1134 * packet. We haven't committed anything yet, 1135 * so just unload the DMA map, put the packet 1136 * back on the queue, and punt. Notify the upper 1137 * layer that there are not more slots left. 1138 */ 1139 ifp->if_flags |= IFF_OACTIVE; 1140 bus_dmamap_unload(sc->sc_dmat, dmamap); 1141 break; 1142 } 1143 1144 IFQ_DEQUEUE(&ifp->if_snd, m0); 1145 1146 /* 1147 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1148 */ 1149 1150 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1151 BUS_DMASYNC_PREWRITE); 1152 1153 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1154 lasttx = -1; 1155 for (nexttx = sc->sc_txnext, seg = 0; 1156 seg < dmamap->dm_nsegs; 1157 seg++, nexttx = MD_NEXTTX(nexttx)) { 1158 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1159 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1160 /* 1161 * If this is the first descriptor we're 1162 * enqueueing, don't set the OWN bit just 1163 * yet. That could cause a race condition. 1164 * We'll do it below. 1165 */ 1166 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1167 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1168 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1169 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1170 (15 << T0_TRID) | T0_PT | 1171 sc->sc_t0coso | T0_TRS; 1172 tdes0 = T0_OWN; /* 2nd and other segments */ 1173 lasttx = nexttx; 1174 } 1175 /* 1176 * Outgoing NFS mbuf must be unloaded when Tx completed. 1177 * Without T1_IC NFS mbuf is left unack'ed for excessive 1178 * time and NFS stops to proceed until scx_watchdog() 1179 * calls txreap() to reclaim the unack'ed mbuf. 1180 * It's painful to traverse every mbuf chain to determine 1181 * whether someone is waiting for Tx completion. 1182 */ 1183 m = m0; 1184 do { 1185 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1186 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1187 break; 1188 } 1189 } while ((m = m->m_next) != NULL); 1190 1191 /* Write deferred 1st segment T0_OWN at the final stage */ 1192 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1193 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1194 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1195 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1196 1197 /* Tell DMA start transmit */ 1198 /* CSR_WRITE(sc, MDTSC, 1); */ 1199 1200 txs->txs_mbuf = m0; 1201 txs->txs_firstdesc = sc->sc_txnext; 1202 txs->txs_lastdesc = lasttx; 1203 txs->txs_ndesc = dmamap->dm_nsegs; 1204 1205 sc->sc_txfree -= txs->txs_ndesc; 1206 sc->sc_txnext = nexttx; 1207 sc->sc_txsfree--; 1208 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1209 /* 1210 * Pass the packet to any BPF listeners. 1211 */ 1212 bpf_mtap(ifp, m0, BPF_D_OUT); 1213 } 1214 1215 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1216 /* No more slots left; notify upper layer. */ 1217 ifp->if_flags |= IFF_OACTIVE; 1218 } 1219 if (sc->sc_txfree != ofree) { 1220 /* Set a watchdog timer in case the chip flakes out. */ 1221 ifp->if_timer = 5; 1222 } 1223 } 1224 1225 static int 1226 scx_intr(void *arg) 1227 { 1228 struct scx_softc *sc = arg; 1229 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1230 1231 (void)ifp; 1232 rxintr(sc); 1233 txreap(sc); 1234 return 1; 1235 } 1236 1237 static void 1238 txreap(struct scx_softc *sc) 1239 { 1240 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1241 struct scx_txsoft *txs; 1242 uint32_t txstat; 1243 int i; 1244 1245 ifp->if_flags &= ~IFF_OACTIVE; 1246 1247 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1248 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1249 txs = &sc->sc_txsoft[i]; 1250 1251 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1252 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1253 1254 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1255 if (txstat & T0_OWN) /* desc is still in use */ 1256 break; 1257 1258 /* There is no way to tell transmission status per frame */ 1259 1260 if_statinc(ifp, if_opackets); 1261 1262 sc->sc_txfree += txs->txs_ndesc; 1263 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1264 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1265 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1266 m_freem(txs->txs_mbuf); 1267 txs->txs_mbuf = NULL; 1268 } 1269 sc->sc_txsdirty = i; 1270 if (sc->sc_txsfree == MD_TXQUEUELEN) 1271 ifp->if_timer = 0; 1272 } 1273 1274 static void 1275 rxintr(struct scx_softc *sc) 1276 { 1277 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1278 struct scx_rxsoft *rxs; 1279 struct mbuf *m; 1280 uint32_t rxstat; 1281 int i, len; 1282 1283 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1284 rxs = &sc->sc_rxsoft[i]; 1285 1286 SCX_CDRXSYNC(sc, i, 1287 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1288 1289 rxstat = sc->sc_rxdescs[i].r0; 1290 if (rxstat & R0_OWN) /* desc is left empty */ 1291 break; 1292 1293 /* R0_FS | R0_LS must have been marked for this desc */ 1294 1295 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1296 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1297 1298 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1299 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1300 m = rxs->rxs_mbuf; 1301 1302 if (add_rxbuf(sc, i) != 0) { 1303 if_statinc(ifp, if_ierrors); 1304 SCX_INIT_RXDESC(sc, i); 1305 bus_dmamap_sync(sc->sc_dmat, 1306 rxs->rxs_dmamap, 0, 1307 rxs->rxs_dmamap->dm_mapsize, 1308 BUS_DMASYNC_PREREAD); 1309 continue; 1310 } 1311 1312 m_set_rcvif(m, ifp); 1313 m->m_pkthdr.len = m->m_len = len; 1314 1315 if (rxstat & R0_CSUM) { 1316 uint32_t csum = M_CSUM_IPv4; 1317 if (rxstat & R0_CERR) 1318 csum |= M_CSUM_IPv4_BAD; 1319 m->m_pkthdr.csum_flags |= csum; 1320 } 1321 if_percpuq_enqueue(ifp->if_percpuq, m); 1322 } 1323 sc->sc_rxptr = i; 1324 } 1325 1326 static int 1327 add_rxbuf(struct scx_softc *sc, int i) 1328 { 1329 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1330 struct mbuf *m; 1331 int error; 1332 1333 MGETHDR(m, M_DONTWAIT, MT_DATA); 1334 if (m == NULL) 1335 return ENOBUFS; 1336 1337 MCLGET(m, M_DONTWAIT); 1338 if ((m->m_flags & M_EXT) == 0) { 1339 m_freem(m); 1340 return ENOBUFS; 1341 } 1342 1343 if (rxs->rxs_mbuf != NULL) 1344 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1345 1346 rxs->rxs_mbuf = m; 1347 1348 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1349 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1350 if (error) { 1351 aprint_error_dev(sc->sc_dev, 1352 "can't load rx DMA map %d, error = %d\n", i, error); 1353 panic("add_rxbuf"); 1354 } 1355 1356 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1357 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1358 SCX_INIT_RXDESC(sc, i); 1359 1360 return 0; 1361 } 1362 1363 static int 1364 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1365 { 1366 int val, loop; 1367 1368 val = CSR_READ(sc, reg); 1369 if ((val & exist) == 0) 1370 return 0; 1371 loop = 3000; 1372 do { 1373 DELAY(10); 1374 val = CSR_READ(sc, reg); 1375 } while (--loop > 0 && (val & exist)); 1376 return (loop > 0) ? 0 : ETIMEDOUT; 1377 } 1378 1379 static int 1380 mac_read(struct scx_softc *sc, int reg) 1381 { 1382 1383 CSR_WRITE(sc, MACCMD, reg); 1384 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1385 return CSR_READ(sc, MACDATA); 1386 } 1387 1388 static void 1389 mac_write(struct scx_softc *sc, int reg, int val) 1390 { 1391 1392 CSR_WRITE(sc, MACDATA, val); 1393 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1394 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1395 } 1396 1397 static int 1398 get_mdioclk(uint32_t freq) 1399 { 1400 1401 const struct { 1402 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 1403 } mdioclk[] = { 1404 { 35, 2 }, /* 25-35 MHz */ 1405 { 60, 3 }, /* 35-60 MHz */ 1406 { 100, 0 }, /* 60-100 MHz */ 1407 { 150, 1 }, /* 100-150 MHz */ 1408 { 250, 4 }, /* 150-250 MHz */ 1409 { 300, 5 }, /* 250-300 MHz */ 1410 }; 1411 int i; 1412 1413 /* convert MDIO clk to a divisor value */ 1414 if (freq < mdioclk[0].freq) 1415 return mdioclk[0].bit; 1416 for (i = 1; i < __arraycount(mdioclk); i++) { 1417 if (freq < mdioclk[i].freq) 1418 return mdioclk[i-1].bit; 1419 } 1420 return mdioclk[__arraycount(mdioclk) - 1].bit << GAR_CTL; 1421 } 1422 1423 static void 1424 loaducode(struct scx_softc *sc) 1425 { 1426 uint32_t up, lo, sz; 1427 uint64_t addr; 1428 1429 sc->sc_ucodeloaded = 1; 1430 1431 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1432 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1433 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1434 sz *= 4; 1435 addr = ((uint64_t)up << 32) | lo; 1436 aprint_normal_dev(sc->sc_dev, "H2M ucode %u\n", sz); 1437 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1438 1439 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1440 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1441 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1442 sz *= 4; 1443 addr = ((uint64_t)up << 32) | lo; 1444 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1445 aprint_normal_dev(sc->sc_dev, "M2H ucode %u\n", sz); 1446 1447 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1448 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1449 sz *= 4; 1450 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1451 aprint_normal_dev(sc->sc_dev, "PKT ucode %u\n", sz); 1452 } 1453 1454 static void 1455 injectucode(struct scx_softc *sc, int port, 1456 bus_addr_t addr, bus_size_t size) 1457 { 1458 bus_space_handle_t bsh; 1459 bus_size_t off; 1460 uint32_t ucode; 1461 1462 if (!bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1463 aprint_error_dev(sc->sc_dev, 1464 "eeprom map failure for ucode port 0x%x\n", port); 1465 return; 1466 } 1467 for (off = 0; off < size; off += 4) { 1468 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1469 CSR_WRITE(sc, port, ucode); 1470 } 1471 bus_space_unmap(sc->sc_st, bsh, size); 1472 } 1473
Indexes created Thu Sep 25 16:09:42 GMT 2025