if_scx.c revision 1.9
1 /* $NetBSD: if_scx.c,v 1.9 2020/03/24 10:47:03 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define NOT_MP_SAFE 0 33 34 /* 35 * Socionext SC2A11 SynQuacer NetSec GbE driver 36 * 37 * (possibly incorrect notes to be removed eventually) 38 * - 32 byte descriptor for 64 bit paddr design. 39 * - multiple rings seems available. There are special descriptor fields 40 * to designify ring number from which to arrive or to which go. 41 * - memory mapped EEPROM to hold MAC address. The rest of the area is 42 * occupied by a set of ucode for two DMA engines and one packet engine. 43 * - The size of frame address filter is unknown. Might be 16 or even 128. 44 * - The first slot is my own station address. Always enabled to perform 45 * to identify oneself. 46 * - 1~16 are for supplimental MAC addresses. Independently enabled for 47 * use. Good to catch multicast. Byte-wise selective match available. 48 * Use the mask to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }. 49 * - 16~128 might be exact match without byte-mask. 50 * - The size of multicast hash filter store is unknown. Might be 256 bit. 51 * - Socionext/Linaro "NetSec" code makes many cut shorts. Some constants 52 * are left unexplained. The values should be handled via external 53 * controls like FDT descriptions. Fortunately, Intel/Altera CycloneV PDFs 54 * describe every detail of "such the instance of" DW EMAC IP and 55 * most of them are likely applicable to SC2A11 GbE. 56 */ 57 58 #include <sys/cdefs.h> 59 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.9 2020/03/24 10:47:03 nisimura Exp $"); 60 61 #include <sys/param.h> 62 #include <sys/bus.h> 63 #include <sys/intr.h> 64 #include <sys/device.h> 65 #include <sys/callout.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/errno.h> 69 #include <sys/rndsource.h> 70 #include <sys/kernel.h> 71 #include <sys/systm.h> 72 73 #include <net/if.h> 74 #include <net/if_media.h> 75 #include <net/if_dl.h> 76 #include <net/if_ether.h> 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <net/bpf.h> 80 81 #include <dev/fdt/fdtvar.h> 82 #include <dev/acpi/acpireg.h> 83 #include <dev/acpi/acpivar.h> 84 #include <dev/acpi/acpi_intr.h> 85 86 #define SWRESET 0x104 87 #define COMINIT 0x120 88 #define INTRST 0x200 89 #define IRQ_RX (1U<<1) 90 #define IRQ_TX (1U<<0) 91 #define INTREN 0x204 92 #define INTR_SET 0x234 93 #define INTR_CLR 0x238 94 #define TXINTST 0x400 95 #define TXINTEN 0x404 96 #define TXINT_SET 0x428 97 #define TXINT_CLR 0x42c 98 #define TXI_NTOWNR (1U<<17) 99 #define TXI_TR_ERR (1U<<16) 100 #define TXI_TXDONE (1U<<15) 101 #define TXI_TMREXP (1U<<14) 102 #define RXINTST 0x440 103 #define RXINTEN 0x444 104 #define RXINT_SET 0x468 105 #define RXINT_CLR 0x46c 106 #define RXI_RC_ERR (1U<<16) 107 #define RXI_PKTCNT (1U<<15) 108 #define RXI_TMREXP (1U<<14) 109 #define TXTIMER 0x41c 110 #define RXTIMER 0x45c 111 #define TXCOUNT 0x410 112 #define RXCOUNT 0x454 113 #define H2MENG 0x210 /* DMAC host2media ucode port */ 114 #define M2HENG 0x21c /* DMAC media2host ucode port */ 115 #define PKTENG 0x0d0 /* packet engine ucode port */ 116 #define HWVER0 0x22c 117 #define HWVER1 0x230 118 119 #define MACSTAT 0x1024 /* gmac status */ 120 #define MACDATA 0x11c0 /* gmac rd/wr data */ 121 #define MACCMD 0x11c4 /* gmac operation */ 122 #define CMD_IOWR (1U<<28) /* write op */ 123 #define CMD_BUSY (1U<<31) /* busy bit */ 124 #define DESCENG_INIT 0x11fc 125 #define DESCENG_SRST 0x1204 126 127 #define GMACMCR 0x0000 /* MAC configuration */ 128 #define MCR_IBN (1U<<30) /* */ 129 #define MCR_CST (1U<<25) /* strip CRC */ 130 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */ 131 #define MCR_JE (1U<<20) /* ignore oversized >9018 condition */ 132 #define MCR_USEMII (1U<<15) /* 1: RMII/MII, 0: RGMII */ 133 #define MCR_SPD100 (1U<<14) /* force speed 100 */ 134 #define MCR_USEFDX (1U<<11) /* force full duplex */ 135 #define MCR_IPCKEN (1U<<10) /* handle checksum */ 136 #define MCR_ACS (1U<<7) /* auto pad strip CRC */ 137 #define MCR_TXE (1U<<3) /* start Tx DMA engine */ 138 #define MCR_RXE (1U<<2) /* start Rx DMA engine */ 139 #define _MCR_FDX 0x0000280c /* XXX TBD */ 140 #define _MCR_HDX 0x0001a00c /* XXX TBD */ 141 #define GMACAFR 0x0004 /* frame DA/SA address filter */ 142 #define AFR_RA (1U<<31) /* receive block all on */ 143 #define AFR_HPF (1U<<10) /* activate hash or perfect filter */ 144 #define AFR_SAF (1U<<9) /* source address filter */ 145 #define AFR_SAIF (1U<<8) /* SA inverse filtering */ 146 #define AFR_PCF (3U<<6) /* */ 147 #define AFR_RB (1U<<5) /* reject broadcast frame */ 148 #define AFR_AM (1U<<4) /* accept all multicast frame */ 149 #define AFR_DAIF (1U<<3) /* DA inverse filtering */ 150 #define AFR_MHTE (1U<<2) /* use multicast hash table */ 151 #define AFR_UHTE (1U<<1) /* use additional MAC addresses */ 152 #define AFR_PM (1U<<0) /* run promisc mode */ 153 #define _AFR 0x80000001 /* XXX TBD */ 154 #define GMACMHTH 0x0008 /* XXX multicast hash table 63:32 */ 155 #define GMACMHTL 0x000c /* XXX multicast hash table 31:0 */ 156 #define GMACGAR 0x0010 /* MDIO operation */ 157 #define GAR_PHY (11) /* mii phy 15:11 */ 158 #define GAR_REG (6) /* mii reg 10:6 */ 159 #define GAR_CTL (2) /* control 5:2 */ 160 #define GAR_IOWR (1U<<1) /* MDIO write op */ 161 #define GAR_BUSY (1U) /* busy bit */ 162 #define GMACGDR 0x0014 /* MDIO rd/wr data */ 163 #define GMACFCR 0x0018 /* 802.3x flowcontrol */ 164 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */ 165 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */ 166 #define GMACVTAG 0x001c /* VLAN tag control */ 167 #define GMACIMPL 0x0020 /* implementation number XXXX.YYYY */ 168 #define GMACMAH0 0x0040 /* MAC address 0 47:32 */ 169 #define GMACMAL0 0x0044 /* MAC address 0 31:0 */ 170 #define GMACMAH(i) ((i)*8+0x40) /* supplimental MAC addr 1 - 15 */ 171 #define GMACMAL(i) ((i)*8+0x44) 172 #define GMACMHT0 0x0500 /* multicast hash table 0 - 7 */ 173 #define GMACMHT(i) ((i)*4+0500) 174 175 #define GMACBMR 0x1000 /* DMA bus mode control 176 * 24 4PBL 177 * 22:17 RPBL 178 * 16 fix burst 179 * 15:14 priority between Rx and Tx 180 * 3 rxtx41 181 * 2 rxtx31 182 * 1 rxtx21 183 * 0 rxtx11 184 * 13:8 PBL possible DMA burst len 185 * 0 reset op. self clear 186 */ 187 #define _BMR 0x00412080 /* XXX TBD */ 188 #define _BMR0 0x00020181 /* XXX TBD */ 189 #define BMR_RST (1U<<0) /* reset op. self clear when done */ 190 #define GMACRDLAR 0x100c /* */ 191 #define _RDLAR 0x18000 /* XXX TBD */ 192 #define GMACTDLAR 0x1010 /* */ 193 #define _TDLAR 0x1c000 /* XXX TBD */ 194 #define GMACOMR 0x1018 /* DMA operation */ 195 #define OMR_TXE (1U<<13) /* start Tx DMA engine, 0 to stop */ 196 #define OMR_RXE (1U<<1) /* start Rx DMA engine, 0 to stop */ 197 198 static int get_mdioclk(uint32_t); 199 200 /* descriptor format definition */ 201 struct tdes { 202 uint32_t t0, t1, t2, t3; 203 }; 204 205 struct rdes { 206 uint32_t r0, r1, r2, r3; 207 }; 208 209 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 210 #define T0_EOD (1U<<30) /* end of descriptor array */ 211 #define T0_DRID (24) /* 29:24 D-RID */ 212 #define T0_PT (1U<<21) /* 23:21 PT */ 213 #define T0_TRID (16) /* 20:16 T-RID */ 214 #define T0_FS (1U<<9) /* first segment of frame */ 215 #define T0_LS (1U<<8) /* last segment of frame */ 216 #define T0_CSUM (1U<<7) /* enable check sum offload */ 217 #define T0_SGOL (1U<<6) /* enable TCP segment offload */ 218 #define T0_TRS (1U<<4) /* 5:4 TRS */ 219 #define T0_IOC (0) /* XXX TBD interrupt when completed */ 220 /* T1 segment address 63:32 */ 221 /* T2 segment address 31:0 */ 222 /* T3 31:16 TCP segment length, 15:0 segment length to transmit */ 223 #define R0_OWN (1U<<31) /* desc is empty */ 224 #define R0_EOD (1U<<30) /* end of descriptor array */ 225 #define R0_SRID (24) /* 29:24 S-RID */ 226 #define R0_FR (1U<<23) /* FR */ 227 #define R0_ER (1U<<21) /* Rx error indication */ 228 #define R0_ERR (3U<<16) /* 18:16 receive error code */ 229 #define R0_TDRID (14) /* 15:14 TD-RID */ 230 #define R0_FS (1U<<9) /* first segment of frame */ 231 #define R0_LS (1U<<8) /* last segment of frame */ 232 #define R0_CSUM (3U<<6) /* 7:6 checksum status */ 233 #define R0_CERR (2U<<6) /* 0 (undone), 1 (found ok), 2 (bad) */ 234 /* R1 frame address 63:32 */ 235 /* R2 frame address 31:0 */ 236 /* R3 31:16 received frame length, 15:0 buffer length to receive */ 237 238 #define MD_NTXSEGS 16 /* fixed */ 239 #define MD_TXQUEUELEN 16 /* tunable */ 240 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1) 241 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4) 242 #define MD_NTXDESC (MD_TXQUEUELEN * MD_NTXSEGS) 243 #define MD_NTXDESC_MASK (MD_NTXDESC - 1) 244 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK) 245 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK) 246 247 #define MD_NRXDESC 64 /* tunable */ 248 #define MD_NRXDESC_MASK (MD_NRXDESC - 1) 249 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK) 250 251 #define SCX_INIT_RXDESC(sc, x) \ 252 do { \ 253 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 254 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 255 struct mbuf *__m = __rxs->rxs_mbuf; \ 256 bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 257 __m->m_data = __m->m_ext.ext_buf; \ 258 __rxd->r3 = __rxs->rxs_dmamap->dm_segs[0].ds_len; \ 259 __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr)); \ 260 __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr)); \ 261 __rxd->r0 = R0_OWN | R0_FS | R0_LS; \ 262 if ((x) == MD_NRXDESC - 1) __rxd->r0 |= R0_EOD; \ 263 } while (/*CONSTCOND*/0) 264 265 struct control_data { 266 struct tdes cd_txdescs[MD_NTXDESC]; 267 struct rdes cd_rxdescs[MD_NRXDESC]; 268 }; 269 #define SCX_CDOFF(x) offsetof(struct control_data, x) 270 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)]) 271 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)]) 272 273 struct scx_txsoft { 274 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 275 bus_dmamap_t txs_dmamap; /* our DMA map */ 276 int txs_firstdesc; /* first descriptor in packet */ 277 int txs_lastdesc; /* last descriptor in packet */ 278 int txs_ndesc; /* # of descriptors used */ 279 }; 280 281 struct scx_rxsoft { 282 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 283 bus_dmamap_t rxs_dmamap; /* our DMA map */ 284 }; 285 286 struct scx_softc { 287 device_t sc_dev; /* generic device information */ 288 bus_space_tag_t sc_st; /* bus space tag */ 289 bus_space_handle_t sc_sh; /* bus space handle */ 290 bus_size_t sc_sz; /* csr map size */ 291 bus_space_handle_t sc_eesh; /* eeprom section handle */ 292 bus_size_t sc_eesz; /* eeprom map size */ 293 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 294 struct ethercom sc_ethercom; /* Ethernet common data */ 295 struct mii_data sc_mii; /* MII */ 296 callout_t sc_tick_ch; /* PHY monitor callout */ 297 bus_dma_segment_t sc_seg; /* descriptor store seg */ 298 int sc_nseg; /* descriptor store nseg */ 299 void *sc_ih; /* interrupt cookie */ 300 int sc_phy_id; /* PHY address */ 301 int sc_flowflags; /* 802.3x PAUSE flow control */ 302 uint32_t sc_mdclk; /* GAR 5:2 clock selection */ 303 uint32_t sc_t0coso; /* T0_CSUM | T0_SGOL to run */ 304 int sc_ucodeloaded; /* ucode for H2M/M2H/PKT */ 305 int sc_100mii; /* 1 for RMII/MII, 0 for RGMII */ 306 int sc_phandle; /* fdt phandle */ 307 308 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 309 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 310 311 struct control_data *sc_control_data; 312 #define sc_txdescs sc_control_data->cd_txdescs 313 #define sc_rxdescs sc_control_data->cd_rxdescs 314 315 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN]; 316 struct scx_rxsoft sc_rxsoft[MD_NRXDESC]; 317 int sc_txfree; /* number of free Tx descriptors */ 318 int sc_txnext; /* next ready Tx descriptor */ 319 int sc_txsfree; /* number of free Tx jobs */ 320 int sc_txsnext; /* next ready Tx job */ 321 int sc_txsdirty; /* dirty Tx jobs */ 322 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 323 324 krndsource_t rnd_source; /* random source */ 325 }; 326 327 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x))) 328 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x))) 329 330 #define SCX_CDTXSYNC(sc, x, n, ops) \ 331 do { \ 332 int __x, __n; \ 333 \ 334 __x = (x); \ 335 __n = (n); \ 336 \ 337 /* If it will wrap around, sync to the end of the ring. */ \ 338 if ((__x + __n) > MD_NTXDESC) { \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 SCX_CDTXOFF(__x), sizeof(struct tdes) * \ 341 (MD_NTXDESC - __x), (ops)); \ 342 __n -= (MD_NTXDESC - __x); \ 343 __x = 0; \ 344 } \ 345 \ 346 /* Now sync whatever is left. */ \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 349 } while (/*CONSTCOND*/0) 350 351 #define SCX_CDRXSYNC(sc, x, ops) \ 352 do { \ 353 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 354 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 355 } while (/*CONSTCOND*/0) 356 357 static int scx_fdt_match(device_t, cfdata_t, void *); 358 static void scx_fdt_attach(device_t, device_t, void *); 359 static int scx_acpi_match(device_t, cfdata_t, void *); 360 static void scx_acpi_attach(device_t, device_t, void *); 361 362 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc), 363 scx_fdt_match, scx_fdt_attach, NULL, NULL); 364 365 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc), 366 scx_acpi_match, scx_acpi_attach, NULL, NULL); 367 368 static void scx_attach_i(struct scx_softc *); 369 static void scx_reset(struct scx_softc *); 370 static int scx_init(struct ifnet *); 371 static void scx_start(struct ifnet *); 372 static void scx_stop(struct ifnet *, int); 373 static void scx_watchdog(struct ifnet *); 374 static int scx_ioctl(struct ifnet *, u_long, void *); 375 static void scx_set_rcvfilt(struct scx_softc *); 376 static int scx_ifmedia_upd(struct ifnet *); 377 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 378 static void mii_statchg(struct ifnet *); 379 static void phy_tick(void *); 380 static int mii_readreg(device_t, int, int, uint16_t *); 381 static int mii_writereg(device_t, int, int, uint16_t); 382 static int scx_intr(void *); 383 static void txreap(struct scx_softc *); 384 static void rxintr(struct scx_softc *); 385 static int add_rxbuf(struct scx_softc *, int); 386 static int spin_waitfor(struct scx_softc *, int, int); 387 static int mac_read(struct scx_softc *, int); 388 static void mac_write(struct scx_softc *, int, int); 389 static void loaducode(struct scx_softc *); 390 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t); 391 392 #define CSR_READ(sc,off) \ 393 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off)) 394 #define CSR_WRITE(sc,off,val) \ 395 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val)) 396 #define EE_READ(sc,off) \ 397 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off)) 398 399 static int 400 scx_fdt_match(device_t parent, cfdata_t cf, void *aux) 401 { 402 static const char * compatible[] = { 403 "socionext,synquacer-netsec", 404 NULL 405 }; 406 struct fdt_attach_args * const faa = aux; 407 408 return of_match_compatible(faa->faa_phandle, compatible); 409 } 410 411 static void 412 scx_fdt_attach(device_t parent, device_t self, void *aux) 413 { 414 struct scx_softc * const sc = device_private(self); 415 struct fdt_attach_args * const faa = aux; 416 const int phandle = faa->faa_phandle; 417 bus_space_tag_t bst = faa->faa_bst; 418 bus_space_handle_t bsh; 419 bus_space_handle_t eebsh; 420 bus_addr_t addr[2]; 421 bus_size_t size[2]; 422 char intrstr[128]; 423 const char *phy_mode; 424 425 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0 426 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) { 427 aprint_error(": unable to map device csr\n"); 428 return; 429 } 430 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 431 aprint_error(": failed to decode interrupt\n"); 432 goto fail; 433 } 434 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 435 NOT_MP_SAFE, scx_intr, sc); 436 if (sc->sc_ih == NULL) { 437 aprint_error_dev(self, "couldn't establish interrupt\n"); 438 goto fail; 439 } 440 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0 441 || bus_space_map(faa->faa_bst, addr[0], size[1], 0, &eebsh) != 0) { 442 aprint_error(": unable to map device eeprom\n"); 443 goto fail; 444 } 445 446 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 447 if (phy_mode == NULL) { 448 aprint_error(": missing 'phy-mode' property\n"); 449 phy_mode = "rgmii"; 450 } 451 452 aprint_naive("\n"); 453 aprint_normal(": Gigabit Ethernet Controller\n"); 454 aprint_normal_dev(self, "interrupt on %s\n", intrstr); 455 456 sc->sc_dev = self; 457 sc->sc_st = bst; 458 sc->sc_sh = bsh; 459 sc->sc_sz = size[0]; 460 sc->sc_eesh = eebsh; 461 sc->sc_eesz = size[1]; 462 sc->sc_dmat = faa->faa_dmat; 463 sc->sc_phandle = phandle; 464 sc->sc_100mii = (strcmp(phy_mode, "rgmii") != 0); 465 466 scx_attach_i(sc); 467 return; 468 fail: 469 if (sc->sc_eesz) 470 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 471 if (sc->sc_sz) 472 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 473 return; 474 } 475 476 static int 477 scx_acpi_match(device_t parent, cfdata_t cf, void *aux) 478 { 479 static const char * compatible[] = { 480 "SCX0001", 481 NULL 482 }; 483 struct acpi_attach_args *aa = aux; 484 485 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 486 return 0; 487 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 488 } 489 490 static void 491 scx_acpi_attach(device_t parent, device_t self, void *aux) 492 { 493 struct scx_softc * const sc = device_private(self); 494 struct acpi_attach_args * const aa = aux; 495 ACPI_HANDLE handle = aa->aa_node->ad_handle; 496 bus_space_tag_t bst = aa->aa_memt; 497 bus_space_handle_t bsh, eebsh; 498 struct acpi_resources res; 499 struct acpi_mem *mem; 500 struct acpi_irq *irq; 501 ACPI_STATUS rv; 502 503 rv = acpi_resource_parse(self, handle, "_CRS", 504 &res, &acpi_resource_parse_ops_default); 505 if (ACPI_FAILURE(rv)) 506 return; 507 mem = acpi_res_mem(&res, 0); 508 irq = acpi_res_irq(&res, 0); 509 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 510 aprint_error(": incomplete csr resources\n"); 511 return; 512 } 513 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &bsh) != 0) { 514 aprint_error(": couldn't map registers\n"); 515 return; 516 } 517 sc->sc_sz = mem->ar_length; 518 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, IPL_NET, 519 NOT_MP_SAFE, scx_intr, sc, device_xname(self)); 520 if (sc->sc_ih == NULL) { 521 aprint_error_dev(self, "couldn't establish interrupt\n"); 522 goto fail; 523 } 524 mem = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */ 525 if (mem == NULL || mem->ar_length == 0) { 526 aprint_error(": incomplete eeprom resources\n"); 527 goto fail; 528 } 529 if (bus_space_map(bst, mem->ar_base, mem->ar_length, 0, &eebsh) != 0) { 530 aprint_error(": couldn't map registers\n"); 531 goto fail; 532 } 533 sc->sc_eesz = mem->ar_length; 534 535 aprint_naive("\n"); 536 aprint_normal(": Gigabit Ethernet Controller\n"); 537 538 sc->sc_dev = self; 539 sc->sc_st = bst; 540 sc->sc_sh = bsh; 541 sc->sc_eesh = eebsh; 542 sc->sc_dmat = aa->aa_dmat64; 543 544 scx_attach_i(sc); 545 546 acpi_resource_cleanup(&res); 547 return; 548 fail: 549 if (sc->sc_eesz > 0) 550 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz); 551 if (sc->sc_sz > 0) 552 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 553 acpi_resource_cleanup(&res); 554 return; 555 } 556 557 static void 558 scx_attach_i(struct scx_softc *sc) 559 { 560 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 561 struct mii_data * const mii = &sc->sc_mii; 562 struct ifmedia * const ifm = &mii->mii_media; 563 uint32_t hwver, phyfreq; 564 uint8_t enaddr[ETHER_ADDR_LEN]; 565 bus_dma_segment_t seg; 566 uint32_t csr; 567 int i, nseg, error = 0; 568 569 hwver = CSR_READ(sc, HWVER1); 570 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0); 571 enaddr[0] = csr >> 24; 572 enaddr[1] = csr >> 16; 573 enaddr[2] = csr >> 8; 574 enaddr[3] = csr; 575 csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4); 576 enaddr[4] = csr >> 24; 577 enaddr[5] = csr >> 16; 578 csr = CSR_READ(sc, GMACIMPL); 579 580 aprint_normal_dev(sc->sc_dev, "NetSec GbE (%d.%d) impl (%x.%x)\n", 581 hwver >> 16, hwver & 0xffff, csr >> 16, csr & 0xffff); 582 aprint_normal_dev(sc->sc_dev, 583 "Ethernet address %s\n", ether_sprintf(enaddr)); 584 585 phyfreq = 0; 586 sc->sc_phy_id = MII_PHY_ANY; 587 sc->sc_mdclk = get_mdioclk(phyfreq); /* 5:2 clk control */ 588 589 sc->sc_flowflags = 0; 590 591 if (sc->sc_ucodeloaded == 0) 592 loaducode(sc); 593 594 mii->mii_ifp = ifp; 595 mii->mii_readreg = mii_readreg; 596 mii->mii_writereg = mii_writereg; 597 mii->mii_statchg = mii_statchg; 598 599 sc->sc_ethercom.ec_mii = mii; 600 ifmedia_init(ifm, 0, scx_ifmedia_upd, scx_ifmedia_sts); 601 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, 602 MII_OFFSET_ANY, MIIF_DOPAUSE); 603 if (LIST_FIRST(&mii->mii_phys) == NULL) { 604 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 605 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 606 } else 607 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 608 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */ 609 610 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 611 ifp->if_softc = sc; 612 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 613 ifp->if_ioctl = scx_ioctl; 614 ifp->if_start = scx_start; 615 ifp->if_watchdog = scx_watchdog; 616 ifp->if_init = scx_init; 617 ifp->if_stop = scx_stop; 618 IFQ_SET_READY(&ifp->if_snd); 619 620 if_attach(ifp); 621 if_deferred_start_init(ifp, NULL); 622 ether_ifattach(ifp, enaddr); 623 624 callout_init(&sc->sc_tick_ch, 0); 625 callout_setfunc(&sc->sc_tick_ch, phy_tick, sc); 626 627 /* 628 * Allocate the control data structures, and create and load the 629 * DMA map for it. 630 */ 631 error = bus_dmamem_alloc(sc->sc_dmat, 632 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 633 if (error != 0) { 634 aprint_error_dev(sc->sc_dev, 635 "unable to allocate control data, error = %d\n", error); 636 goto fail_0; 637 } 638 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 639 sizeof(struct control_data), (void **)&sc->sc_control_data, 640 BUS_DMA_COHERENT); 641 if (error != 0) { 642 aprint_error_dev(sc->sc_dev, 643 "unable to map control data, error = %d\n", error); 644 goto fail_1; 645 } 646 error = bus_dmamap_create(sc->sc_dmat, 647 sizeof(struct control_data), 1, 648 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap); 649 if (error != 0) { 650 aprint_error_dev(sc->sc_dev, 651 "unable to create control data DMA map, " 652 "error = %d\n", error); 653 goto fail_2; 654 } 655 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 656 sc->sc_control_data, sizeof(struct control_data), NULL, 0); 657 if (error != 0) { 658 aprint_error_dev(sc->sc_dev, 659 "unable to load control data DMA map, error = %d\n", 660 error); 661 goto fail_3; 662 } 663 for (i = 0; i < MD_TXQUEUELEN; i++) { 664 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 665 MD_NTXSEGS, MCLBYTES, 0, 0, 666 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 667 aprint_error_dev(sc->sc_dev, 668 "unable to create tx DMA map %d, error = %d\n", 669 i, error); 670 goto fail_4; 671 } 672 } 673 for (i = 0; i < MD_NRXDESC; i++) { 674 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 675 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 676 aprint_error_dev(sc->sc_dev, 677 "unable to create rx DMA map %d, error = %d\n", 678 i, error); 679 goto fail_5; 680 } 681 sc->sc_rxsoft[i].rxs_mbuf = NULL; 682 } 683 sc->sc_seg = seg; 684 sc->sc_nseg = nseg; 685 printf("bus_dmaseg ds_addr %08lx, ds_len %08lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg); 686 687 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 688 pmf_class_network_register(sc->sc_dev, ifp); 689 else 690 aprint_error_dev(sc->sc_dev, 691 "couldn't establish power handler\n"); 692 693 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 694 RND_TYPE_NET, RND_FLAG_DEFAULT); 695 696 return; 697 698 fail_5: 699 for (i = 0; i < MD_NRXDESC; i++) { 700 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 701 bus_dmamap_destroy(sc->sc_dmat, 702 sc->sc_rxsoft[i].rxs_dmamap); 703 } 704 fail_4: 705 for (i = 0; i < MD_TXQUEUELEN; i++) { 706 if (sc->sc_txsoft[i].txs_dmamap != NULL) 707 bus_dmamap_destroy(sc->sc_dmat, 708 sc->sc_txsoft[i].txs_dmamap); 709 } 710 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 711 fail_3: 712 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 713 fail_2: 714 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 715 sizeof(struct control_data)); 716 fail_1: 717 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 718 fail_0: 719 if (sc->sc_phandle) 720 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 721 else 722 acpi_intr_disestablish(sc->sc_ih); 723 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 724 return; 725 } 726 727 static void 728 scx_reset(struct scx_softc *sc) 729 { 730 731 mac_write(sc, GMACBMR, BMR_RST); /* may take for a while */ 732 (void)spin_waitfor(sc, GMACBMR, BMR_RST); 733 734 CSR_WRITE(sc, DESCENG_SRST, 1); 735 CSR_WRITE(sc, DESCENG_INIT, 1); 736 mac_write(sc, GMACBMR, _BMR); 737 mac_write(sc, GMACRDLAR, _RDLAR); 738 mac_write(sc, GMACTDLAR, _TDLAR); 739 mac_write(sc, GMACAFR, _AFR); 740 } 741 742 static int 743 scx_init(struct ifnet *ifp) 744 { 745 struct scx_softc *sc = ifp->if_softc; 746 const uint8_t *ea = CLLADDR(ifp->if_sadl); 747 uint32_t csr; 748 int i; 749 750 /* Cancel pending I/O. */ 751 scx_stop(ifp, 0); 752 753 /* Reset the chip to a known state. */ 754 scx_reset(sc); 755 756 /* build sane Tx and load Rx descriptors with mbuf */ 757 for (i = 0; i < MD_NTXDESC; i++) 758 sc->sc_txdescs[i].t0 = T0_OWN; 759 sc->sc_txdescs[MD_NTXDESC - 1].t0 |= T0_EOD; /* tie off the ring */ 760 for (i = 0; i < MD_NRXDESC; i++) 761 (void)add_rxbuf(sc, i); 762 763 /* set my address in perfect match slot 0 */ 764 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; 765 CSR_WRITE(sc, GMACMAL0, csr); 766 csr = (ea[5] << 8) | ea[4]; 767 CSR_WRITE(sc, GMACMAH0, csr | 1U<<31); /* always valid? */ 768 769 /* accept multicast frame or run promisc mode */ 770 scx_set_rcvfilt(sc); 771 772 (void)scx_ifmedia_upd(ifp); 773 774 /* kick to start GMAC engine */ 775 csr = mac_read(sc, GMACOMR); 776 CSR_WRITE(sc, RXINT_CLR, ~0); 777 CSR_WRITE(sc, TXINT_CLR, ~0); 778 mac_write(sc, GMACOMR, csr | OMR_RXE | OMR_TXE); 779 780 ifp->if_flags |= IFF_RUNNING; 781 ifp->if_flags &= ~IFF_OACTIVE; 782 783 /* start one second timer */ 784 callout_schedule(&sc->sc_tick_ch, hz); 785 786 return 0; 787 } 788 789 static void 790 scx_stop(struct ifnet *ifp, int disable) 791 { 792 struct scx_softc *sc = ifp->if_softc; 793 794 /* Stop the one second clock. */ 795 callout_stop(&sc->sc_tick_ch); 796 797 /* Down the MII. */ 798 mii_down(&sc->sc_mii); 799 800 /* Mark the interface down and cancel the watchdog timer. */ 801 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 802 ifp->if_timer = 0; 803 } 804 805 static void 806 scx_watchdog(struct ifnet *ifp) 807 { 808 struct scx_softc *sc = ifp->if_softc; 809 810 /* 811 * Since we're not interrupting every packet, sweep 812 * up before we report an error. 813 */ 814 txreap(sc); 815 816 if (sc->sc_txfree != MD_NTXDESC) { 817 aprint_error_dev(sc->sc_dev, 818 "device timeout (txfree %d txsfree %d txnext %d)\n", 819 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 820 if_statinc(ifp, if_oerrors); 821 822 /* Reset the interface. */ 823 scx_init(ifp); 824 } 825 826 scx_start(ifp); 827 } 828 829 static int 830 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 831 { 832 struct scx_softc *sc = ifp->if_softc; 833 struct ifreq *ifr = (struct ifreq *)data; 834 struct ifmedia *ifm; 835 int s, error; 836 837 s = splnet(); 838 839 switch (cmd) { 840 case SIOCSIFMEDIA: 841 /* Flow control requires full-duplex mode. */ 842 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 843 (ifr->ifr_media & IFM_FDX) == 0) 844 ifr->ifr_media &= ~IFM_ETH_FMASK; 845 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 846 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 847 /* We can do both TXPAUSE and RXPAUSE. */ 848 ifr->ifr_media |= 849 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 850 } 851 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 852 } 853 ifm = &sc->sc_mii.mii_media; 854 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 855 break; 856 default: 857 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 858 break; 859 860 error = 0; 861 862 if (cmd == SIOCSIFCAP) 863 error = (*ifp->if_init)(ifp); 864 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 865 ; 866 else if (ifp->if_flags & IFF_RUNNING) { 867 /* 868 * Multicast list has changed; set the hardware filter 869 * accordingly. 870 */ 871 scx_set_rcvfilt(sc); 872 } 873 break; 874 } 875 876 splx(s); 877 return error; 878 } 879 880 static void 881 scx_set_rcvfilt(struct scx_softc *sc) 882 { 883 struct ethercom * const ec = &sc->sc_ethercom; 884 struct ifnet * const ifp = &ec->ec_if; 885 struct ether_multistep step; 886 struct ether_multi *enm; 887 uint32_t mchash[8]; /* 8x 32 = 256 bit */ 888 uint32_t csr, crc; 889 int i; 890 891 csr = CSR_READ(sc, GMACAFR); 892 csr &= ~(AFR_PM | AFR_AM | AFR_MHTE); 893 CSR_WRITE(sc, GMACAFR, csr); 894 895 ETHER_LOCK(ec); 896 if (ifp->if_flags & IFF_PROMISC) { 897 ec->ec_flags |= ETHER_F_ALLMULTI; 898 ETHER_UNLOCK(ec); 899 goto update; 900 } 901 ec->ec_flags &= ~ETHER_F_ALLMULTI; 902 903 /* clear 15 entry supplimental perfect match filter */ 904 for (i = 1; i < 16; i++) 905 CSR_WRITE(sc, GMACMAH(i), 0); 906 /* build 256 bit multicast hash filter */ 907 memset(mchash, 0, sizeof(mchash)); 908 crc = 0; 909 910 ETHER_FIRST_MULTI(step, ec, enm); 911 i = 1; /* slot 0 is occupied */ 912 while (enm != NULL) { 913 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 914 /* 915 * We must listen to a range of multicast addresses. 916 * For now, just accept all multicasts, rather than 917 * trying to set only those filter bits needed to match 918 * the range. (At this time, the only use of address 919 * ranges is for IP multicast routing, for which the 920 * range is big enough to require all bits set.) 921 */ 922 ec->ec_flags |= ETHER_F_ALLMULTI; 923 ETHER_UNLOCK(ec); 924 goto update; 925 } 926 printf("[%d] %s\n", i, ether_sprintf(enm->enm_addrlo)); 927 if (i < 16) { 928 /* use 15 entry perfect match filter */ 929 uint32_t addr; 930 uint8_t *ep = enm->enm_addrlo; 931 addr = (ep[3] << 24) | (ep[2] << 16) 932 | (ep[1] << 8) | ep[0]; 933 CSR_WRITE(sc, GMACMAL(i), addr); 934 addr = (ep[5] << 8) | ep[4]; 935 CSR_WRITE(sc, GMACMAH(i), addr | 1U<<31); 936 } else { 937 /* use hash table when too many */ 938 /* bit_reserve_32(~crc) !? */ 939 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 940 /* 3(31:29) 5(28:24) bit sampling */ 941 mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f); 942 } 943 ETHER_NEXT_MULTI(step, enm); 944 i++; 945 } 946 ETHER_UNLOCK(ec); 947 948 if (crc) 949 csr |= AFR_MHTE; 950 for (i = 0; i < __arraycount(mchash); i++) 951 CSR_WRITE(sc, GMACMHT(i), mchash[i]); 952 CSR_WRITE(sc, GMACAFR, csr); 953 return; 954 955 update: 956 /* With PM or AM, MHTE/MHT0-7 are never consulted. really? */ 957 if (ifp->if_flags & IFF_PROMISC) 958 csr |= AFR_PM; /* run promisc. mode */ 959 else 960 csr |= AFR_AM; /* accept all multicast */ 961 CSR_WRITE(sc, GMACAFR, csr); 962 return; 963 } 964 965 static int 966 scx_ifmedia_upd(struct ifnet *ifp) 967 { 968 struct scx_softc *sc = ifp->if_softc; 969 struct ifmedia *ifm = &sc->sc_mii.mii_media; 970 971 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_AUTO) { 972 ; /* restart AN */ 973 ; /* enable AN */ 974 ; /* advertise flow control pause */ 975 ; /* adv. 100FDX,100HDX,10FDX,10HDX */ 976 } else { 977 #if 1 /* XXX not sure to belong here XXX */ 978 uint32_t mcr = mac_read(sc, GMACMCR); 979 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_1000_T) 980 mcr &= ~MCR_USEMII; /* RGMII+SPD1000 */ 981 else { 982 if (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_100_TX 983 && sc->sc_100mii) 984 mcr |= MCR_SPD100; 985 mcr |= MCR_USEMII; 986 } 987 if (ifm->ifm_cur->ifm_media & IFM_FDX) 988 mcr |= MCR_USEFDX; 989 mcr |= MCR_CST | MCR_JE; 990 if (sc->sc_100mii == 0) 991 mcr |= MCR_IBN; 992 mac_write(sc, GMACMCR, mcr); 993 #endif 994 } 995 return 0; 996 } 997 998 static void 999 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1000 { 1001 struct scx_softc *sc = ifp->if_softc; 1002 struct mii_data *mii = &sc->sc_mii; 1003 1004 mii_pollstat(mii); 1005 ifmr->ifm_status = mii->mii_media_status; 1006 ifmr->ifm_active = sc->sc_flowflags | 1007 (mii->mii_media_active & ~IFM_ETH_FMASK); 1008 } 1009 1010 void 1011 mii_statchg(struct ifnet *ifp) 1012 { 1013 struct scx_softc *sc = ifp->if_softc; 1014 struct mii_data *mii = &sc->sc_mii; 1015 uint32_t fcr; 1016 1017 /* Get flow control negotiation result. */ 1018 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1019 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) 1020 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1021 1022 /* Adjust PAUSE flow control. */ 1023 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE); 1024 if (mii->mii_media_active & IFM_FDX) { 1025 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 1026 fcr |= FCR_TFE; 1027 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 1028 fcr |= FCR_RFE; 1029 } 1030 mac_write(sc, GMACFCR, fcr); 1031 1032 printf("%ctxfe, %crxfe\n", 1033 (fcr & FCR_TFE) ? '+' : '-', (fcr & FCR_RFE) ? '+' : '-'); 1034 } 1035 1036 static void 1037 phy_tick(void *arg) 1038 { 1039 struct scx_softc *sc = arg; 1040 struct mii_data *mii = &sc->sc_mii; 1041 int s; 1042 1043 s = splnet(); 1044 mii_tick(mii); 1045 splx(s); 1046 1047 callout_schedule(&sc->sc_tick_ch, hz); 1048 } 1049 1050 static int 1051 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1052 { 1053 struct scx_softc *sc = device_private(self); 1054 uint32_t miia; 1055 int error; 1056 1057 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1058 mac_write(sc, GMACGAR, miia | GAR_BUSY); 1059 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1060 if (error) 1061 return error; 1062 *val = mac_read(sc, GMACGDR); 1063 return 0; 1064 } 1065 1066 static int 1067 mii_writereg(device_t self, int phy, int reg, uint16_t val) 1068 { 1069 struct scx_softc *sc = device_private(self); 1070 uint32_t miia; 1071 uint16_t dummy; 1072 int error; 1073 1074 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk; 1075 mac_write(sc, GMACGDR, val); 1076 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY); 1077 error = spin_waitfor(sc, GMACGAR, GAR_BUSY); 1078 if (error) 1079 return error; 1080 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */ 1081 return 0; 1082 } 1083 1084 static void 1085 scx_start(struct ifnet *ifp) 1086 { 1087 struct scx_softc *sc = ifp->if_softc; 1088 struct mbuf *m0, *m; 1089 struct scx_txsoft *txs; 1090 bus_dmamap_t dmamap; 1091 int error, nexttx, lasttx, ofree, seg; 1092 uint32_t tdes0; 1093 1094 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1095 return; 1096 1097 /* Remember the previous number of free descriptors. */ 1098 ofree = sc->sc_txfree; 1099 1100 /* 1101 * Loop through the send queue, setting up transmit descriptors 1102 * until we drain the queue, or use up all available transmit 1103 * descriptors. 1104 */ 1105 for (;;) { 1106 IFQ_POLL(&ifp->if_snd, m0); 1107 if (m0 == NULL) 1108 break; 1109 1110 if (sc->sc_txsfree < MD_TXQUEUE_GC) { 1111 txreap(sc); 1112 if (sc->sc_txsfree == 0) 1113 break; 1114 } 1115 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1116 dmamap = txs->txs_dmamap; 1117 1118 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1119 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1120 if (error) { 1121 if (error == EFBIG) { 1122 aprint_error_dev(sc->sc_dev, 1123 "Tx packet consumes too many " 1124 "DMA segments, dropping...\n"); 1125 IFQ_DEQUEUE(&ifp->if_snd, m0); 1126 m_freem(m0); 1127 continue; 1128 } 1129 /* Short on resources, just stop for now. */ 1130 break; 1131 } 1132 1133 if (dmamap->dm_nsegs > sc->sc_txfree) { 1134 /* 1135 * Not enough free descriptors to transmit this 1136 * packet. We haven't committed anything yet, 1137 * so just unload the DMA map, put the packet 1138 * back on the queue, and punt. Notify the upper 1139 * layer that there are not more slots left. 1140 */ 1141 ifp->if_flags |= IFF_OACTIVE; 1142 bus_dmamap_unload(sc->sc_dmat, dmamap); 1143 break; 1144 } 1145 1146 IFQ_DEQUEUE(&ifp->if_snd, m0); 1147 1148 /* 1149 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1150 */ 1151 1152 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1153 BUS_DMASYNC_PREWRITE); 1154 1155 tdes0 = 0; /* to postpone 1st segment T0_OWN write */ 1156 lasttx = -1; 1157 for (nexttx = sc->sc_txnext, seg = 0; 1158 seg < dmamap->dm_nsegs; 1159 seg++, nexttx = MD_NEXTTX(nexttx)) { 1160 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 1161 bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr; 1162 /* 1163 * If this is the first descriptor we're 1164 * enqueueing, don't set the OWN bit just 1165 * yet. That could cause a race condition. 1166 * We'll do it below. 1167 */ 1168 tdes->t3 = dmamap->dm_segs[seg].ds_len; 1169 tdes->t2 = htole32(BUS_ADDR_LO32(paddr)); 1170 tdes->t1 = htole32(BUS_ADDR_HI32(paddr)); 1171 tdes->t0 = tdes0 | (tdes->t0 & T0_EOD) | 1172 (15 << T0_TRID) | T0_PT | 1173 sc->sc_t0coso | T0_TRS; 1174 tdes0 = T0_OWN; /* 2nd and other segments */ 1175 lasttx = nexttx; 1176 } 1177 /* 1178 * Outgoing NFS mbuf must be unloaded when Tx completed. 1179 * Without T1_IC NFS mbuf is left unack'ed for excessive 1180 * time and NFS stops to proceed until scx_watchdog() 1181 * calls txreap() to reclaim the unack'ed mbuf. 1182 * It's painful to traverse every mbuf chain to determine 1183 * whether someone is waiting for Tx completion. 1184 */ 1185 m = m0; 1186 do { 1187 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 1188 sc->sc_txdescs[lasttx].t0 |= T0_IOC; /* !!! */ 1189 break; 1190 } 1191 } while ((m = m->m_next) != NULL); 1192 1193 /* Write deferred 1st segment T0_OWN at the final stage */ 1194 sc->sc_txdescs[lasttx].t0 |= T0_LS; 1195 sc->sc_txdescs[sc->sc_txnext].t0 |= (T0_FS | T0_OWN); 1196 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1197 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1198 1199 /* Tell DMA start transmit */ 1200 /* CSR_WRITE(sc, MDTSC, 1); */ 1201 1202 txs->txs_mbuf = m0; 1203 txs->txs_firstdesc = sc->sc_txnext; 1204 txs->txs_lastdesc = lasttx; 1205 txs->txs_ndesc = dmamap->dm_nsegs; 1206 1207 sc->sc_txfree -= txs->txs_ndesc; 1208 sc->sc_txnext = nexttx; 1209 sc->sc_txsfree--; 1210 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext); 1211 /* 1212 * Pass the packet to any BPF listeners. 1213 */ 1214 bpf_mtap(ifp, m0, BPF_D_OUT); 1215 } 1216 1217 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1218 /* No more slots left; notify upper layer. */ 1219 ifp->if_flags |= IFF_OACTIVE; 1220 } 1221 if (sc->sc_txfree != ofree) { 1222 /* Set a watchdog timer in case the chip flakes out. */ 1223 ifp->if_timer = 5; 1224 } 1225 } 1226 1227 static int 1228 scx_intr(void *arg) 1229 { 1230 struct scx_softc *sc = arg; 1231 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1232 1233 (void)ifp; 1234 rxintr(sc); 1235 txreap(sc); 1236 return 1; 1237 } 1238 1239 static void 1240 txreap(struct scx_softc *sc) 1241 { 1242 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1243 struct scx_txsoft *txs; 1244 uint32_t txstat; 1245 int i; 1246 1247 ifp->if_flags &= ~IFF_OACTIVE; 1248 1249 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN; 1250 i = MD_NEXTTXS(i), sc->sc_txsfree++) { 1251 txs = &sc->sc_txsoft[i]; 1252 1253 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1254 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1255 1256 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1257 if (txstat & T0_OWN) /* desc is still in use */ 1258 break; 1259 1260 /* There is no way to tell transmission status per frame */ 1261 1262 if_statinc(ifp, if_opackets); 1263 1264 sc->sc_txfree += txs->txs_ndesc; 1265 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1266 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1267 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1268 m_freem(txs->txs_mbuf); 1269 txs->txs_mbuf = NULL; 1270 } 1271 sc->sc_txsdirty = i; 1272 if (sc->sc_txsfree == MD_TXQUEUELEN) 1273 ifp->if_timer = 0; 1274 } 1275 1276 static void 1277 rxintr(struct scx_softc *sc) 1278 { 1279 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1280 struct scx_rxsoft *rxs; 1281 struct mbuf *m; 1282 uint32_t rxstat; 1283 int i, len; 1284 1285 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) { 1286 rxs = &sc->sc_rxsoft[i]; 1287 1288 SCX_CDRXSYNC(sc, i, 1289 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1290 1291 rxstat = sc->sc_rxdescs[i].r0; 1292 if (rxstat & R0_OWN) /* desc is left empty */ 1293 break; 1294 1295 /* R0_FS | R0_LS must have been marked for this desc */ 1296 1297 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1298 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1299 1300 len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */ 1301 len -= ETHER_CRC_LEN; /* Trim CRC off */ 1302 m = rxs->rxs_mbuf; 1303 1304 if (add_rxbuf(sc, i) != 0) { 1305 if_statinc(ifp, if_ierrors); 1306 SCX_INIT_RXDESC(sc, i); 1307 bus_dmamap_sync(sc->sc_dmat, 1308 rxs->rxs_dmamap, 0, 1309 rxs->rxs_dmamap->dm_mapsize, 1310 BUS_DMASYNC_PREREAD); 1311 continue; 1312 } 1313 1314 m_set_rcvif(m, ifp); 1315 m->m_pkthdr.len = m->m_len = len; 1316 1317 if (rxstat & R0_CSUM) { 1318 uint32_t csum = M_CSUM_IPv4; 1319 if (rxstat & R0_CERR) 1320 csum |= M_CSUM_IPv4_BAD; 1321 m->m_pkthdr.csum_flags |= csum; 1322 } 1323 if_percpuq_enqueue(ifp->if_percpuq, m); 1324 } 1325 sc->sc_rxptr = i; 1326 } 1327 1328 static int 1329 add_rxbuf(struct scx_softc *sc, int i) 1330 { 1331 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i]; 1332 struct mbuf *m; 1333 int error; 1334 1335 MGETHDR(m, M_DONTWAIT, MT_DATA); 1336 if (m == NULL) 1337 return ENOBUFS; 1338 1339 MCLGET(m, M_DONTWAIT); 1340 if ((m->m_flags & M_EXT) == 0) { 1341 m_freem(m); 1342 return ENOBUFS; 1343 } 1344 1345 if (rxs->rxs_mbuf != NULL) 1346 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1347 1348 rxs->rxs_mbuf = m; 1349 1350 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1351 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1352 if (error) { 1353 aprint_error_dev(sc->sc_dev, 1354 "can't load rx DMA map %d, error = %d\n", i, error); 1355 panic("add_rxbuf"); 1356 } 1357 1358 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1359 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1360 SCX_INIT_RXDESC(sc, i); 1361 1362 return 0; 1363 } 1364 1365 static int 1366 spin_waitfor(struct scx_softc *sc, int reg, int exist) 1367 { 1368 int val, loop; 1369 1370 val = CSR_READ(sc, reg); 1371 if ((val & exist) == 0) 1372 return 0; 1373 loop = 3000; 1374 do { 1375 DELAY(10); 1376 val = CSR_READ(sc, reg); 1377 } while (--loop > 0 && (val & exist)); 1378 return (loop > 0) ? 0 : ETIMEDOUT; 1379 } 1380 1381 static int 1382 mac_read(struct scx_softc *sc, int reg) 1383 { 1384 1385 CSR_WRITE(sc, MACCMD, reg); 1386 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1387 return CSR_READ(sc, MACDATA); 1388 } 1389 1390 static void 1391 mac_write(struct scx_softc *sc, int reg, int val) 1392 { 1393 1394 CSR_WRITE(sc, MACDATA, val); 1395 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR); 1396 (void)spin_waitfor(sc, MACCMD, CMD_BUSY); 1397 } 1398 1399 static int 1400 get_mdioclk(uint32_t freq) 1401 { 1402 1403 const struct { 1404 uint16_t freq, bit; /* GAR 5:2 MDIO frequency selection */ 1405 } mdioclk[] = { 1406 { 35, 2 }, /* 25-35 MHz */ 1407 { 60, 3 }, /* 35-60 MHz */ 1408 { 100, 0 }, /* 60-100 MHz */ 1409 { 150, 1 }, /* 100-150 MHz */ 1410 { 250, 4 }, /* 150-250 MHz */ 1411 { 300, 5 }, /* 250-300 MHz */ 1412 }; 1413 int i; 1414 1415 /* convert MDIO clk to a divisor value */ 1416 if (freq < mdioclk[0].freq) 1417 return mdioclk[0].bit; 1418 for (i = 1; i < __arraycount(mdioclk); i++) { 1419 if (freq < mdioclk[i].freq) 1420 return mdioclk[i-1].bit; 1421 } 1422 return mdioclk[__arraycount(mdioclk) - 1].bit << GAR_CTL; 1423 } 1424 1425 static void 1426 loaducode(struct scx_softc *sc) 1427 { 1428 uint32_t up, lo, sz; 1429 uint64_t addr; 1430 1431 sc->sc_ucodeloaded = 1; 1432 1433 up = EE_READ(sc, 0x08); /* H->M ucode addr high */ 1434 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */ 1435 sz = EE_READ(sc, 0x10); /* H->M ucode size */ 1436 sz *= 4; 1437 addr = ((uint64_t)up << 32) | lo; 1438 aprint_normal_dev(sc->sc_dev, "H2M ucode %u\n", sz); 1439 injectucode(sc, H2MENG, (bus_addr_t)addr, (bus_size_t)sz); 1440 1441 up = EE_READ(sc, 0x14); /* M->H ucode addr high */ 1442 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */ 1443 sz = EE_READ(sc, 0x1c); /* M->H ucode size */ 1444 sz *= 4; 1445 addr = ((uint64_t)up << 32) | lo; 1446 injectucode(sc, M2HENG, (bus_addr_t)addr, (bus_size_t)sz); 1447 aprint_normal_dev(sc->sc_dev, "M2H ucode %u\n", sz); 1448 1449 lo = EE_READ(sc, 0x20); /* PKT ucode addr */ 1450 sz = EE_READ(sc, 0x24); /* PKT ucode size */ 1451 sz *= 4; 1452 injectucode(sc, PKTENG, (bus_addr_t)lo, (bus_size_t)sz); 1453 aprint_normal_dev(sc->sc_dev, "PKT ucode %u\n", sz); 1454 } 1455 1456 static void 1457 injectucode(struct scx_softc *sc, int port, 1458 bus_addr_t addr, bus_size_t size) 1459 { 1460 bus_space_handle_t bsh; 1461 bus_size_t off; 1462 uint32_t ucode; 1463 1464 if (!bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) { 1465 aprint_error_dev(sc->sc_dev, 1466 "eeprom map failure for ucode port 0x%x\n", port); 1467 return; 1468 } 1469 for (off = 0; off < size; off += 4) { 1470 ucode = bus_space_read_4(sc->sc_st, bsh, off); 1471 CSR_WRITE(sc, port, ucode); 1472 } 1473 bus_space_unmap(sc->sc_st, bsh, size); 1474 } 1475
Indexes created Fri Sep 26 20:09:58 GMT 2025